coreboot-gerrit April 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 175ad4a AMD Thatcher: ConnectorTypeDP supports both DP and HDMI
by gerrit＠coreboot.org 23 Apr '13

23 Apr '13

the following patch was just integrated into master: commit 175ad4aa6eca2d7f884745959bd175b37c5ffc31 Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Mon Apr 15 17:58:57 2013 +0800 AMD Thatcher: ConnectorTypeDP supports both DP and HDMI It seems that ConnectorTypeDP in DdiList supports both DP and HDMI monitors. I tested by DP monitor and HDMI monitor connected by passive DP->HDMI adapter. Video and audio are OK. Hot plugging is also supported. This commit partially reverts commit >AMD Thatcher: Fix PCIE link issues< (7f23aeb0) [1]. [1] http://review.coreboot.org/3011 Change-Id: I23cf1c69a8274f47daf56f1a12aafd88bad4a128 Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Reviewed-on: http://review.coreboot.org/3088 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Apr 23 08:44:22 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Apr 23 17:35:26 2013, giving +2 See http://review.coreboot.org/3088 for details. -gerrit

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New patch to review for coreboot: 565e2f7 x86: use proper types for interrupt callbacks
by Aaron Durbin 23 Apr '13

23 Apr '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3124 -gerrit commit 565e2f74b4d4d10d45c0a051149a5b604743d2cd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 23 10:25:34 2013 -0500 x86: use proper types for interrupt callbacks The mainboard_interrupt_handlers() argument for the function pointer was using void * as the type. This does not allow the compiler to catch type differences for the arguments. Thus, some code has been committed which violates the new interrupt callbacks not taking any arguments. Make sure the compiler provides a type checking benefit. Change-Id: I268ec8e16929080955751ef518d65b91895e4308 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/include/arch/interrupt.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/include/arch/interrupt.h b/src/arch/x86/include/arch/interrupt.h index 8c9b4a9..afe5617 100644 --- a/src/arch/x86/include/arch/interrupt.h +++ b/src/arch/x86/include/arch/interrupt.h @@ -23,9 +23,9 @@ /* setup interrupt handlers for mainboard */ #if CONFIG_PCI_OPTION_ROM_RUN_REALMODE -extern void mainboard_interrupt_handlers(int intXX, void *intXX_func); +extern void mainboard_interrupt_handlers(int intXX, void (*intXX_func)(void)); #elif CONFIG_PCI_OPTION_ROM_RUN_YABEL #include <device/oprom/yabel/biosemu.h> #else -static inline void mainboard_interrupt_handlers(int intXX, void *intXX_func) { } +static inline void mainboard_interrupt_handlers(int intXX, void (*intXX_func)(void)) { } #endif

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Patch set updated for coreboot: 8605a03 Intel 82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2
by Paul Menzel 23 Apr '13

23 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3122 -gerrit commit 8605a032dfb371952b96380ec94b424170c9917b Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 13:00:34 2013 +0200 Intel 82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2 Commit »Support for the Intel ICH7 southbridge.« (debb11fc) [1] used `1 << 25` to set the I/O APIC ID of 2. Instead using `2 << 24`, which is the same value, makes it clear, that the I/O APIC ID is 2. Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2« (8c937c7e) [2] is used as a template. [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=debb11fc1fe5f55… [2] http://review.coreboot.org/3100 Change-Id: Ib688500944cd78a1cc1c8082bb138fa9468bdbfb Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/i82801gx/lpc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 3a94e84..777a6d7 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -52,12 +52,12 @@ static void i82801gx_enable_apic(struct device *dev) pci_write_config8(dev, ACPI_CNTL, ACPI_EN); *ioapic_index = 0; - *ioapic_data = (1 << 25); + *ioapic_data = (2 << 24); *ioapic_index = 0; reg32 = *ioapic_data; printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) + if (reg32 != (2 << 24)) die("APIC Error\n"); printk(BIOS_SPEW, "Dumping IOAPIC registers\n");

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Patch set updated for coreboot: b8fa838 Intel 82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2
by Paul Menzel 23 Apr '13

23 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3122 -gerrit commit b8fa8380d68125dcb892fc1fa61156e72760be3b Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 13:00:34 2013 +0200 Intel 82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2 Commit »Support for the Intel ICH7 southbridge.« (debb11fc) [1] used `1 << 25` to set the I/O APIC ID of 2. Instead using `2 << 24`, which is the same value, makes it clear, that the I/O APIC ID is 2. Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2« (8c937c7e) [2] is used as a template. [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=debb11fc1fe5f55… [2] http://review.coreboot.org/3100 Change-Id: Ib688500944cd78a1cc1c8082bb138fa9468bdbfb Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/i82801gx/lpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 3a94e84..a4dd523 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -52,7 +52,7 @@ static void i82801gx_enable_apic(struct device *dev) pci_write_config8(dev, ACPI_CNTL, ACPI_EN); *ioapic_index = 0; - *ioapic_data = (1 << 25); + *ioapic_data = (2 << 24); *ioapic_index = 0; reg32 = *ioapic_data;

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Patch set updated for coreboot: 1047dc1 Intel i82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2
by Paul Menzel 23 Apr '13

23 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3122 -gerrit commit 1047dc1668c72b18bc39c33bbf8efbebd0ee59ec Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 13:00:34 2013 +0200 Intel i82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2 Commit »Support for the Intel ICH7 southbridge.« (debb11fc) [1] used `1 << 25` to set the I/O APIC ID of 2. Instead using `2 << 24`, which is the same value, makes it clear, that the I/O APIC ID is 2. Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2« (8c937c7e) [2] is used as a template. [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=debb11fc1fe5f55… [2] http://review.coreboot.org/3100 Change-Id: Ib688500944cd78a1cc1c8082bb138fa9468bdbfb Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/i82801gx/lpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 3a94e84..a4dd523 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -52,7 +52,7 @@ static void i82801gx_enable_apic(struct device *dev) pci_write_config8(dev, ACPI_CNTL, ACPI_EN); *ioapic_index = 0; - *ioapic_data = (1 << 25); + *ioapic_data = (2 << 24); *ioapic_index = 0; reg32 = *ioapic_data;

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New patch to review for coreboot: 365a87c Intel Lynx Point: Use 2 << 24 to clarify that I/O APIC ID is 2
by Paul Menzel 23 Apr '13

23 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3123 -gerrit commit 365a87c6b51fd919e29709d07a153daeae07ef1b Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 13:00:34 2013 +0200 Intel Lynx Point: Use 2 << 24 to clarify that I/O APIC ID is 2 Commit »haswell: Add initial support for Haswell platforms« (76c3700f) [1] used `1 << 25` to set the I/O APIC ID of 2. Instead using `2 << 24`, which is the same value, makes it clear, that the I/O APIC ID is 2. Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2« (8c937c7e) [2] is used as a template. [1] http://review.coreboot.org/2616 [2] http://review.coreboot.org/3100 Change-Id: I28f9e90856157b4fdd9a1e781472cc4f51d25ece Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/lynxpoint/lpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index f6c64c5..40e0468 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -56,7 +56,7 @@ static void pch_enable_apic(struct device *dev) pci_write_config8(dev, ACPI_CNTL, 0x80); *ioapic_index = 0; - *ioapic_data = (1 << 25); + *ioapic_data = (2 << 24); /* affirm full set of redirection table entries ("write once") */ *ioapic_index = 1;

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New patch to review for coreboot: 456b8ab Intel i82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2
by Paul Menzel 23 Apr '13

23 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3122 -gerrit commit 456b8abde777b3c571ffb0b2821f0d78cc014f12 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 13:00:34 2013 +0200 Intel i82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2 Commit »Support for the Intel ICH7 southbridge.« (debb11fc) [1] used `1 << 25` to set the I/O APIC ID of 2. Instead using `2 << 24`, which is the same value, makes it clear, that the I/O APIC ID is 2. Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2« (8c937c7e) is used as a template. [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=debb11fc1fe5f55… [2] http://review.coreboot.org/3100 Change-Id: Ib688500944cd78a1cc1c8082bb138fa9468bdbfb Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/i82801gx/lpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 3a94e84..a4dd523 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -52,7 +52,7 @@ static void i82801gx_enable_apic(struct device *dev) pci_write_config8(dev, ACPI_CNTL, ACPI_EN); *ioapic_index = 0; - *ioapic_data = (1 << 25); + *ioapic_data = (2 << 24); *ioapic_index = 0; reg32 = *ioapic_data;

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Patch set updated for coreboot: c4ab1f7 AMD Thatcher: ConnectorTypeDP supports both DP and HDMI
by Siyuan Wang 23 Apr '13

23 Apr '13

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3088 -gerrit commit c4ab1f70cd1d47bd97702a723a92f7b506d7f8ed Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Mon Apr 15 17:58:57 2013 +0800 AMD Thatcher: ConnectorTypeDP supports both DP and HDMI It seems that ConnectorTypeDP in DdiList supports both DP and HDMI monitors. I tested by DP monitor and HDMI monitor connected by passive DP->HDMI adapter. Video and audio are OK. Hot plugging is also supported. This commit partially reverts commit >AMD Thatcher: Fix PCIE link issues< (7f23aeb0) [1]. [1] http://review.coreboot.org/3011 Change-Id: I23cf1c69a8274f47daf56f1a12aafd88bad4a128 Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> --- src/mainboard/amd/thatcher/PlatformGnbPcie.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcie.c b/src/mainboard/amd/thatcher/PlatformGnbPcie.c index ade2840..153b13d 100644 --- a/src/mainboard/amd/thatcher/PlatformGnbPcie.c +++ b/src/mainboard/amd/thatcher/PlatformGnbPcie.c @@ -23,7 +23,6 @@ #include "heapManager.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" -#include "Fch.h" #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -80,19 +79,19 @@ PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_DDI_DESCRIPTOR DdiList [] = { // DP0 to HDMI0/DP0 { - 1, + 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) }, // DP1 to HDMI1/DP1 { - 1, + 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) }, // DP2 to MINI-DDI Card { - 1, + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3) }, @@ -130,7 +129,6 @@ OemCustomizeInitEarly ( VOID *TrinityPcieComplexListPtr; VOID *TrinityPciePortPtr; VOID *TrinityPcieDdiPtr; - UINT8 Value; ALLOCATE_HEAP_PARAMS AllocHeapParams; @@ -177,13 +175,6 @@ OemCustomizeInitEarly ( LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); - - LibAmdMemRead (AccessWidth8, ACPI_MMIO_BASE + GPIO_BASE + 50, &Value, &InitEarly->StdHeader); - if (!(Value & 0x80)) - DdiList[0].Ddi.ConnectorType = ConnectorTypeHDMI; - LibAmdMemRead (AccessWidth8, ACPI_MMIO_BASE + GPIO_BASE + 51, &Value, &InitEarly->StdHeader); - if (!(Value & 0x80)) - DdiList[1].Ddi.ConnectorType = ConnectorTypeHDMI; LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 3, &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr;

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Patch merged into coreboot/master: 2810afa GOOGLE/SNOW: get graphics working
by gerrit＠coreboot.org 23 Apr '13

23 Apr '13

the following patch was just integrated into master: commit 2810afa57de26871c99e1c5bb7b3c2fbdcaf4f98 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Apr 18 18:09:24 2013 -0700 GOOGLE/SNOW: get graphics working This adds support for display bring-up on Snow. It includes framebuffer initialization and LCD enable functions. Change-Id: I16e711c97e9d02c916824f621e2313297448732b Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/3116 Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Tue Apr 23 03:42:37 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Apr 23 04:41:23 2013, giving +2 See http://review.coreboot.org/3116 for details. -gerrit

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Patch merged into coreboot/master: 2c88cc0 Intel microcode: Return when `microcode_updates` is `NULL`
by gerrit＠coreboot.org 23 Apr '13

23 Apr '13

the following patch was just integrated into master: commit 2c88cc0696be2b01ebd4df6f7593d8658c8fe419 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Mar 30 12:04:23 2013 +0100 Intel microcode: Return when `microcode_updates` is `NULL` Add a safety check in function `intel_update_microcode` to return when accidentally `NULL` is passed as `microcode_updates`, which would lead to a null pointer dereference later on. for (c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { While at it, use `return NULL` for clarity in function `intel_microcode_find` and include the header file `stddef.h`. for it. The review of this patch had some more discussion on adding more comments and more detailed error messages. But this should be done in a separate patch. For clarity here some history, on how this was found and what caused the discussion and confusion. Originally when Vladimir made this improvement, selecting `CPU_MICROCODE_IN_CBFS` in Kconfig but not having the microcode blob `cpu_microcode_blob.bin` in CBFS resulted in a null pointer dereference later on causing a crash. for (c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { Vladimir fixed this by returning if `microcode_updates` is `NULL`, that means no file is found and successfully tested this on his Lenovo X201. When pushing the patch to Gerrit for review, the code was rewritten though by Aaron in commit »intel microcode: split up microcode loading stages« (98ffb426) [1], which also returns when no file is found. So the other parts of the code were checked and the safety check as described above is added. [1] http://review.coreboot.org/2778 Change-Id: I6e18fd37256910bf047061e4633a66cf29ad7b69 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2990 Reviewed-by: Aaron Durbin <adurbin(a)google.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Mon Apr 22 15:45:37 2013, giving +1 See http://review.coreboot.org/2990 for details. -gerrit

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coreboot-gerrit April 2013