coreboot-gerrit April 2013

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Patch merged into coreboot/master: c0c620e superiotool: add CR dump for W83627UHG = NCT6627UD
by gerrit＠coreboot.org 22 Apr '13

22 Apr '13

the following patch was just integrated into master: commit c0c620e74ab4578ac8bd8ca80c7265fc4c62a37c Author: Frank Rysanek <Frantisek.Rysanek(a)post.cz> Date: Fri Apr 5 10:44:10 2013 +0200 superiotool: add CR dump for W83627UHG = NCT6627UD This commit adds "register dump capability" to superiotool for a specific chip by Winbond/Nuvoton: the W83627UHG AKA NCT6627UD (same chip, different package). In other words, it fills in the "CR map" definitions in winbond.c, which so far have been void for this chip. - superiotool r4.0-3976-g190011e Found Winbond W83627UHG = NCT6627UD (id=0xa2, rev=0x32) at 0x2e Register dump: idx 02 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f val ff a2 32 ff f0 44 00 00 ff 00 00 00 00 03 00 00 ff def 00 a2 NA ff f0 MM 00 MM RR 00 00 00 00 02 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val 00 00 00 00 02 8e 00 ff 00 00 def 01 03 f0 06 02 8e 00 ff 00 00 LDN 0x01 (Parallel port) idx 30 60 61 70 74 f0 val 00 03 78 0c 04 3f def 01 03 78 07 04 3f LDN 0x02 (UART A) idx 30 60 61 70 f0 val 01 03 f8 04 00 def 01 03 f8 04 00 LDN 0x03 (UART B) idx 30 60 61 70 f0 f1 val 01 02 f8 03 00 44 def 01 02 f8 03 00 00 LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 72 f0 val 01 00 60 00 64 01 0c 82 def 01 00 60 00 64 01 0c 83 LDN 0x06 (UART C) idx 30 60 61 70 f0 val 01 03 e8 05 80 def 01 03 e0 04 00 LDN 0x07 (GPIO 3, GPIO 4) idx 30 e0 e1 e2 e3 e4 e5 e6 e7 val 04 ff ff ff ff ff ff ff ff def 00 ff 00 00 00 ff 00 00 00 LDN 0x08 (WDTO#, PLED, GPIO 5,6 & GPIO Base Address) idx 30 60 61 e0 e1 e2 e3 e4 e5 e6 e7 f5 f6 f7 val 01 00 00 ff ff ff ff ff ff ff ff 02 00 00 def 02 00 00 ff 00 00 00 ff 1f 00 00 00 00 00 LDN 0x09 (GPIO 1, GPIO 2 and SUSLED) idx 30 e0 e1 e2 e3 e4 e5 e6 e7 f3 val 02 ff ff ff ff 00 ff 00 00 00 def 00 ff 00 00 00 ff 00 00 00 00 LDN 0x0a (ACPI) idx 30 70 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f2 f3 f4 f6 f7 fe val 01 00 01 00 0a 00 00 00 0c 00 09 00 01 00 00 00 00 00 def 00 00 01 00 ff 08 00 00 1c 00 RR RR 3e 00 00 00 00 00 LDN 0x0b (Hardware monitor) idx 30 60 61 70 f0 f1 f2 val 01 02 48 00 81 ff 81 def 00 00 00 00 RR RR 00 LDN 0x0c (PECI, SST) idx e0 e1 e2 e3 e4 e5 e6 e7 e8 f1 f2 f3 fe ff val 00 48 48 48 48 00 00 00 00 4c 50 10 23 5a def 00 48 48 48 48 00 RR RR 00 48 50 10 23 5a LDN 0x0d (UART D) idx 30 60 61 70 f0 val 00 00 00 00 00 def 00 02 e0 03 00 LDN 0x0e (UART E) idx 30 60 61 70 f0 val 00 00 00 00 80 def 00 03 e8 04 00 LDN 0x0f (UART F) idx 30 60 61 70 f0 val 01 02 38 0a 00 def 00 02 e8 03 00 Change-Id: I834f8767b29f3148f353004edb22cfd7db5ddd56 Signed-off-by: Frank Rysanek <Frantisek.Rysanek(a)post.cz> Reviewed-on: http://review.coreboot.org/3027 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Apr 5 13:22:55 2013, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Mon Apr 22 17:07:12 2013, giving +2 See http://review.coreboot.org/3027 for details. -gerrit

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Patch set updated for coreboot: 70aed62 Intel microcode: Return when `microcode_updates` is `NULL`
by Paul Menzel 22 Apr '13

22 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2990 -gerrit commit 70aed6232764e3f9c9231e648db19fb50c2b55c2 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Mar 30 12:04:23 2013 +0100 Intel microcode: Return when `microcode_updates` is `NULL` Add a safety check in function `intel_update_microcode` to return when accidentally `NULL` is passed as `microcode_updates`, which would lead to a null pointer dereference later on. for (c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { While at it, use `return NULL` for clarity in function `intel_microcode_find` and include the header file `stddef.h`. for it. The review of this patch had some more discussion on adding more comments and more detailed error messages. But this should be done in a separate patch. For clarity here some history, on how this was found and what caused the discussion and confusion. Originally when Vladimir made this improvement, selecting `CPU_MICROCODE_IN_CBFS` in Kconfig but not having the microcode blob `cpu_microcode_blob.bin` in CBFS resulted in a null pointer dereference later on causing a crash. for (c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { Vladimir fixed this by returning if `microcode_updates` is `NULL`, that means no file is found and successfully tested this on his Lenovo X201. When pushing the patch to Gerrit for review, the code was rewritten though by Aaron in commit »intel microcode: split up microcode loading stages« (98ffb426) [1], which also returns when no file is found. So the other parts of the code were checked and the safety check as described above is added. [1] http://review.coreboot.org/2778 Change-Id: I6e18fd37256910bf047061e4633a66cf29ad7b69 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/intel/microcode/microcode.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index d908c25..1991ed8 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -21,6 +21,7 @@ /* Microcode update for Intel PIII and later CPUs */ #include <stdint.h> +#include <stddef.h> #if !defined(__ROMCC__) #include <console/console.h> #endif @@ -131,7 +132,7 @@ const void *intel_microcode_find(void) #endif if (!microcode_updates) - return microcode_updates; + return NULL; /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ msr.lo = 0; @@ -202,6 +203,13 @@ void intel_update_microcode(const void *microcode_updates) const char *c; msr_t msr; + if (!microcode_updates) { +#if !defined(__ROMCC__) + printk(BIOS_WARNING, "No microcode updates found.\n"); +#endif + return; + } + /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ msr.lo = 0; msr.hi = 0;

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Patch set updated for coreboot: 3d4d935 crossgcc: update to gcc 4.7.3
by Idwer Vollering 22 Apr '13

22 Apr '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3112 -gerrit commit 3d4d93543dcdeb3b033b4d38c0a54515b1c83ba9 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Fri Apr 19 00:56:57 2013 +0200 crossgcc: update to gcc 4.7.3 Update crossgcc to use gcc 4.7.3 The resulting coreboot.rom is not runtime tested (any volunteers?). Drop the texinfo patch, rename the armv7a patch. Some Linux distributions have moved on to gcc 4.8, under certain circumstances this version can't (cross-)compile gcc 4.7.2 Bug report: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56927 Change-Id: Id8ce5f86c34e1a0900d44dc6ae4e81cb9548ecc2 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- util/crossgcc/buildgcc | 6 +- util/crossgcc/patches/gcc-4.7.2_armv7a.patch | 12 ---- util/crossgcc/patches/gcc-4.7.2_texinfo.patch | 98 --------------------------- util/crossgcc/patches/gcc-4.7.3_armv7a.patch | 12 ++++ 4 files changed, 15 insertions(+), 113 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index be8d1f2..7d416c2 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -20,8 +20,8 @@ # Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA # -CROSSGCC_DATE="December 4th, 2012" -CROSSGCC_VERSION="1.20" +CROSSGCC_DATE="April 19th, 2013" +CROSSGCC_VERSION="1.21" # default settings TARGETDIR=`pwd`/xgcc @@ -33,7 +33,7 @@ GMP_VERSION=5.0.5 MPFR_VERSION=3.1.1 MPC_VERSION=1.0.1 LIBELF_VERSION=0.8.13 -GCC_VERSION=4.7.2 +GCC_VERSION=4.7.3 GCC_AUTOCONF_VERSION=2.64 BINUTILS_VERSION=2.23 GDB_VERSION=7.5 diff --git a/util/crossgcc/patches/gcc-4.7.2_armv7a.patch b/util/crossgcc/patches/gcc-4.7.2_armv7a.patch deleted file mode 100644 index 82e6609..0000000 --- a/util/crossgcc/patches/gcc-4.7.2_armv7a.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -ur gcc-4.7.2/config.sub gcc-4.7.2/config.sub ---- gcc-4.7.2/config.sub 2012-08-06 07:34:27.000000000 -0700 -+++ gcc-4.7.2/config.sub 2012-12-04 15:03:30.813137430 -0800 -@@ -250,7 +250,7 @@ - | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ - | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ - | am33_2.0 \ -- | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ -+ | arc | arm | arm[bl]e | arme[lb] | armv* | armv[345][lb] | avr | avr32 \ - | be32 | be64 \ - | bfin \ - | c4x | clipper \ diff --git a/util/crossgcc/patches/gcc-4.7.2_texinfo.patch b/util/crossgcc/patches/gcc-4.7.2_texinfo.patch deleted file mode 100644 index 34c6a68..0000000 --- a/util/crossgcc/patches/gcc-4.7.2_texinfo.patch +++ /dev/null @@ -1,98 +0,0 @@ -diff -urp gcc-4.7.2/gcc/doc/cppopts.texi gcc-4.7.2/gcc/doc/cppopts.texi ---- gcc-4.7.2/gcc/doc/cppopts.texi 2013-03-28 13:41:01.000000000 +0100 -+++ gcc-4.7.2/gcc/doc/cppopts.texi 2013-03-28 13:55:05.000000000 +0100 -@@ -803,7 +803,7 @@ Replacement: [ ] @{ @} - Enable special code to work around file systems which only permit very - short file names, such as MS-DOS@. - --@itemx --help -+@item --help - @itemx --target-help - @opindex help - @opindex target-help -diff -urp gcc-4.7.2/gcc/doc/generic.texi gcc-4.7.2/gcc/doc/generic.texi ---- gcc-4.7.2/gcc/doc/generic.texi 2011-12-23 23:07:16.000000000 +0100 -+++ gcc-4.7.2/gcc/doc/generic.texi 2013-03-28 14:01:19.000000000 +0100 -@@ -1415,13 +1415,13 @@ generate these expressions anyhow, if it - not matter. The type of the operands and that of the result are - always of @code{BOOLEAN_TYPE} or @code{INTEGER_TYPE}. - --@itemx POINTER_PLUS_EXPR -+@item POINTER_PLUS_EXPR - This node represents pointer arithmetic. The first operand is always - a pointer/reference type. The second operand is always an unsigned - integer type compatible with sizetype. This is the only binary - arithmetic operand that can operate on pointer types. - --@itemx PLUS_EXPR -+@item PLUS_EXPR - @itemx MINUS_EXPR - @itemx MULT_EXPR - These nodes represent various binary arithmetic operations. -diff -urp gcc-4.7.2/gcc/doc/invoke.texi gcc-4.7.2/gcc/doc/invoke.texi ---- gcc-4.7.2/gcc/doc/invoke.texi 2012-09-14 22:45:27.000000000 +0200 -+++ gcc-4.7.2/gcc/doc/invoke.texi 2013-03-28 13:55:57.000000000 +0100 -@@ -5179,7 +5179,7 @@ thus dbg_cnt() returns true always unles - e.g. With -fdbg-cnt=dce:10,tail_call:0 - dbg_cnt(dce) will return true only for first 10 invocations - --@itemx -fenable-@var{kind}-@var{pass} -+@item -fenable-@var{kind}-@var{pass} - @itemx -fdisable-@var{kind}-@var{pass}=@var{range-list} - @opindex fdisable- - @opindex fenable- -@@ -5327,11 +5327,11 @@ Dump after duplicating the computed goto - @option{-fdump-rtl-ce3} enable dumping after the three - if conversion passes. - --@itemx -fdump-rtl-cprop_hardreg -+@item -fdump-rtl-cprop_hardreg - @opindex fdump-rtl-cprop_hardreg - Dump after hard register copy propagation. - --@itemx -fdump-rtl-csa -+@item -fdump-rtl-csa - @opindex fdump-rtl-csa - Dump after combining stack adjustments. - -@@ -5342,11 +5342,11 @@ Dump after combining stack adjustments. - @option{-fdump-rtl-cse1} and @option{-fdump-rtl-cse2} enable dumping after - the two common sub-expression elimination passes. - --@itemx -fdump-rtl-dce -+@item -fdump-rtl-dce - @opindex fdump-rtl-dce - Dump after the standalone dead code elimination passes. - --@itemx -fdump-rtl-dbr -+@item -fdump-rtl-dbr - @opindex fdump-rtl-dbr - Dump after delayed branch scheduling. - -@@ -5391,7 +5391,7 @@ Dump after the initialization of the reg - @opindex fdump-rtl-initvals - Dump after the computation of the initial value sets. - --@itemx -fdump-rtl-into_cfglayout -+@item -fdump-rtl-into_cfglayout - @opindex fdump-rtl-into_cfglayout - Dump after converting to cfglayout mode. - -@@ -5421,7 +5421,7 @@ Dump after removing redundant mode switc - @opindex fdump-rtl-rnreg - Dump after register renumbering. - --@itemx -fdump-rtl-outof_cfglayout -+@item -fdump-rtl-outof_cfglayout - @opindex fdump-rtl-outof_cfglayout - Dump after converting from cfglayout mode. - -@@ -5433,7 +5433,7 @@ Dump after the peephole pass. - @opindex fdump-rtl-postreload - Dump after post-reload optimizations. - --@itemx -fdump-rtl-pro_and_epilogue -+@item -fdump-rtl-pro_and_epilogue - @opindex fdump-rtl-pro_and_epilogue - Dump after generating the function prologues and epilogues. - diff --git a/util/crossgcc/patches/gcc-4.7.3_armv7a.patch b/util/crossgcc/patches/gcc-4.7.3_armv7a.patch new file mode 100644 index 0000000..ccbc01e --- /dev/null +++ b/util/crossgcc/patches/gcc-4.7.3_armv7a.patch @@ -0,0 +1,12 @@ +diff -ur gcc-4.7.3/config.sub gcc-4.7.3-patched/config.sub +--- gcc-4.7.3/config.sub 2012-08-06 16:34:27.000000000 +0200 ++++ gcc-4.7.3-patched/config.sub 2013-04-19 00:25:16.401391381 +0200 +@@ -250,7 +250,7 @@ + | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ + | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ + | am33_2.0 \ +- | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ ++ | arc | arm | arm[bl]e | arme[lb] | armv* | armv[345][lb] | avr | avr32 \ + | be32 | be64 \ + | bfin \ + | c4x | clipper \

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Patch set updated for coreboot: 9c6451e crossgcc: update to gcc 4.7.3
by Idwer Vollering 22 Apr '13

22 Apr '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3112 -gerrit commit 9c6451e1967a149b2bbedf2f8abdc9e1c3d3db08 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Fri Apr 19 00:56:57 2013 +0200 crossgcc: update to gcc 4.7.3 Update crossgcc to use gcc 4.7.3 The resulting coreboot.rom is not runtime tested (any volunteers?). Drop the texinfo patch, rename the armv7a patch. Some Linux distributions have moved on to gcc 4.8, under certain circumstances this version can't (cross-)compile gcc 4.7.2 Bug report: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56927 Change-Id: Id8ce5f86c34e1a0900d44dc6ae4e81cb9548ecc2 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- util/crossgcc/buildgcc | 6 +- util/crossgcc/patches/gcc-4.7.2_armv7a.patch | 12 ---- util/crossgcc/patches/gcc-4.7.2_texinfo.patch | 98 --------------------------- util/crossgcc/patches/gcc-4.7.3_armv7a.patch | 12 ++++ 4 files changed, 15 insertions(+), 113 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 34518a8..116aaf6 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -20,8 +20,8 @@ # Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA # -CROSSGCC_DATE="December 4th, 2012" -CROSSGCC_VERSION="1.20" +CROSSGCC_DATE="April 19th, 2013" +CROSSGCC_VERSION="1.21" # default settings TARGETDIR=`pwd`/xgcc @@ -33,7 +33,7 @@ GMP_VERSION=5.0.5 MPFR_VERSION=3.1.1 MPC_VERSION=1.0.1 LIBELF_VERSION=0.8.13 -GCC_VERSION=4.7.2 +GCC_VERSION=4.7.3 GCC_AUTOCONF_VERSION=2.64 BINUTILS_VERSION=2.23 GDB_VERSION=7.5 diff --git a/util/crossgcc/patches/gcc-4.7.2_armv7a.patch b/util/crossgcc/patches/gcc-4.7.2_armv7a.patch deleted file mode 100644 index 82e6609..0000000 --- a/util/crossgcc/patches/gcc-4.7.2_armv7a.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -ur gcc-4.7.2/config.sub gcc-4.7.2/config.sub ---- gcc-4.7.2/config.sub 2012-08-06 07:34:27.000000000 -0700 -+++ gcc-4.7.2/config.sub 2012-12-04 15:03:30.813137430 -0800 -@@ -250,7 +250,7 @@ - | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ - | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ - | am33_2.0 \ -- | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ -+ | arc | arm | arm[bl]e | arme[lb] | armv* | armv[345][lb] | avr | avr32 \ - | be32 | be64 \ - | bfin \ - | c4x | clipper \ diff --git a/util/crossgcc/patches/gcc-4.7.2_texinfo.patch b/util/crossgcc/patches/gcc-4.7.2_texinfo.patch deleted file mode 100644 index 34c6a68..0000000 --- a/util/crossgcc/patches/gcc-4.7.2_texinfo.patch +++ /dev/null @@ -1,98 +0,0 @@ -diff -urp gcc-4.7.2/gcc/doc/cppopts.texi gcc-4.7.2/gcc/doc/cppopts.texi ---- gcc-4.7.2/gcc/doc/cppopts.texi 2013-03-28 13:41:01.000000000 +0100 -+++ gcc-4.7.2/gcc/doc/cppopts.texi 2013-03-28 13:55:05.000000000 +0100 -@@ -803,7 +803,7 @@ Replacement: [ ] @{ @} - Enable special code to work around file systems which only permit very - short file names, such as MS-DOS@. - --@itemx --help -+@item --help - @itemx --target-help - @opindex help - @opindex target-help -diff -urp gcc-4.7.2/gcc/doc/generic.texi gcc-4.7.2/gcc/doc/generic.texi ---- gcc-4.7.2/gcc/doc/generic.texi 2011-12-23 23:07:16.000000000 +0100 -+++ gcc-4.7.2/gcc/doc/generic.texi 2013-03-28 14:01:19.000000000 +0100 -@@ -1415,13 +1415,13 @@ generate these expressions anyhow, if it - not matter. The type of the operands and that of the result are - always of @code{BOOLEAN_TYPE} or @code{INTEGER_TYPE}. - --@itemx POINTER_PLUS_EXPR -+@item POINTER_PLUS_EXPR - This node represents pointer arithmetic. The first operand is always - a pointer/reference type. The second operand is always an unsigned - integer type compatible with sizetype. This is the only binary - arithmetic operand that can operate on pointer types. - --@itemx PLUS_EXPR -+@item PLUS_EXPR - @itemx MINUS_EXPR - @itemx MULT_EXPR - These nodes represent various binary arithmetic operations. -diff -urp gcc-4.7.2/gcc/doc/invoke.texi gcc-4.7.2/gcc/doc/invoke.texi ---- gcc-4.7.2/gcc/doc/invoke.texi 2012-09-14 22:45:27.000000000 +0200 -+++ gcc-4.7.2/gcc/doc/invoke.texi 2013-03-28 13:55:57.000000000 +0100 -@@ -5179,7 +5179,7 @@ thus dbg_cnt() returns true always unles - e.g. With -fdbg-cnt=dce:10,tail_call:0 - dbg_cnt(dce) will return true only for first 10 invocations - --@itemx -fenable-@var{kind}-@var{pass} -+@item -fenable-@var{kind}-@var{pass} - @itemx -fdisable-@var{kind}-@var{pass}=@var{range-list} - @opindex fdisable- - @opindex fenable- -@@ -5327,11 +5327,11 @@ Dump after duplicating the computed goto - @option{-fdump-rtl-ce3} enable dumping after the three - if conversion passes. - --@itemx -fdump-rtl-cprop_hardreg -+@item -fdump-rtl-cprop_hardreg - @opindex fdump-rtl-cprop_hardreg - Dump after hard register copy propagation. - --@itemx -fdump-rtl-csa -+@item -fdump-rtl-csa - @opindex fdump-rtl-csa - Dump after combining stack adjustments. - -@@ -5342,11 +5342,11 @@ Dump after combining stack adjustments. - @option{-fdump-rtl-cse1} and @option{-fdump-rtl-cse2} enable dumping after - the two common sub-expression elimination passes. - --@itemx -fdump-rtl-dce -+@item -fdump-rtl-dce - @opindex fdump-rtl-dce - Dump after the standalone dead code elimination passes. - --@itemx -fdump-rtl-dbr -+@item -fdump-rtl-dbr - @opindex fdump-rtl-dbr - Dump after delayed branch scheduling. - -@@ -5391,7 +5391,7 @@ Dump after the initialization of the reg - @opindex fdump-rtl-initvals - Dump after the computation of the initial value sets. - --@itemx -fdump-rtl-into_cfglayout -+@item -fdump-rtl-into_cfglayout - @opindex fdump-rtl-into_cfglayout - Dump after converting to cfglayout mode. - -@@ -5421,7 +5421,7 @@ Dump after removing redundant mode switc - @opindex fdump-rtl-rnreg - Dump after register renumbering. - --@itemx -fdump-rtl-outof_cfglayout -+@item -fdump-rtl-outof_cfglayout - @opindex fdump-rtl-outof_cfglayout - Dump after converting from cfglayout mode. - -@@ -5433,7 +5433,7 @@ Dump after the peephole pass. - @opindex fdump-rtl-postreload - Dump after post-reload optimizations. - --@itemx -fdump-rtl-pro_and_epilogue -+@item -fdump-rtl-pro_and_epilogue - @opindex fdump-rtl-pro_and_epilogue - Dump after generating the function prologues and epilogues. - diff --git a/util/crossgcc/patches/gcc-4.7.3_armv7a.patch b/util/crossgcc/patches/gcc-4.7.3_armv7a.patch new file mode 100644 index 0000000..ccbc01e --- /dev/null +++ b/util/crossgcc/patches/gcc-4.7.3_armv7a.patch @@ -0,0 +1,12 @@ +diff -ur gcc-4.7.3/config.sub gcc-4.7.3-patched/config.sub +--- gcc-4.7.3/config.sub 2012-08-06 16:34:27.000000000 +0200 ++++ gcc-4.7.3-patched/config.sub 2013-04-19 00:25:16.401391381 +0200 +@@ -250,7 +250,7 @@ + | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ + | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ + | am33_2.0 \ +- | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ ++ | arc | arm | arm[bl]e | arme[lb] | armv* | armv[345][lb] | avr | avr32 \ + | be32 | be64 \ + | bfin \ + | c4x | clipper \

1 0

Patch set updated for coreboot: a81986b crossgcc: update to gcc 4.7.3
by Idwer Vollering 22 Apr '13

22 Apr '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3112 -gerrit commit a81986b84f7212e41fa74590305f5b483ad707e1 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Fri Apr 19 00:56:57 2013 +0200 crossgcc: update to gcc 4.7.3 Update crossgcc to use gcc 4.7.3 The resulting coreboot.rom is not runtime tested (any volunteers?). Drop the texinfo patch, rename the armv7a patch. Some Linux distributions have moved on to gcc 4.8, under certain circumstances this version can't (cross-)compile gcc 4.7.2 Bug report: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56927 Change-Id: Id8ce5f86c34e1a0900d44dc6ae4e81cb9548ecc2 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- util/crossgcc/buildgcc | 2 +- util/crossgcc/patches/gcc-4.7.2_armv7a.patch | 12 ---- util/crossgcc/patches/gcc-4.7.2_texinfo.patch | 98 --------------------------- util/crossgcc/patches/gcc-4.7.3_armv7a.patch | 12 ++++ 4 files changed, 13 insertions(+), 111 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index be8d1f2..ae79d4b 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -33,7 +33,7 @@ GMP_VERSION=5.0.5 MPFR_VERSION=3.1.1 MPC_VERSION=1.0.1 LIBELF_VERSION=0.8.13 -GCC_VERSION=4.7.2 +GCC_VERSION=4.7.3 GCC_AUTOCONF_VERSION=2.64 BINUTILS_VERSION=2.23 GDB_VERSION=7.5 diff --git a/util/crossgcc/patches/gcc-4.7.2_armv7a.patch b/util/crossgcc/patches/gcc-4.7.2_armv7a.patch deleted file mode 100644 index 82e6609..0000000 --- a/util/crossgcc/patches/gcc-4.7.2_armv7a.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -ur gcc-4.7.2/config.sub gcc-4.7.2/config.sub ---- gcc-4.7.2/config.sub 2012-08-06 07:34:27.000000000 -0700 -+++ gcc-4.7.2/config.sub 2012-12-04 15:03:30.813137430 -0800 -@@ -250,7 +250,7 @@ - | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ - | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ - | am33_2.0 \ -- | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ -+ | arc | arm | arm[bl]e | arme[lb] | armv* | armv[345][lb] | avr | avr32 \ - | be32 | be64 \ - | bfin \ - | c4x | clipper \ diff --git a/util/crossgcc/patches/gcc-4.7.2_texinfo.patch b/util/crossgcc/patches/gcc-4.7.2_texinfo.patch deleted file mode 100644 index 34c6a68..0000000 --- a/util/crossgcc/patches/gcc-4.7.2_texinfo.patch +++ /dev/null @@ -1,98 +0,0 @@ -diff -urp gcc-4.7.2/gcc/doc/cppopts.texi gcc-4.7.2/gcc/doc/cppopts.texi ---- gcc-4.7.2/gcc/doc/cppopts.texi 2013-03-28 13:41:01.000000000 +0100 -+++ gcc-4.7.2/gcc/doc/cppopts.texi 2013-03-28 13:55:05.000000000 +0100 -@@ -803,7 +803,7 @@ Replacement: [ ] @{ @} - Enable special code to work around file systems which only permit very - short file names, such as MS-DOS@. - --@itemx --help -+@item --help - @itemx --target-help - @opindex help - @opindex target-help -diff -urp gcc-4.7.2/gcc/doc/generic.texi gcc-4.7.2/gcc/doc/generic.texi ---- gcc-4.7.2/gcc/doc/generic.texi 2011-12-23 23:07:16.000000000 +0100 -+++ gcc-4.7.2/gcc/doc/generic.texi 2013-03-28 14:01:19.000000000 +0100 -@@ -1415,13 +1415,13 @@ generate these expressions anyhow, if it - not matter. The type of the operands and that of the result are - always of @code{BOOLEAN_TYPE} or @code{INTEGER_TYPE}. - --@itemx POINTER_PLUS_EXPR -+@item POINTER_PLUS_EXPR - This node represents pointer arithmetic. The first operand is always - a pointer/reference type. The second operand is always an unsigned - integer type compatible with sizetype. This is the only binary - arithmetic operand that can operate on pointer types. - --@itemx PLUS_EXPR -+@item PLUS_EXPR - @itemx MINUS_EXPR - @itemx MULT_EXPR - These nodes represent various binary arithmetic operations. -diff -urp gcc-4.7.2/gcc/doc/invoke.texi gcc-4.7.2/gcc/doc/invoke.texi ---- gcc-4.7.2/gcc/doc/invoke.texi 2012-09-14 22:45:27.000000000 +0200 -+++ gcc-4.7.2/gcc/doc/invoke.texi 2013-03-28 13:55:57.000000000 +0100 -@@ -5179,7 +5179,7 @@ thus dbg_cnt() returns true always unles - e.g. With -fdbg-cnt=dce:10,tail_call:0 - dbg_cnt(dce) will return true only for first 10 invocations - --@itemx -fenable-@var{kind}-@var{pass} -+@item -fenable-@var{kind}-@var{pass} - @itemx -fdisable-@var{kind}-@var{pass}=@var{range-list} - @opindex fdisable- - @opindex fenable- -@@ -5327,11 +5327,11 @@ Dump after duplicating the computed goto - @option{-fdump-rtl-ce3} enable dumping after the three - if conversion passes. - --@itemx -fdump-rtl-cprop_hardreg -+@item -fdump-rtl-cprop_hardreg - @opindex fdump-rtl-cprop_hardreg - Dump after hard register copy propagation. - --@itemx -fdump-rtl-csa -+@item -fdump-rtl-csa - @opindex fdump-rtl-csa - Dump after combining stack adjustments. - -@@ -5342,11 +5342,11 @@ Dump after combining stack adjustments. - @option{-fdump-rtl-cse1} and @option{-fdump-rtl-cse2} enable dumping after - the two common sub-expression elimination passes. - --@itemx -fdump-rtl-dce -+@item -fdump-rtl-dce - @opindex fdump-rtl-dce - Dump after the standalone dead code elimination passes. - --@itemx -fdump-rtl-dbr -+@item -fdump-rtl-dbr - @opindex fdump-rtl-dbr - Dump after delayed branch scheduling. - -@@ -5391,7 +5391,7 @@ Dump after the initialization of the reg - @opindex fdump-rtl-initvals - Dump after the computation of the initial value sets. - --@itemx -fdump-rtl-into_cfglayout -+@item -fdump-rtl-into_cfglayout - @opindex fdump-rtl-into_cfglayout - Dump after converting to cfglayout mode. - -@@ -5421,7 +5421,7 @@ Dump after removing redundant mode switc - @opindex fdump-rtl-rnreg - Dump after register renumbering. - --@itemx -fdump-rtl-outof_cfglayout -+@item -fdump-rtl-outof_cfglayout - @opindex fdump-rtl-outof_cfglayout - Dump after converting from cfglayout mode. - -@@ -5433,7 +5433,7 @@ Dump after the peephole pass. - @opindex fdump-rtl-postreload - Dump after post-reload optimizations. - --@itemx -fdump-rtl-pro_and_epilogue -+@item -fdump-rtl-pro_and_epilogue - @opindex fdump-rtl-pro_and_epilogue - Dump after generating the function prologues and epilogues. - diff --git a/util/crossgcc/patches/gcc-4.7.3_armv7a.patch b/util/crossgcc/patches/gcc-4.7.3_armv7a.patch new file mode 100644 index 0000000..ccbc01e --- /dev/null +++ b/util/crossgcc/patches/gcc-4.7.3_armv7a.patch @@ -0,0 +1,12 @@ +diff -ur gcc-4.7.3/config.sub gcc-4.7.3-patched/config.sub +--- gcc-4.7.3/config.sub 2012-08-06 16:34:27.000000000 +0200 ++++ gcc-4.7.3-patched/config.sub 2013-04-19 00:25:16.401391381 +0200 +@@ -250,7 +250,7 @@ + | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ + | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ + | am33_2.0 \ +- | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ ++ | arc | arm | arm[bl]e | arme[lb] | armv* | armv[345][lb] | avr | avr32 \ + | be32 | be64 \ + | bfin \ + | c4x | clipper \

1 0

Patch set updated for coreboot: 0edd4cb Intel: Return on missing microcode file to fix null pointer dereference
by Stefan Reinauer 22 Apr '13

22 Apr '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2990 -gerrit commit 0edd4cbf2e76ce92a80ff19dff5b85f9b1b5c813 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Mar 30 12:04:23 2013 +0100 Intel: Return on missing microcode file to fix null pointer dereference Selecting `CPU_MICROCODE_IN_CBFS` in Kconfig but not having the microcode blob `cpu_microcode_blob.bin` in CBFS results in a null pointer dereference later on resulting in a crash. for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { Fix this by returning if `microcode_updates` is `NULL`, that means no file is found. This patch is successfully tested on the Lenovo X201. Change-Id: I6e18fd37256910bf047061e4633a66cf29ad7b69 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/intel/microcode/microcode.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index d908c25..1991ed8 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -21,6 +21,7 @@ /* Microcode update for Intel PIII and later CPUs */ #include <stdint.h> +#include <stddef.h> #if !defined(__ROMCC__) #include <console/console.h> #endif @@ -131,7 +132,7 @@ const void *intel_microcode_find(void) #endif if (!microcode_updates) - return microcode_updates; + return NULL; /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ msr.lo = 0; @@ -202,6 +203,13 @@ void intel_update_microcode(const void *microcode_updates) const char *c; msr_t msr; + if (!microcode_updates) { +#if !defined(__ROMCC__) + printk(BIOS_WARNING, "No microcode updates found.\n"); +#endif + return; + } + /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ msr.lo = 0; msr.hi = 0;

1 0

Patch set updated for coreboot: f8404bd google/snow: Support sleep/resume.
by David Hendricks 21 Apr '13

21 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3102 -gerrit commit f8404bdc9685685f63fdc065b94585248a96e2dc Author: Hung-Te Lin <hungte(a)chromium.org> Date: Tue Apr 16 20:03:00 2013 +0800 google/snow: Support sleep/resume. WIP. Do not submit. Change-Id: I65681c42eeef2736e55bb906595f42a5b1dfdf11 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/Makefile.inc | 2 +- src/cpu/samsung/exynos5250/dmc_init_ddr3.c | 14 +++-- src/cpu/samsung/exynos5250/power.c | 7 +-- src/cpu/samsung/exynos5250/setup.h | 4 +- src/mainboard/google/snow/Makefile.inc | 3 + src/mainboard/google/snow/bootblock.c | 12 ++++ src/mainboard/google/snow/mainboard.h | 2 + src/mainboard/google/snow/romstage.c | 97 ++++++++++++++++-------------- src/mainboard/google/snow/wakeup.c | 28 +++++++++ 9 files changed, 113 insertions(+), 56 deletions(-) diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 8788a6c..25d1bc5 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -3,7 +3,7 @@ # image outside of CBFS #INTERMEDIATE += exynos5250_add_bl1 -bootblock-y += pinmux.c mct.c +bootblock-y += pinmux.c mct.c power.c # Clock is required for UART bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c index 5bb8a37..132471d 100644 --- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c @@ -61,7 +61,8 @@ static void reset_phy_ctrl(void) udelay(500); } -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) +int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, + int mem_reset) { unsigned int val; struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl; @@ -71,9 +72,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE; phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE; dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE; - printk(BIOS_SPEW, "ddr3_mem_ctrl_init: reset phy: "); - reset_phy_ctrl(); - printk(BIOS_SPEW, "done\n"); + + if (mem_reset) { + printk(BIOS_SPEW, "%s: reset phy: ", __func__); + reset_phy_ctrl(); + printk(BIOS_SPEW, "done\n"); + } else { + printk(BIOS_SPEW, "%s: skip mem_reset.\n", __func__); + } /* Set Impedance Output Driver */ printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Set Impedance Output Driver\n"); diff --git a/src/cpu/samsung/exynos5250/power.c b/src/cpu/samsung/exynos5250/power.c index 8aba0e8..6ed6af7 100644 --- a/src/cpu/samsung/exynos5250/power.c +++ b/src/cpu/samsung/exynos5250/power.c @@ -25,7 +25,7 @@ #include <common.h> #include <arch/hlt.h> #include <arch/io.h> -#include <arch/hlt.h> +#include <arch/stages.h> #include <console/console.h> #include <cpu/samsung/exynos5-common/power.h> #include <cpu/samsung/exynos5250/cpu.h> @@ -122,9 +122,8 @@ void power_exit_wakeup(void) { struct exynos5_power *power = samsung_get_base_power(); - typedef void (*resume_func)(void); - - ((resume_func)power->inform0)(); + ps_hold_setup(); + stage_exit((void *)power->inform0); } int power_init(void) diff --git a/src/cpu/samsung/exynos5250/setup.h b/src/cpu/samsung/exynos5250/setup.h index 4f7f58c..952c125 100644 --- a/src/cpu/samsung/exynos5250/setup.h +++ b/src/cpu/samsung/exynos5250/setup.h @@ -702,9 +702,11 @@ void mem_ctrl_init(void); * which the DMC uses to decide how to split a memory * chunk into smaller chunks to support concurrent * accesses; may vary across boards. + * @param mem_reset Reset memory when initialization. * @return 0 if ok, SETUP_ERR_... if there is a problem */ -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size); +int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, + int mem_reset); void tzpc_init(void); /* diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc index 46e366f..84a8c05 100644 --- a/src/mainboard/google/snow/Makefile.inc +++ b/src/mainboard/google/snow/Makefile.inc @@ -17,9 +17,12 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +bootblock-y += wakeup.c + romstage-y += mainboard.c romstage-y += memory.c romstage-y += romstage.c +romstage-y += wakeup.c # ramstage-y += ec.c ramstage-y += ramstage.c diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index d2e0b50..cd617e4 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -23,17 +23,29 @@ #include <uart.h> #include <time.h> #include <console/console.h> +#include <cpu/samsung/exynos5-common/exynos5-common.h> #include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/pinmux.h> +#include <cpu/samsung/exynos5250/power.h> +#include "mainboard.h" void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { + int reset_status; + /* kick off the microsecond timer. We want to do this as early * as we can. */ timer_start(); + reset_status = power_read_reset_status(); + if (reset_status == S5P_CHECK_DIDLE || + reset_status == S5P_CHECK_LPA) { + if (wakeup_permitted()) + power_exit_wakeup(); + } + exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); #if CONFIG_EARLY_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); diff --git a/src/mainboard/google/snow/mainboard.h b/src/mainboard/google/snow/mainboard.h index 6fe371f..17777ad 100644 --- a/src/mainboard/google/snow/mainboard.h +++ b/src/mainboard/google/snow/mainboard.h @@ -35,4 +35,6 @@ enum snow_board_config { int board_get_config(void); +int wakeup_permitted(void); + #endif /* MAINBOARD_H */ diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 41b88e1..f221055 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -25,6 +25,8 @@ #include <arch/cache.h> #include <arch/gpio.h> +#include <arch/hlt.h> +#include <cpu/samsung/exynos5-common/exynos5-common.h> #include <cpu/samsung/exynos5-common/i2c.h> #include <cpu/samsung/exynos5250/clk.h> #include <cpu/samsung/exynos5250/cpu.h> @@ -46,19 +48,6 @@ #define PMIC_BUS 0 #define MMC0_GPIO_PIN (58) -#if 0 -static int board_wakeup_permitted(void) -{ - const int gpio = GPIO_Y10; - int is_bad_wake; - - /* We're a bad wakeup if the gpio was defined and was high */ - is_bad_wake = ((gpio != -1) && gpio_get_value(gpio)); - - return !is_bad_wake; -} -#endif - static int setup_pmic(void) { int error = 0; @@ -100,7 +89,22 @@ static int setup_pmic(void) return error; } -static void initialize_s5p_mshc(void) +static int setup_memory(struct mem_timings *mem, int reset) +{ + int ret; + printk(BIOS_SPEW, "mem: %#x type: %#x, div: %#x, mhz: %#x\n", + mem->mem_manuf, mem->mem_type, mem->mpll_mdiv, + mem->frequency_mhz); + ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, reset); + if (ret) { + printk(BIOS_CRIT, + "%s: Memory controller init failed, err: %#x\n", + __func__, ret); + } + return ret; +} + +static void setup_mmc(void) { /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ if (clock_set_mshci(PERIPH_ID_SDMMC0)) @@ -117,12 +121,12 @@ static void initialize_s5p_mshc(void) exynos_pinmux_config(PERIPH_ID_SDMMC2, 0); } -static void graphics(void) +static void setup_graphics(void) { exynos_pinmux_config(PERIPH_ID_DPHPD, 0); } -static void chromeos_gpios(void) +static void setup_chromeos_gpios(void) { struct exynos5_gpio_part1 *gpio_pt1; struct exynos5_gpio_part2 *gpio_pt2; @@ -154,49 +158,50 @@ void main(void) { struct mem_timings *mem; struct arm_clk_ratios *arm_ratios; - int ret; + int is_resume = 0; void *entry; + uint32_t reset_status; - clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ + reset_status = power_read_reset_status(); + /* S5P_CHECK_DIDLE / S5P_CHECK_LPA are already handled in bootblock. */ + if (reset_status == S5P_CHECK_SLEEP) + is_resume = 1; - /* Clock must be initialized before console_init, otherwise you may need - * to re-initialize serial console drivers again. */ + /* Clock must be initialized before console_init, otherwise you + * may need to re-initialize serial console drivers again. */ mem = get_mem_timings(); + if (!mem) + die("Unable to auto-detect memory timings"); arm_ratios = get_arm_clk_ratios(); system_clock_init(mem, arm_ratios); - console_init(); - i2c_init(0, CONFIG_SYS_I2C_SPEED, 0x00); - if (power_init()) - power_shutdown(); - printk(BIOS_DEBUG, "%s: setting up pmic...\n", __func__); - if (setup_pmic()) - power_shutdown(); - - if (!mem) { - printk(BIOS_CRIT, "Unable to auto-detect memory timings\n"); - while(1); + power_init(); + if (!is_resume) { + /* Initialize I2C to program PMIC. */ + i2c_init(0, CONFIG_SYS_I2C_SPEED, 0x00); + printk(BIOS_SPEW, "%s: Set up PMIC.\n", __func__); + if (setup_pmic()) + power_shutdown(); } - printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n", - mem->mem_manuf, - mem->mem_type, - mem->mpll_mdiv, - mem->frequency_mhz); - ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE); - if (ret) { - printk(BIOS_ERR, "Memory controller init failed, err: %x\n", - ret); - while(1); - } - - initialize_s5p_mshc(); + if (setup_memory(mem, !is_resume)) + power_shutdown(); - chromeos_gpios(); + if (is_resume) { + printk(BIOS_SPEW, "%s: Trying to wake up.\n", __func__); + if (!wakeup_permitted()) + power_reset(); + power_exit_wakeup(); + /* Never returns. */ + } - graphics(); + /* Initialize peripherals. */ + setup_mmc(); + setup_chromeos_gpios(); + setup_graphics(); + clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry); diff --git a/src/mainboard/google/snow/wakeup.c b/src/mainboard/google/snow/wakeup.c new file mode 100644 index 0000000..d5f7a25 --- /dev/null +++ b/src/mainboard/google/snow/wakeup.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/gpio.h> +#include <cpu/samsung/exynos5250/gpio.h> + +#include "mainboard.h" + +int wakeup_permitted(void) +{ + /* We're a bad wakeup if the gpio is high */ + return gpio_get_value(GPIO_Y10); +} +

1 0

Patch set updated for coreboot: a278543 GOOGLE/SNOW: get graphics working
by David Hendricks 21 Apr '13

21 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3116 -gerrit commit a2785438a20105e0665ba6e2578ecf57d92f5a19 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Apr 18 18:09:24 2013 -0700 GOOGLE/SNOW: get graphics working This adds preliminary support for display bring-up on Snow. It includes framebuffer initialization and LCD enable functions. Change-Id: I16e711c97e9d02c916824f621e2313297448732b Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/exynos-fb.c | 84 ++++++++++++++++++++++++----- src/cpu/samsung/exynos5-common/s5p-dp-reg.c | 10 ++-- src/cpu/samsung/exynos5250/cpu.c | 25 +++++++-- src/mainboard/google/snow/Kconfig | 2 + src/mainboard/google/snow/ramstage.c | 36 +++++++++++++ 5 files changed, 138 insertions(+), 19 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index 54a2d7a..cdb5881 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -27,6 +27,7 @@ #include <arch/io.h> #include <stdlib.h> #include <string.h> +#include <time.h> #include <console/console.h> #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/power.h> @@ -41,6 +42,28 @@ #include "cpu/samsung/exynos5250/s5p-dp.h" #include "s5p-dp-core.h" +/* + * Here is the rough outline of how we bring up the display: + * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD + * 2. Source determines video mode by reading DPCD receiver capability field + * (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD + * 0000Dh). + * 3. Sink replies DPCD receiver capability field. + * 4. Source starts EDID read thru I2C-over-AUX. + * 5. Sink replies EDID thru I2C-over-AUX. + * 6. Source determines link configuration, such as MAX_LINK_RATE and + * MAX_LANE_COUNT. Source also determines which type of eDP Authentication + * method to use and writes DPCD link configuration field (DPCD 00100h to + * 0010Ah) including eDP configuration set (DPCD 0010Ah). + * 7. Source starts link training. Sink does clock recovery and equalization. + * 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh). + * 9. Sink replies DPCD link status field. If main link is not stable, Source + * repeats Step 7. + * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video + * parameters and recovers stream clock. + * 11. Source sends video data. + */ + /* To help debug any init errors here, define a list of possible errors */ enum { ERR_PLL_NOT_UNLOCKED = 2, @@ -126,38 +149,54 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, { unsigned int val; u32 fbsize; - struct exynos5_fimd *fimd = - samsung_get_base_fimd(); - struct exynos5_disp_ctrl *disp_ctrl = - samsung_get_base_disp_ctrl(); - + struct exynos5_fimd *fimd = samsung_get_base_fimd(); + struct exynos5_disp_ctrl *disp_ctrl = samsung_get_base_disp_ctrl(); + + printk(BIOS_SPEW, "%s: fimd %p disp_ctrl %p\n", + __func__, fimd, disp_ctrl); + printk(BIOS_SPEW, "pd %p\n", pd); + printk(BIOS_SPEW, "lcdbase %p\n", lcdbase); + printk(BIOS_SPEW, "pd->xres %d pd->yres %d\n", pd->xres, pd->yres); + printk(BIOS_SPEW, "Write %08x to %p\n", + pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); writel(pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); val = ENVID_ON | ENVID_F_ON | (pd->clkval_f << CLKVAL_F_OFFSET); + printk(BIOS_SPEW, "Write %08x to fimd->vidcon0\n", val); writel(val, &fimd->vidcon0); val = (pd->vsync << VSYNC_PULSE_WIDTH_OFFSET) | (pd->lower_margin << V_FRONT_PORCH_OFFSET) | (pd->upper_margin << V_BACK_PORCH_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon0); writel(val, &disp_ctrl->vidtcon0); val = (pd->hsync << HSYNC_PULSE_WIDTH_OFFSET) | (pd->right_margin << H_FRONT_PORCH_OFFSET) | (pd->left_margin << H_BACK_PORCH_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon1); writel(val, &disp_ctrl->vidtcon1); val = ((pd->xres - 1) << HOZVAL_OFFSET) | ((pd->yres - 1) << LINEVAL_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon2); writel(val, &disp_ctrl->vidtcon2); + printk(BIOS_SPEW, "Write %08x to %p\n", + (unsigned int)lcdbase, &fimd->vidw00add0b0); writel((unsigned int)lcdbase, &fimd->vidw00add0b0); fbsize = calc_fbsize(panel_info); + printk(BIOS_SPEW, "Write %08x to %p\n", + (unsigned int)fbsize, &fimd->vidw00add1b0); writel((unsigned int)lcdbase + fbsize, &fimd->vidw00add1b0); + printk(BIOS_SPEW, "Write %08x to %p\n", + (unsigned int)pd->xres*2, &fimd->vidw00add0b0); writel(pd->xres * 2, &fimd->vidw00add2); val = ((pd->xres - 1) << OSD_RIGHTBOTX_F_OFFSET); val |= ((pd->yres - 1) << OSD_RIGHTBOTY_F_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &fimd->vidosd0b); writel(val, &fimd->vidosd0b); writel(pd->xres * pd->yres, &fimd->vidosd0c); @@ -165,6 +204,7 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, val = BPPMODE_F_RGB_16BIT_565 << BPPMODE_F_OFFSET; val |= ENWIN_F_ENABLE | HALF_WORD_SWAP_EN; + printk(BIOS_SPEW, "Write %08x to %p\n", val, &fimd->wincon0); writel(val, &fimd->wincon0); /* DPCLKCON_ENABLE */ @@ -191,7 +231,7 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, struct video_info *video_info) { int timeout = 0; - u32 start; + u32 start, end; struct exynos5_dp *base = dp->base; s5p_dp_config_video_slave_mode(dp, video_info); @@ -206,16 +246,18 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, return -ERR_PLL_NOT_UNLOCKED; } - start = get_timer(0); + start = timer_us(); + end = start + STREAM_ON_TIMEOUT*1000; do { if (s5p_dp_is_slave_video_stream_clock_on(dp) == 0) { timeout++; break; } - } while (get_timer(start) <= STREAM_ON_TIMEOUT); + } while (timer_us() < end); if (!timeout) { - printk(BIOS_DEBUG, "Video Clock Not ok\n"); + printk(BIOS_DEBUG, "Video Clock Not ok after %uus.\n", + timer_us() - start); return -ERR_VIDEO_CLOCK_BAD; } @@ -255,7 +297,6 @@ static int s5p_dp_enable_rx_to_enhanced_mode(struct s5p_dp_device *dp) printk(BIOS_DEBUG, "DPCD read error\n"); return -ERR_DPCD_READ_ERROR1; } - if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, DPCD_ENHANCED_FRAME_EN | (data & DPCD_LANE_COUNT_SET_MASK))) { @@ -408,6 +449,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, unsigned int max_lane, unsigned int max_rate) { + int pll_is_locked = 0; u32 data; u32 start; int lane; @@ -417,14 +459,15 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, clrbits_le32(&base->video_ctl_1, VIDEO_EN); start = get_timer(0); - while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + while ((pll_is_locked = s5p_dp_get_pll_lock_status(dp)) == PLL_UNLOCKED) { if (get_timer(start) > PLL_LOCK_TIMEOUT) { /* Ignore this error, and try to continue */ printk(BIOS_ERR, "PLL is not locked yet.\n"); break; } } - + printk(BIOS_SPEW, "PLL is %slocked\n", + pll_is_locked == PLL_LOCKED ? "": "not "); /* Reset Macro */ setbits_le32(&base->dp_phy_test, MACRO_RST); @@ -448,6 +491,9 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, s5p_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); s5p_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); + printk(BIOS_SPEW, "%s: rate 0x%x, lane_count %d\n", __func__, + dp->link_train.link_rate, dp->link_train.lane_count); + if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { printk(BIOS_DEBUG, "Rx Max Link Rate is abnormal :%x !\n", @@ -470,21 +516,27 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, dp->link_train.link_rate = max_rate; /* Set link rate and count as you want to establish*/ + printk(BIOS_SPEW, "Set link rate and count\n"); writel(dp->link_train.lane_count, &base->lane_count_set); writel(dp->link_train.link_rate, &base->link_bw_set); /* Set sink to D0 (Sink Not Ready) mode. */ + printk(BIOS_SPEW, "Set sink rate to D0\n"); s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE, DPCD_SET_POWER_STATE_D0); /* Start HW link training */ + printk(BIOS_SPEW, "Start Link hardware training\n"); writel(HW_TRAINING_EN, &base->dp_hw_link_training); - /* Wait unitl HW link training done */ + /* Wait until HW link training done */ + printk(BIOS_SPEW, "Wait until HW link training done\n"); s5p_dp_wait_hw_link_training_done(dp); + printk(BIOS_SPEW, "HW link training done\n"); /* Get hardware link training status */ data = readl(&base->dp_hw_link_training); + printk(BIOS_SPEW, "hardware link training status: 0x%08x\n", data); if (data != 0) { printk(BIOS_DEBUG, " H/W link training failure: 0x%x\n", data); return -ERR_LINK_TRAINING_FAILURE; @@ -497,6 +549,8 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, data = readl(&base->lane_count_set); dp->link_train.lane_count = data; + printk(BIOS_SPEW, "Done training: Link bandwidth: 0x%x, lane_count: %d\n", + dp->link_train.link_rate, data); return 0; } @@ -533,12 +587,14 @@ int dp_controller_init(struct s5p_dp_device *dp_device) /* Minimum delay after H/w Link training */ udelay(1000); + printk(BIOS_DEBUG, "call s5p_dp_enable_scramble\n"); ret = s5p_dp_enable_scramble(dp); if (ret) { printk(BIOS_DEBUG, "unable to set scramble mode\n"); return ret; } + printk(BIOS_DEBUG, "call s5p_dp_enable_rx_to_enhanced_mode\n"); ret = s5p_dp_enable_rx_to_enhanced_mode(dp); if (ret) { printk(BIOS_DEBUG, "unable to set enhanced mode\n"); @@ -553,7 +609,9 @@ int dp_controller_init(struct s5p_dp_device *dp_device) writel(dp->link_train.lane_count, &base->lane_count_set); writel(dp->link_train.link_rate, &base->link_bw_set); + printk(BIOS_DEBUG, "call s5p_dp_init_video\n"); s5p_dp_init_video(dp); + printk(BIOS_DEBUG, "call s5p_dp_config_video\n"); ret = s5p_dp_config_video(dp, dp->video_info); if (ret) { printk(BIOS_DEBUG, "unable to config video\n"); diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c index 60e1398..6b5cd69 100644 --- a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c +++ b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c @@ -102,6 +102,8 @@ unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp) u32 reg; reg = readl(&dp->base->dp_debug_ctl); + printk(BIOS_SPEW, "%s: reg is 0x%x, PLL_LOCK is 0x%x\n", + __func__, reg, PLL_LOCK); if (reg & PLL_LOCK) return PLL_LOCKED; else @@ -129,7 +131,8 @@ int s5p_dp_init_analog_func(struct s5p_dp_device *dp) start = get_timer(0); while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { if (get_timer(start) > PLL_LOCK_TIMEOUT) { - printk(BIOS_DEBUG, "%s: PLL is not locked yet\n", __func__); + printk(BIOS_DEBUG, "%s: PLL is not locked\n", + __func__); return -1; } } @@ -176,8 +179,9 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp) /* Enable AUX CH operation */ setbits_le32(&base->aux_ch_ctl_2, AUX_EN); - printk(BIOS_DEBUG, "%s: base: 0x%p, &base->aux_ch_ctl_2: 0x%p, aux_ch_ctl_2: 0x%08x\n", - __func__, base, &base->aux_ch_ctl_2, readl(&base->aux_ch_ctl_2)); + printk(BIOS_DEBUG, "%s: base: 0x%p, &base->aux_ch_ctl_2: 0x%p, " + "aux_ch_ctl_2: 0x%08x\n", __func__, base, &base->aux_ch_ctl_2, + readl(&base->aux_ch_ctl_2)); /* Is AUX CH command reply received? */ reg = readl(&base->dp_int_sta); diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 09b670e..677b0f4 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -5,6 +5,7 @@ #include <console/console.h> #include <device/device.h> #include <cbmem.h> +#include <arch/cache.h> #include <cpu/samsung/exynos5250/fimd.h> #include <cpu/samsung/exynos5-common/s5p-dp-core.h> #include "chip.h" @@ -32,7 +33,6 @@ static void exynos_displayport_init(device_t dev) unsigned long int fb_size; u32 lcdbase; - printk(BIOS_SPEW, "%s: dev 0x%p, conf 0x%p\n", __func__, dev, conf); memset(&vi, 0, sizeof(vi)); memset(&panel, 0, sizeof(panel)); @@ -61,16 +61,35 @@ static void exynos_displayport_init(device_t dev) * The size is a magic number from hardware. Allocate enough for the * frame buffer and color map. */ - fb_size = conf->xres * conf->yres * sizeof(unsigned long); + fb_size = conf->xres * conf->yres * (conf->bpp / 8); lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size + 64*KiB); printk(BIOS_SPEW, "lcd colormap base is %p\n", (void *)(lcdbase)); mmio_resource(dev, 0, lcdbase/KiB, 64); vi.cmap = (void *)lcdbase; + /* + * We need to clean and invalidate the framebuffer region and disable + * caching as well. We assume that our dcache <--> memory address + * space is identity-mapped in 1MB chunks, so align accordingly. + * + * Note: We may want to do something clever to ensure the framebuffer + * region is aligned such that we don't change dcache policy for other + * stuff inadvertantly. + * + * FIXME: Is disabling/re-enabling the MMU entirely necessary? + */ + uint32_t lower = ALIGN_DOWN(lcdbase, MiB); + uint32_t upper = ALIGN_UP(lcdbase + fb_size + 64*KiB, MiB); + dcache_clean_invalidate_by_mva(lower, upper - lower); + dcache_mmu_disable(); + mmu_config_range(lower/MiB, (upper - lower)/MiB, DCACHE_OFF); + dcache_mmu_enable(); + lcdbase += 64*KiB; mmio_resource(dev, 1, lcdbase/KiB, fb_size + (KiB-1)/KiB); printk(BIOS_DEBUG, - "Initializing exynos VGA, base %p\n",(void *)lcdbase); + "Initializing exynos VGA, base %p\n", (void *)lcdbase); + memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase); } diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index 6d3d7c8..c28a986 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -33,6 +33,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EXYNOS_DISPLAYPORT select CHROMEOS select DRIVER_TI_TPS65090 + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_DO_NATIVE_VGA_INIT config MAINBOARD_DIR string diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 1cd84e8..c2c9374 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -23,6 +23,7 @@ #include <drivers/ti/tps65090/tps65090.h> #include <cbmem.h> #include <delay.h> +#include <boot/coreboot_tables.h> #include <arch/cache.h> #include <arch/exception.h> #include <arch/gpio.h> @@ -41,6 +42,41 @@ #define DRAM_SIZE CONFIG_DRAM_SIZE_MB #define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ +int vbe_mode_info_valid(void); +int vbe_mode_info_valid(void) +{ + return 1; +} + +void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); +void fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +{ + /* + * The address returned points at the LCD colormap base. The + * 64KiB offset points at the LCD base. + */ + framebuffer->physical_address = + (u32)cbmem_find(CBMEM_ID_CONSOLE) + 64*KiB; + printk(BIOS_SPEW, "%s: framebuffer->physical address is 0x%llx\n", + __func__, framebuffer->physical_address); + + framebuffer->x_resolution = 1366; + framebuffer->y_resolution = 768; + framebuffer->bits_per_pixel = 16; + framebuffer->bytes_per_line = + (framebuffer->x_resolution * framebuffer->bits_per_pixel) / 8; + + framebuffer->red_mask_pos = 11; + framebuffer->red_mask_size = 5; + framebuffer->green_mask_pos = 6; + framebuffer->green_mask_size = 5; + framebuffer->blue_mask_pos = 0; + framebuffer->blue_mask_size = 5; + framebuffer->reserved_mask_pos = 0; + framebuffer->reserved_mask_size = 0; +} + + void hardwaremain(int boot_complete); void main(void) {

1 0

Patch set updated for coreboot: 24620d6 GOOGLE/SNOW: get graphics working
by David Hendricks 21 Apr '13

21 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3116 -gerrit commit 24620d6058719d53fb0cf54504bd5879c74b1806 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Apr 18 18:09:24 2013 -0700 GOOGLE/SNOW: get graphics working This adds preliminary support for display bring-up on Snow. It includes framebuffer initialization and LCD enable functions. Change-Id: I16e711c97e9d02c916824f621e2313297448732b Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/exynos-fb.c | 84 ++++++++++++++++++++++++----- src/cpu/samsung/exynos5-common/s5p-dp-reg.c | 10 ++-- src/cpu/samsung/exynos5250/cpu.c | 25 +++++++-- src/mainboard/google/snow/Kconfig | 2 + src/mainboard/google/snow/chromeos.c | 7 ++- src/mainboard/google/snow/ramstage.c | 34 ++++++++++++ 6 files changed, 142 insertions(+), 20 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index 54a2d7a..cdb5881 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -27,6 +27,7 @@ #include <arch/io.h> #include <stdlib.h> #include <string.h> +#include <time.h> #include <console/console.h> #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/power.h> @@ -41,6 +42,28 @@ #include "cpu/samsung/exynos5250/s5p-dp.h" #include "s5p-dp-core.h" +/* + * Here is the rough outline of how we bring up the display: + * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD + * 2. Source determines video mode by reading DPCD receiver capability field + * (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD + * 0000Dh). + * 3. Sink replies DPCD receiver capability field. + * 4. Source starts EDID read thru I2C-over-AUX. + * 5. Sink replies EDID thru I2C-over-AUX. + * 6. Source determines link configuration, such as MAX_LINK_RATE and + * MAX_LANE_COUNT. Source also determines which type of eDP Authentication + * method to use and writes DPCD link configuration field (DPCD 00100h to + * 0010Ah) including eDP configuration set (DPCD 0010Ah). + * 7. Source starts link training. Sink does clock recovery and equalization. + * 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh). + * 9. Sink replies DPCD link status field. If main link is not stable, Source + * repeats Step 7. + * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video + * parameters and recovers stream clock. + * 11. Source sends video data. + */ + /* To help debug any init errors here, define a list of possible errors */ enum { ERR_PLL_NOT_UNLOCKED = 2, @@ -126,38 +149,54 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, { unsigned int val; u32 fbsize; - struct exynos5_fimd *fimd = - samsung_get_base_fimd(); - struct exynos5_disp_ctrl *disp_ctrl = - samsung_get_base_disp_ctrl(); - + struct exynos5_fimd *fimd = samsung_get_base_fimd(); + struct exynos5_disp_ctrl *disp_ctrl = samsung_get_base_disp_ctrl(); + + printk(BIOS_SPEW, "%s: fimd %p disp_ctrl %p\n", + __func__, fimd, disp_ctrl); + printk(BIOS_SPEW, "pd %p\n", pd); + printk(BIOS_SPEW, "lcdbase %p\n", lcdbase); + printk(BIOS_SPEW, "pd->xres %d pd->yres %d\n", pd->xres, pd->yres); + printk(BIOS_SPEW, "Write %08x to %p\n", + pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); writel(pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); val = ENVID_ON | ENVID_F_ON | (pd->clkval_f << CLKVAL_F_OFFSET); + printk(BIOS_SPEW, "Write %08x to fimd->vidcon0\n", val); writel(val, &fimd->vidcon0); val = (pd->vsync << VSYNC_PULSE_WIDTH_OFFSET) | (pd->lower_margin << V_FRONT_PORCH_OFFSET) | (pd->upper_margin << V_BACK_PORCH_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon0); writel(val, &disp_ctrl->vidtcon0); val = (pd->hsync << HSYNC_PULSE_WIDTH_OFFSET) | (pd->right_margin << H_FRONT_PORCH_OFFSET) | (pd->left_margin << H_BACK_PORCH_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon1); writel(val, &disp_ctrl->vidtcon1); val = ((pd->xres - 1) << HOZVAL_OFFSET) | ((pd->yres - 1) << LINEVAL_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon2); writel(val, &disp_ctrl->vidtcon2); + printk(BIOS_SPEW, "Write %08x to %p\n", + (unsigned int)lcdbase, &fimd->vidw00add0b0); writel((unsigned int)lcdbase, &fimd->vidw00add0b0); fbsize = calc_fbsize(panel_info); + printk(BIOS_SPEW, "Write %08x to %p\n", + (unsigned int)fbsize, &fimd->vidw00add1b0); writel((unsigned int)lcdbase + fbsize, &fimd->vidw00add1b0); + printk(BIOS_SPEW, "Write %08x to %p\n", + (unsigned int)pd->xres*2, &fimd->vidw00add0b0); writel(pd->xres * 2, &fimd->vidw00add2); val = ((pd->xres - 1) << OSD_RIGHTBOTX_F_OFFSET); val |= ((pd->yres - 1) << OSD_RIGHTBOTY_F_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &fimd->vidosd0b); writel(val, &fimd->vidosd0b); writel(pd->xres * pd->yres, &fimd->vidosd0c); @@ -165,6 +204,7 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, val = BPPMODE_F_RGB_16BIT_565 << BPPMODE_F_OFFSET; val |= ENWIN_F_ENABLE | HALF_WORD_SWAP_EN; + printk(BIOS_SPEW, "Write %08x to %p\n", val, &fimd->wincon0); writel(val, &fimd->wincon0); /* DPCLKCON_ENABLE */ @@ -191,7 +231,7 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, struct video_info *video_info) { int timeout = 0; - u32 start; + u32 start, end; struct exynos5_dp *base = dp->base; s5p_dp_config_video_slave_mode(dp, video_info); @@ -206,16 +246,18 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, return -ERR_PLL_NOT_UNLOCKED; } - start = get_timer(0); + start = timer_us(); + end = start + STREAM_ON_TIMEOUT*1000; do { if (s5p_dp_is_slave_video_stream_clock_on(dp) == 0) { timeout++; break; } - } while (get_timer(start) <= STREAM_ON_TIMEOUT); + } while (timer_us() < end); if (!timeout) { - printk(BIOS_DEBUG, "Video Clock Not ok\n"); + printk(BIOS_DEBUG, "Video Clock Not ok after %uus.\n", + timer_us() - start); return -ERR_VIDEO_CLOCK_BAD; } @@ -255,7 +297,6 @@ static int s5p_dp_enable_rx_to_enhanced_mode(struct s5p_dp_device *dp) printk(BIOS_DEBUG, "DPCD read error\n"); return -ERR_DPCD_READ_ERROR1; } - if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, DPCD_ENHANCED_FRAME_EN | (data & DPCD_LANE_COUNT_SET_MASK))) { @@ -408,6 +449,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, unsigned int max_lane, unsigned int max_rate) { + int pll_is_locked = 0; u32 data; u32 start; int lane; @@ -417,14 +459,15 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, clrbits_le32(&base->video_ctl_1, VIDEO_EN); start = get_timer(0); - while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + while ((pll_is_locked = s5p_dp_get_pll_lock_status(dp)) == PLL_UNLOCKED) { if (get_timer(start) > PLL_LOCK_TIMEOUT) { /* Ignore this error, and try to continue */ printk(BIOS_ERR, "PLL is not locked yet.\n"); break; } } - + printk(BIOS_SPEW, "PLL is %slocked\n", + pll_is_locked == PLL_LOCKED ? "": "not "); /* Reset Macro */ setbits_le32(&base->dp_phy_test, MACRO_RST); @@ -448,6 +491,9 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, s5p_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); s5p_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); + printk(BIOS_SPEW, "%s: rate 0x%x, lane_count %d\n", __func__, + dp->link_train.link_rate, dp->link_train.lane_count); + if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { printk(BIOS_DEBUG, "Rx Max Link Rate is abnormal :%x !\n", @@ -470,21 +516,27 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, dp->link_train.link_rate = max_rate; /* Set link rate and count as you want to establish*/ + printk(BIOS_SPEW, "Set link rate and count\n"); writel(dp->link_train.lane_count, &base->lane_count_set); writel(dp->link_train.link_rate, &base->link_bw_set); /* Set sink to D0 (Sink Not Ready) mode. */ + printk(BIOS_SPEW, "Set sink rate to D0\n"); s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE, DPCD_SET_POWER_STATE_D0); /* Start HW link training */ + printk(BIOS_SPEW, "Start Link hardware training\n"); writel(HW_TRAINING_EN, &base->dp_hw_link_training); - /* Wait unitl HW link training done */ + /* Wait until HW link training done */ + printk(BIOS_SPEW, "Wait until HW link training done\n"); s5p_dp_wait_hw_link_training_done(dp); + printk(BIOS_SPEW, "HW link training done\n"); /* Get hardware link training status */ data = readl(&base->dp_hw_link_training); + printk(BIOS_SPEW, "hardware link training status: 0x%08x\n", data); if (data != 0) { printk(BIOS_DEBUG, " H/W link training failure: 0x%x\n", data); return -ERR_LINK_TRAINING_FAILURE; @@ -497,6 +549,8 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, data = readl(&base->lane_count_set); dp->link_train.lane_count = data; + printk(BIOS_SPEW, "Done training: Link bandwidth: 0x%x, lane_count: %d\n", + dp->link_train.link_rate, data); return 0; } @@ -533,12 +587,14 @@ int dp_controller_init(struct s5p_dp_device *dp_device) /* Minimum delay after H/w Link training */ udelay(1000); + printk(BIOS_DEBUG, "call s5p_dp_enable_scramble\n"); ret = s5p_dp_enable_scramble(dp); if (ret) { printk(BIOS_DEBUG, "unable to set scramble mode\n"); return ret; } + printk(BIOS_DEBUG, "call s5p_dp_enable_rx_to_enhanced_mode\n"); ret = s5p_dp_enable_rx_to_enhanced_mode(dp); if (ret) { printk(BIOS_DEBUG, "unable to set enhanced mode\n"); @@ -553,7 +609,9 @@ int dp_controller_init(struct s5p_dp_device *dp_device) writel(dp->link_train.lane_count, &base->lane_count_set); writel(dp->link_train.link_rate, &base->link_bw_set); + printk(BIOS_DEBUG, "call s5p_dp_init_video\n"); s5p_dp_init_video(dp); + printk(BIOS_DEBUG, "call s5p_dp_config_video\n"); ret = s5p_dp_config_video(dp, dp->video_info); if (ret) { printk(BIOS_DEBUG, "unable to config video\n"); diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c index 60e1398..6b5cd69 100644 --- a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c +++ b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c @@ -102,6 +102,8 @@ unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp) u32 reg; reg = readl(&dp->base->dp_debug_ctl); + printk(BIOS_SPEW, "%s: reg is 0x%x, PLL_LOCK is 0x%x\n", + __func__, reg, PLL_LOCK); if (reg & PLL_LOCK) return PLL_LOCKED; else @@ -129,7 +131,8 @@ int s5p_dp_init_analog_func(struct s5p_dp_device *dp) start = get_timer(0); while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { if (get_timer(start) > PLL_LOCK_TIMEOUT) { - printk(BIOS_DEBUG, "%s: PLL is not locked yet\n", __func__); + printk(BIOS_DEBUG, "%s: PLL is not locked\n", + __func__); return -1; } } @@ -176,8 +179,9 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp) /* Enable AUX CH operation */ setbits_le32(&base->aux_ch_ctl_2, AUX_EN); - printk(BIOS_DEBUG, "%s: base: 0x%p, &base->aux_ch_ctl_2: 0x%p, aux_ch_ctl_2: 0x%08x\n", - __func__, base, &base->aux_ch_ctl_2, readl(&base->aux_ch_ctl_2)); + printk(BIOS_DEBUG, "%s: base: 0x%p, &base->aux_ch_ctl_2: 0x%p, " + "aux_ch_ctl_2: 0x%08x\n", __func__, base, &base->aux_ch_ctl_2, + readl(&base->aux_ch_ctl_2)); /* Is AUX CH command reply received? */ reg = readl(&base->dp_int_sta); diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 09b670e..677b0f4 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -5,6 +5,7 @@ #include <console/console.h> #include <device/device.h> #include <cbmem.h> +#include <arch/cache.h> #include <cpu/samsung/exynos5250/fimd.h> #include <cpu/samsung/exynos5-common/s5p-dp-core.h> #include "chip.h" @@ -32,7 +33,6 @@ static void exynos_displayport_init(device_t dev) unsigned long int fb_size; u32 lcdbase; - printk(BIOS_SPEW, "%s: dev 0x%p, conf 0x%p\n", __func__, dev, conf); memset(&vi, 0, sizeof(vi)); memset(&panel, 0, sizeof(panel)); @@ -61,16 +61,35 @@ static void exynos_displayport_init(device_t dev) * The size is a magic number from hardware. Allocate enough for the * frame buffer and color map. */ - fb_size = conf->xres * conf->yres * sizeof(unsigned long); + fb_size = conf->xres * conf->yres * (conf->bpp / 8); lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size + 64*KiB); printk(BIOS_SPEW, "lcd colormap base is %p\n", (void *)(lcdbase)); mmio_resource(dev, 0, lcdbase/KiB, 64); vi.cmap = (void *)lcdbase; + /* + * We need to clean and invalidate the framebuffer region and disable + * caching as well. We assume that our dcache <--> memory address + * space is identity-mapped in 1MB chunks, so align accordingly. + * + * Note: We may want to do something clever to ensure the framebuffer + * region is aligned such that we don't change dcache policy for other + * stuff inadvertantly. + * + * FIXME: Is disabling/re-enabling the MMU entirely necessary? + */ + uint32_t lower = ALIGN_DOWN(lcdbase, MiB); + uint32_t upper = ALIGN_UP(lcdbase + fb_size + 64*KiB, MiB); + dcache_clean_invalidate_by_mva(lower, upper - lower); + dcache_mmu_disable(); + mmu_config_range(lower/MiB, (upper - lower)/MiB, DCACHE_OFF); + dcache_mmu_enable(); + lcdbase += 64*KiB; mmio_resource(dev, 1, lcdbase/KiB, fb_size + (KiB-1)/KiB); printk(BIOS_DEBUG, - "Initializing exynos VGA, base %p\n",(void *)lcdbase); + "Initializing exynos VGA, base %p\n", (void *)lcdbase); + memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase); } diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index 6d3d7c8..c28a986 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -33,6 +33,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EXYNOS_DISPLAYPORT select CHROMEOS select DRIVER_TI_TPS65090 + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_DO_NATIVE_VGA_INIT config MAINBOARD_DIR string diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index 6e46d13..c4e6ef4 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -98,7 +98,12 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_developer_mode_switch(void) { - return 0; + /* + * FIXME: This should return 0, but we hardcode it to 1 to ensure + * coreboot draws the dev mode screen while we're working on this + * patch. + */ + return 1; } int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 1cd84e8..f14c803 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -23,6 +23,7 @@ #include <drivers/ti/tps65090/tps65090.h> #include <cbmem.h> #include <delay.h> +#include <boot/coreboot_tables.h> #include <arch/cache.h> #include <arch/exception.h> #include <arch/gpio.h> @@ -41,6 +42,39 @@ #define DRAM_SIZE CONFIG_DRAM_SIZE_MB #define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ +int vbe_mode_info_valid(void); +int vbe_mode_info_valid(void) +{ + return 1; +} + +void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); +void fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +{ + /* + * The address returned points at the LCD colormap base. The + * 64KiB offset points at the LCD base. + */ + framebuffer->physical_address = + (u32)cbmem_find(CBMEM_ID_CONSOLE) + 64*KiB; + printk(BIOS_SPEW, "%s: framebuffer->physical address is 0x%llx\n", + __func__, framebuffer->physical_address); + + framebuffer->x_resolution = 1366; + framebuffer->y_resolution = 768; + framebuffer->bytes_per_line = 1366*2; /* FIXME: is this correct? */ + framebuffer->bits_per_pixel = 16; + framebuffer->red_mask_pos = 11; + framebuffer->red_mask_size = 5; + framebuffer->green_mask_pos = 6; + framebuffer->green_mask_size = 5; + framebuffer->blue_mask_pos = 0; + framebuffer->blue_mask_size = 5; + framebuffer->reserved_mask_pos = 0; + framebuffer->reserved_mask_size = 0; +} + + void hardwaremain(int boot_complete); void main(void) {

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Patch merged into coreboot/master: 6974396 AMD SB800 based boards: Use `#include <sb_cimx.h>` instead of `"sb_cimx.h"`
by gerrit＠coreboot.org 20 Apr '13

20 Apr '13

the following patch was just integrated into master: commit 69743962617b9de1a0263dc372bd9116671b5025 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Apr 19 10:05:57 2013 +0200 AMD SB800 based boards: Use `#include <sb_cimx.h>` instead of `"sb_cimx.h"` Due to $ more src/southbridge/amd/cimx/sb800/Makefile.inc […] romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c ramstage-y += cfg.c ramstage-y += late.c […] `src/southbridge/amd/cimx/sb800/` is passed with the switch `-I` to the compiler, where it is also going to find the header file `sb_cimx.h`. Therefore use `#include <sb_cimx>` everywhere, which is what some AMD SB800 based boards already do. The only effect is, that the compiler will not needlessly look into directories which do not contain the header file [1]. The following command was used for the replacement. $ git grep -l sb_cimx.h src/mainboard/ | xargs sed -i 's/#include "sb_cimx.h"/#include <sb_cimx.h>/' [1] http://gcc.gnu.org/onlinedocs/cpp/Search-Path.html Change-Id: I96ab34bac1524e6c38c85dfe9d99cb6ef55e6d7c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3118 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Apr 20 05:12:11 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sat Apr 20 18:57:19 2013, giving +2 See http://review.coreboot.org/3118 for details. -gerrit

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coreboot-gerrit April 2013