David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3109
-gerrit
commit 8f53695a6c1e7555eb878bc9113af0fe2beaadf2
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Thu Apr 18 13:46:00 2013 -0700
google/snow: disable unused USB3.0 PLL to save power
This PLL is unused and can be disabled to save about 250mW.
Change-Id: I1be37304d6ea5ff78696e05ad1023ce3c57f636c
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
---
src/mainboard/google/snow/ramstage.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c
index 1cd84e8..54d13d3 100644
--- a/src/mainboard/google/snow/ramstage.c
+++ b/src/mainboard/google/snow/ramstage.c
@@ -198,6 +198,16 @@ static struct video_info snow_dp_video_info = {
#define EXYNOS5250_DP1_BASE 0x145b0000
#define SNOW_MAX_DP_TRIES 5
+/*
+ * This function disables the USB3.0 PLL to save power
+ */
+static void disable_usb30_pll(void)
+{
+ enum exynos5_gpio_pin usb3_pll_l = GPIO_Y11;
+
+ gpio_direction_output(usb3_pll_l, 0);
+}
+
/* this happens after cpu_init where exynos resources are set */
static void mainboard_init(device_t dev)
{
@@ -215,6 +225,9 @@ static void mainboard_init(device_t dev)
/* Clock Gating all the unused IP's to save power */
clock_gate();
+ /* Disable USB3.0 PLL to save 250mW of power */
+ disable_usb30_pll();
+
snow_lcd_vdd();
do {
udelay(50);
the following patch was just integrated into master:
commit 95399327193f9ae23b6cd323cac6a0383c269865
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Thu Apr 18 17:27:07 2013 -0700
exynos5: eliminate lcd_base variable
The original imported code used "lcdbase" and "lcd_base" which quite
predictably caused confusion and bugs. Let's put an end to this little
bit of insanity.
Change-Id: I4f995482cfbff5f23bb296a1e6d35beccf5f8a91
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-on: http://review.coreboot.org/3114
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Tested-by: build bot (Jenkins)
Build-Tested: build bot (Jenkins) at Fri Apr 19 08:05:50 2013, giving +1
See http://review.coreboot.org/3114 for details.
-gerrit
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3109
-gerrit
commit 12c6b4885b031a1f1fbc6a22b0ce494316a9c6f7
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Thu Apr 18 13:46:00 2013 -0700
google/snow: disable unused USB3.0 PLL to save power
This PLL is unused and can be disabled to save about 250mW.
Change-Id: I1be37304d6ea5ff78696e05ad1023ce3c57f636c
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
---
src/mainboard/google/snow/ramstage.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c
index 1cd84e8..54d13d3 100644
--- a/src/mainboard/google/snow/ramstage.c
+++ b/src/mainboard/google/snow/ramstage.c
@@ -198,6 +198,16 @@ static struct video_info snow_dp_video_info = {
#define EXYNOS5250_DP1_BASE 0x145b0000
#define SNOW_MAX_DP_TRIES 5
+/*
+ * This function disables the USB3.0 PLL to save power
+ */
+static void disable_usb30_pll(void)
+{
+ enum exynos5_gpio_pin usb3_pll_l = GPIO_Y11;
+
+ gpio_direction_output(usb3_pll_l, 0);
+}
+
/* this happens after cpu_init where exynos resources are set */
static void mainboard_init(device_t dev)
{
@@ -215,6 +225,9 @@ static void mainboard_init(device_t dev)
/* Clock Gating all the unused IP's to save power */
clock_gate();
+ /* Disable USB3.0 PLL to save 250mW of power */
+ disable_usb30_pll();
+
snow_lcd_vdd();
do {
udelay(50);
the following patch was just integrated into master:
commit ec10ce8971221463314bf1f88e054e1d399bd7a9
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Thu Apr 18 16:45:47 2013 -0700
google/snow: Minor clean-ups for display setup code in ramstage
This just cleans up a few areas:
- Removed an unnecessary delay from exynos_dp_bridge_setup()
- The delay at the end of exynos_dp_bridge_init() is necessary, so
removed the comment suggesting that it might not be.
- Simplified exynos_dp_hotplug
Change-Id: I44150f5ef3958e333985440c1022b4f1544a93aa
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-on: http://review.coreboot.org/3113
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Fri Apr 19 07:38:40 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri Apr 19 18:24:14 2013, giving +2
See http://review.coreboot.org/3113 for details.
-gerrit
the following patch was just integrated into master:
commit 954d25484b0f4d4881c1b6d5662c587c85c920a2
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Thu Apr 18 13:49:57 2013 -0700
google/snow: enable clock gating to save power
This enables clock gating to save power on unused IPs.
Change-Id: I9ab2a2535ebb91bb4110390a6f055a67146bdbf9
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-on: http://review.coreboot.org/3110
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Fri Apr 19 13:36:58 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri Apr 19 18:22:51 2013, giving +2
See http://review.coreboot.org/3110 for details.
-gerrit
the following patch was just integrated into master:
commit 8a275c1810ecd1aa2cec543c14696313f379a9ee
Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com>
Date: Mon Apr 15 19:10:24 2013 +0800
AMD Parmer: change DdiList to ConnectorTypeDP to support DP and HDMI
This patch is based on >>AMD Thatcher: ConnectorTypeDP supports both DP and HDMI<< (I23cf1c6) [1]
I tested by DP monitor and HDMI monitor connected by passive DP->HDMI adapter.
Video and audio are OK. Hot plugging is also supported.
[1] http://review.coreboot.org/#/c/3088/
Change-Id: I291beff43609ecb68ece24939f2dbc7c08dd0374
Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com>
Reviewed-on: http://review.coreboot.org/3090
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Fri Apr 19 14:03:42 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri Apr 19 18:17:13 2013, giving +2
See http://review.coreboot.org/3090 for details.
-gerrit
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3109
-gerrit
commit a771190124f645283db0b12f16b4f84933aca1e7
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Thu Apr 18 13:46:00 2013 -0700
google/snow: disable unused USB3.0 PLL to save power
This PLL is unused and can be disabled to save about 250mW.
Change-Id: I1be37304d6ea5ff78696e05ad1023ce3c57f636c
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
---
src/mainboard/google/snow/ramstage.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c
index f3dad4a..492ac07 100644
--- a/src/mainboard/google/snow/ramstage.c
+++ b/src/mainboard/google/snow/ramstage.c
@@ -206,6 +206,16 @@ static struct video_info snow_dp_video_info = {
#define EXYNOS5250_DP1_BASE 0x145b0000
#define SNOW_MAX_DP_TRIES 5
+/*
+ * This function disables the USB3.0 PLL to save power
+ */
+static void disable_usb30_pll(void)
+{
+ enum exynos5_gpio_pin usb3_pll_l = GPIO_Y11;
+
+ gpio_direction_output(usb3_pll_l, 0);
+}
+
/* this happens after cpu_init where exynos resources are set */
static void mainboard_init(device_t dev)
{
@@ -220,6 +230,9 @@ static void mainboard_init(device_t dev)
tmu_init(&exynos5250_tmu_info);
+ /* Disable USB3.0 PLL to save 250mW of power */
+ disable_usb30_pll();
+
snow_lcd_vdd();
do {
udelay(50);
the following patch was just integrated into master:
commit d83c117e86acf21f179495f7a607f9a2fd9349a2
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Thu Apr 18 16:10:29 2013 -0700
exynos5250: get xres and yres out of the device tree and into the panel descriptor
We neglected to copy xres and yres out; now we do.
Change-Id: Icc4a8eb35799d156b11274f71bcfb4a1d10e01e3
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
Reviewed-on: http://review.coreboot.org/3111
Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
Tested-by: build bot (Jenkins)
Build-Tested: build bot (Jenkins) at Fri Apr 19 12:34:42 2013, giving +1
Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Fri Apr 19 05:27:26 2013, giving +2
See http://review.coreboot.org/3111 for details.
-gerrit