coreboot-gerrit April 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 642b1db Eliminate use of pointers in coreboot table
by gerrit＠coreboot.org 20 Apr '13

20 Apr '13

the following patch was just integrated into master: commit 642b1db7336d4770d882684e42157103f3f38b19 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Apr 18 18:01:34 2013 -0700 Eliminate use of pointers in coreboot table Because pointers can be 32bit or 64bit big, using them in the coreboot table requires the OS and the firmware to operate in the same mode which is not always the case. Hence, use 64bit for all pointers stored in the coreboot table. Guess we'll have to fix this up once we port to the first 128bit machines. Change-Id: I46fc1dad530e5230986f7aa5740595428ede4f93 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/3115 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> Build-Tested: build bot (Jenkins) at Sat Apr 20 02:28:48 2013, giving +1 See http://review.coreboot.org/3115 for details. -gerrit

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New patch to review for coreboot: e82bb73 AMD SB800 based boards: Use `#include <sb_cimx.h>` instead of `"sb_cimx.h"`
by Paul Menzel 20 Apr '13

20 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3118 -gerrit commit e82bb73d59a3c907dc42a83a1e851a5a4b6a7295 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Apr 19 10:05:57 2013 +0200 AMD SB800 based boards: Use `#include <sb_cimx.h>` instead of `"sb_cimx.h"` Due to $ more src/southbridge/amd/cimx/sb800/Makefile.inc […] romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c ramstage-y += cfg.c ramstage-y += late.c […] `src/southbridge/amd/cimx/sb800/` is passed with the switch `-I` to the compiler, where it is also going to find the header file `sb_cimx.h`. Therefore use `#include <sb_cimx>` everywhere, which is what some AMD SB800 based boards already do. The only effect is, that the compiler will not needlessly look into directories which do not contain the header file [1]. The following command was used for the replacement. $ git grep -l sb_cimx.h src/mainboard/ | xargs sed -i 's/#include "sb_cimx.h"/#include <sb_cimx.h>/' [1] http://gcc.gnu.org/onlinedocs/cpp/Search-Path.html Change-Id: I96ab34bac1524e6c38c85dfe9d99cb6ef55e6d7c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/dinar/romstage.c | 2 +- src/mainboard/amd/inagua/romstage.c | 2 +- src/mainboard/amd/persimmon/romstage.c | 2 +- src/mainboard/amd/south_station/romstage.c | 2 +- src/mainboard/amd/union_station/romstage.c | 2 +- src/mainboard/asrock/e350m1/get_bus_conf.c | 2 +- src/mainboard/asrock/e350m1/romstage.c | 2 +- src/mainboard/lippert/frontrunner-af/romstage.c | 2 +- src/mainboard/lippert/toucan-af/romstage.c | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index a59d142..a9bcde0 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -34,7 +34,7 @@ #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" #include "nb_cimx.h" -#include "sb_cimx.h" +#include <sb_cimx.h> #include "Platform.h" #include <arch/cpu.h> diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index a03d5a7..d46d4ab 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -35,7 +35,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" -#include "sb_cimx.h" +#include <sb_cimx.h> #include "SBPLATFORM.h" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 0c8c456..eedae56 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -35,7 +35,7 @@ #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" #include <cpu/x86/cache.h> -#include "sb_cimx.h" +#include <sb_cimx.h> #include "SBPLATFORM.h" #include "cbmem.h" #include "cpu/amd/mtrr.h" diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 88c6490..c273344 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -33,7 +33,7 @@ #include "cpu/x86/bist.h" #include "superio/fintek/f81865f/f81865f_early_serial.c" #include "cpu/x86/lapic/boot_cpu.c" -#include "sb_cimx.h" +#include <sb_cimx.h> #include "SBPLATFORM.h" #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 4538157..9045c04 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -32,7 +32,7 @@ #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic/boot_cpu.c" -#include "sb_cimx.h" +#include <sb_cimx.h> #include "SBPLATFORM.h" #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c index 1419d79..cbe19d8 100644 --- a/src/mainboard/asrock/e350m1/get_bus_conf.c +++ b/src/mainboard/asrock/e350m1/get_bus_conf.c @@ -26,7 +26,7 @@ #include <cpu/amd/amdfam14.h> #include "agesawrapper.h" #if CONFIG_AMD_SB_CIMX -#include "sb_cimx.h" +#include <sb_cimx.h> #endif diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 79f963b..96339b9 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -34,7 +34,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" -#include "sb_cimx.h" +#include <sb_cimx.h> #include "SBPLATFORM.h" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 0e1b134..b04b0ea 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -35,7 +35,7 @@ #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" #include <cpu/x86/cache.h> -#include "sb_cimx.h" +#include <sb_cimx.h> #include "SBPLATFORM.h" #include "cbmem.h" #include "cpu/amd/mtrr.h" diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 043af85..b5ff31f 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -35,7 +35,7 @@ #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" #include <cpu/x86/cache.h> -#include "sb_cimx.h" +#include <sb_cimx.h> #include "SBPLATFORM.h" #include "cbmem.h" #include "cpu/amd/mtrr.h"

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Patch set updated for coreboot: 0409e88 cbmem utility: compatibility with older coreboot versions
by Stefan Reinauer 20 Apr '13

20 Apr '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3117 -gerrit commit 0409e88dded8e9815a9c9e7ffa00dadc67928c63 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Apr 19 14:22:29 2013 -0700 cbmem utility: compatibility with older coreboot versions Commit b8ad224 changed the memory address in lb_cbmem_ref coreboot table entries from a pointer to a uint64_t. This change was introduced to make the cbmem utility work on both 32bit and 64bit userland. Unfortunately, this broke the cbmem utility running on older versions of coreboot because they were still providing a 32bit only field for the address while the cbmem utility would now take the following 4 bytes as upper 32bits of a pointer that can obviously not be mmapped. This change checks if the size of the lb_cbmem_ref structure provided by coreboot is smaller than expected, and if so, ignore the upper 32bit of the address read. Also make the memory mapping more robust by using O_SYNC and O_DIRECT when opening /dev/mem and fix a potential type conflict in a debug message. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I9dff766a89663322b1854b425ca5fd32e9e502d7 --- util/cbmem/cbmem.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 1ff9a08..99a826e 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -21,6 +21,7 @@ #include <stdlib.h> #include <string.h> #include <unistd.h> +#include <inttypes.h> #include <getopt.h> #include <errno.h> #include <fcntl.h> @@ -127,12 +128,31 @@ static struct lb_cbmem_ref timestamps; static struct lb_cbmem_ref console; static struct lb_memory_range cbmem; +/* This is a work-around for a nasty problem introduced by initially having + * pointer sized entries in the lb_cbmem_ref structures. This caused problems + * on 64bit x86 systems because coreboot is 32bit on those systems. + * When the problem was found, it was corrected, but there are a lot of + * systems out there with a firmware that does not produce the right + * lb_cbmem_ref structure. Hence we try to autocorrect this issue here. + */ +static struct lb_cbmem_ref parse_cbmem_ref(struct lb_cbmem_ref *cbmem_ref) +{ + struct lb_cbmem_ref ret; + + ret = *cbmem_ref; + + if (cbmem_ref->size < sizeof(*cbmem_ref)) + ret.cbmem_addr = (uint32_t)ret.cbmem_addr; + + return ret; +} + static int parse_cbtable(u64 address) { int i, found = 0; void *buf; - debug("Looking for coreboot table at %llx\n", address); + debug("Looking for coreboot table at %" PRIx64 "\n", address); buf = map_memory(address); /* look at every 16 bytes within 4K of the base */ @@ -183,12 +203,12 @@ static int parse_cbtable(u64 address) } case LB_TAG_TIMESTAMPS: { debug(" Found timestamp table.\n"); - timestamps = *(struct lb_cbmem_ref *) lbr_p; + timestamps = parse_cbmem_ref((struct lb_cbmem_ref *) lbr_p); continue; } case LB_TAG_CBMEM_CONSOLE: { debug(" Found cbmem console.\n"); - console = *(struct lb_cbmem_ref *) lbr_p; + console = parse_cbmem_ref((struct lb_cbmem_ref *) lbr_p); continue; } case LB_TAG_FORWARD: { @@ -603,7 +623,7 @@ int main(int argc, char** argv) } } - fd = open("/dev/mem", O_RDONLY, 0); + fd = open("/dev/mem", O_RDONLY | O_SYNC | O_DIRECT, 0); if (fd < 0) { fprintf(stderr, "Failed to gain memory access: %s\n", strerror(errno));

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Patch set updated for coreboot: 0845e1a GOOGLE/SNOW: get graphics working
by David Hendricks 20 Apr '13

20 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3116 -gerrit commit 0845e1a4a8f834d62b98a0e557e3675a7f8bcb5f Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Apr 18 18:09:24 2013 -0700 GOOGLE/SNOW: get graphics working This adds preliminary support for display bring-up on Snow. It includes framebuffer initialization and LCD enable functions. Change-Id: I16e711c97e9d02c916824f621e2313297448732b Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/exynos-fb.c | 84 ++++++++++++++++++++++++----- src/cpu/samsung/exynos5-common/s5p-dp-reg.c | 10 ++-- src/cpu/samsung/exynos5250/cpu.c | 6 ++- src/mainboard/google/snow/Kconfig | 2 + src/mainboard/google/snow/chromeos.c | 7 ++- src/mainboard/google/snow/ramstage.c | 34 ++++++++++++ 6 files changed, 125 insertions(+), 18 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index 54a2d7a..cdb5881 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -27,6 +27,7 @@ #include <arch/io.h> #include <stdlib.h> #include <string.h> +#include <time.h> #include <console/console.h> #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/power.h> @@ -41,6 +42,28 @@ #include "cpu/samsung/exynos5250/s5p-dp.h" #include "s5p-dp-core.h" +/* + * Here is the rough outline of how we bring up the display: + * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD + * 2. Source determines video mode by reading DPCD receiver capability field + * (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD + * 0000Dh). + * 3. Sink replies DPCD receiver capability field. + * 4. Source starts EDID read thru I2C-over-AUX. + * 5. Sink replies EDID thru I2C-over-AUX. + * 6. Source determines link configuration, such as MAX_LINK_RATE and + * MAX_LANE_COUNT. Source also determines which type of eDP Authentication + * method to use and writes DPCD link configuration field (DPCD 00100h to + * 0010Ah) including eDP configuration set (DPCD 0010Ah). + * 7. Source starts link training. Sink does clock recovery and equalization. + * 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh). + * 9. Sink replies DPCD link status field. If main link is not stable, Source + * repeats Step 7. + * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video + * parameters and recovers stream clock. + * 11. Source sends video data. + */ + /* To help debug any init errors here, define a list of possible errors */ enum { ERR_PLL_NOT_UNLOCKED = 2, @@ -126,38 +149,54 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, { unsigned int val; u32 fbsize; - struct exynos5_fimd *fimd = - samsung_get_base_fimd(); - struct exynos5_disp_ctrl *disp_ctrl = - samsung_get_base_disp_ctrl(); - + struct exynos5_fimd *fimd = samsung_get_base_fimd(); + struct exynos5_disp_ctrl *disp_ctrl = samsung_get_base_disp_ctrl(); + + printk(BIOS_SPEW, "%s: fimd %p disp_ctrl %p\n", + __func__, fimd, disp_ctrl); + printk(BIOS_SPEW, "pd %p\n", pd); + printk(BIOS_SPEW, "lcdbase %p\n", lcdbase); + printk(BIOS_SPEW, "pd->xres %d pd->yres %d\n", pd->xres, pd->yres); + printk(BIOS_SPEW, "Write %08x to %p\n", + pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); writel(pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); val = ENVID_ON | ENVID_F_ON | (pd->clkval_f << CLKVAL_F_OFFSET); + printk(BIOS_SPEW, "Write %08x to fimd->vidcon0\n", val); writel(val, &fimd->vidcon0); val = (pd->vsync << VSYNC_PULSE_WIDTH_OFFSET) | (pd->lower_margin << V_FRONT_PORCH_OFFSET) | (pd->upper_margin << V_BACK_PORCH_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon0); writel(val, &disp_ctrl->vidtcon0); val = (pd->hsync << HSYNC_PULSE_WIDTH_OFFSET) | (pd->right_margin << H_FRONT_PORCH_OFFSET) | (pd->left_margin << H_BACK_PORCH_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon1); writel(val, &disp_ctrl->vidtcon1); val = ((pd->xres - 1) << HOZVAL_OFFSET) | ((pd->yres - 1) << LINEVAL_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon2); writel(val, &disp_ctrl->vidtcon2); + printk(BIOS_SPEW, "Write %08x to %p\n", + (unsigned int)lcdbase, &fimd->vidw00add0b0); writel((unsigned int)lcdbase, &fimd->vidw00add0b0); fbsize = calc_fbsize(panel_info); + printk(BIOS_SPEW, "Write %08x to %p\n", + (unsigned int)fbsize, &fimd->vidw00add1b0); writel((unsigned int)lcdbase + fbsize, &fimd->vidw00add1b0); + printk(BIOS_SPEW, "Write %08x to %p\n", + (unsigned int)pd->xres*2, &fimd->vidw00add0b0); writel(pd->xres * 2, &fimd->vidw00add2); val = ((pd->xres - 1) << OSD_RIGHTBOTX_F_OFFSET); val |= ((pd->yres - 1) << OSD_RIGHTBOTY_F_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &fimd->vidosd0b); writel(val, &fimd->vidosd0b); writel(pd->xres * pd->yres, &fimd->vidosd0c); @@ -165,6 +204,7 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, val = BPPMODE_F_RGB_16BIT_565 << BPPMODE_F_OFFSET; val |= ENWIN_F_ENABLE | HALF_WORD_SWAP_EN; + printk(BIOS_SPEW, "Write %08x to %p\n", val, &fimd->wincon0); writel(val, &fimd->wincon0); /* DPCLKCON_ENABLE */ @@ -191,7 +231,7 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, struct video_info *video_info) { int timeout = 0; - u32 start; + u32 start, end; struct exynos5_dp *base = dp->base; s5p_dp_config_video_slave_mode(dp, video_info); @@ -206,16 +246,18 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, return -ERR_PLL_NOT_UNLOCKED; } - start = get_timer(0); + start = timer_us(); + end = start + STREAM_ON_TIMEOUT*1000; do { if (s5p_dp_is_slave_video_stream_clock_on(dp) == 0) { timeout++; break; } - } while (get_timer(start) <= STREAM_ON_TIMEOUT); + } while (timer_us() < end); if (!timeout) { - printk(BIOS_DEBUG, "Video Clock Not ok\n"); + printk(BIOS_DEBUG, "Video Clock Not ok after %uus.\n", + timer_us() - start); return -ERR_VIDEO_CLOCK_BAD; } @@ -255,7 +297,6 @@ static int s5p_dp_enable_rx_to_enhanced_mode(struct s5p_dp_device *dp) printk(BIOS_DEBUG, "DPCD read error\n"); return -ERR_DPCD_READ_ERROR1; } - if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, DPCD_ENHANCED_FRAME_EN | (data & DPCD_LANE_COUNT_SET_MASK))) { @@ -408,6 +449,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, unsigned int max_lane, unsigned int max_rate) { + int pll_is_locked = 0; u32 data; u32 start; int lane; @@ -417,14 +459,15 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, clrbits_le32(&base->video_ctl_1, VIDEO_EN); start = get_timer(0); - while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + while ((pll_is_locked = s5p_dp_get_pll_lock_status(dp)) == PLL_UNLOCKED) { if (get_timer(start) > PLL_LOCK_TIMEOUT) { /* Ignore this error, and try to continue */ printk(BIOS_ERR, "PLL is not locked yet.\n"); break; } } - + printk(BIOS_SPEW, "PLL is %slocked\n", + pll_is_locked == PLL_LOCKED ? "": "not "); /* Reset Macro */ setbits_le32(&base->dp_phy_test, MACRO_RST); @@ -448,6 +491,9 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, s5p_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); s5p_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); + printk(BIOS_SPEW, "%s: rate 0x%x, lane_count %d\n", __func__, + dp->link_train.link_rate, dp->link_train.lane_count); + if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { printk(BIOS_DEBUG, "Rx Max Link Rate is abnormal :%x !\n", @@ -470,21 +516,27 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, dp->link_train.link_rate = max_rate; /* Set link rate and count as you want to establish*/ + printk(BIOS_SPEW, "Set link rate and count\n"); writel(dp->link_train.lane_count, &base->lane_count_set); writel(dp->link_train.link_rate, &base->link_bw_set); /* Set sink to D0 (Sink Not Ready) mode. */ + printk(BIOS_SPEW, "Set sink rate to D0\n"); s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE, DPCD_SET_POWER_STATE_D0); /* Start HW link training */ + printk(BIOS_SPEW, "Start Link hardware training\n"); writel(HW_TRAINING_EN, &base->dp_hw_link_training); - /* Wait unitl HW link training done */ + /* Wait until HW link training done */ + printk(BIOS_SPEW, "Wait until HW link training done\n"); s5p_dp_wait_hw_link_training_done(dp); + printk(BIOS_SPEW, "HW link training done\n"); /* Get hardware link training status */ data = readl(&base->dp_hw_link_training); + printk(BIOS_SPEW, "hardware link training status: 0x%08x\n", data); if (data != 0) { printk(BIOS_DEBUG, " H/W link training failure: 0x%x\n", data); return -ERR_LINK_TRAINING_FAILURE; @@ -497,6 +549,8 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, data = readl(&base->lane_count_set); dp->link_train.lane_count = data; + printk(BIOS_SPEW, "Done training: Link bandwidth: 0x%x, lane_count: %d\n", + dp->link_train.link_rate, data); return 0; } @@ -533,12 +587,14 @@ int dp_controller_init(struct s5p_dp_device *dp_device) /* Minimum delay after H/w Link training */ udelay(1000); + printk(BIOS_DEBUG, "call s5p_dp_enable_scramble\n"); ret = s5p_dp_enable_scramble(dp); if (ret) { printk(BIOS_DEBUG, "unable to set scramble mode\n"); return ret; } + printk(BIOS_DEBUG, "call s5p_dp_enable_rx_to_enhanced_mode\n"); ret = s5p_dp_enable_rx_to_enhanced_mode(dp); if (ret) { printk(BIOS_DEBUG, "unable to set enhanced mode\n"); @@ -553,7 +609,9 @@ int dp_controller_init(struct s5p_dp_device *dp_device) writel(dp->link_train.lane_count, &base->lane_count_set); writel(dp->link_train.link_rate, &base->link_bw_set); + printk(BIOS_DEBUG, "call s5p_dp_init_video\n"); s5p_dp_init_video(dp); + printk(BIOS_DEBUG, "call s5p_dp_config_video\n"); ret = s5p_dp_config_video(dp, dp->video_info); if (ret) { printk(BIOS_DEBUG, "unable to config video\n"); diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c index 60e1398..6b5cd69 100644 --- a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c +++ b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c @@ -102,6 +102,8 @@ unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp) u32 reg; reg = readl(&dp->base->dp_debug_ctl); + printk(BIOS_SPEW, "%s: reg is 0x%x, PLL_LOCK is 0x%x\n", + __func__, reg, PLL_LOCK); if (reg & PLL_LOCK) return PLL_LOCKED; else @@ -129,7 +131,8 @@ int s5p_dp_init_analog_func(struct s5p_dp_device *dp) start = get_timer(0); while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { if (get_timer(start) > PLL_LOCK_TIMEOUT) { - printk(BIOS_DEBUG, "%s: PLL is not locked yet\n", __func__); + printk(BIOS_DEBUG, "%s: PLL is not locked\n", + __func__); return -1; } } @@ -176,8 +179,9 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp) /* Enable AUX CH operation */ setbits_le32(&base->aux_ch_ctl_2, AUX_EN); - printk(BIOS_DEBUG, "%s: base: 0x%p, &base->aux_ch_ctl_2: 0x%p, aux_ch_ctl_2: 0x%08x\n", - __func__, base, &base->aux_ch_ctl_2, readl(&base->aux_ch_ctl_2)); + printk(BIOS_DEBUG, "%s: base: 0x%p, &base->aux_ch_ctl_2: 0x%p, " + "aux_ch_ctl_2: 0x%08x\n", __func__, base, &base->aux_ch_ctl_2, + readl(&base->aux_ch_ctl_2)); /* Is AUX CH command reply received? */ reg = readl(&base->dp_int_sta); diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 09b670e..44b184f 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -32,7 +32,6 @@ static void exynos_displayport_init(device_t dev) unsigned long int fb_size; u32 lcdbase; - printk(BIOS_SPEW, "%s: dev 0x%p, conf 0x%p\n", __func__, dev, conf); memset(&vi, 0, sizeof(vi)); memset(&panel, 0, sizeof(panel)); @@ -71,6 +70,11 @@ static void exynos_displayport_init(device_t dev) mmio_resource(dev, 1, lcdbase/KiB, fb_size + (KiB-1)/KiB); printk(BIOS_DEBUG, "Initializing exynos VGA, base %p\n",(void *)lcdbase); + /* + * FIXME: This is for testing only. It will color a the top half + * of the screen blue. + */ + memset((void *)lcdbase, 0x55, 0x100000); ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase); } diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index 6d3d7c8..c28a986 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -33,6 +33,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EXYNOS_DISPLAYPORT select CHROMEOS select DRIVER_TI_TPS65090 + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_DO_NATIVE_VGA_INIT config MAINBOARD_DIR string diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index 6e46d13..c4e6ef4 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -98,7 +98,12 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_developer_mode_switch(void) { - return 0; + /* + * FIXME: This should return 0, but we hardcode it to 1 to ensure + * coreboot draws the dev mode screen while we're working on this + * patch. + */ + return 1; } int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 1cd84e8..f14c803 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -23,6 +23,7 @@ #include <drivers/ti/tps65090/tps65090.h> #include <cbmem.h> #include <delay.h> +#include <boot/coreboot_tables.h> #include <arch/cache.h> #include <arch/exception.h> #include <arch/gpio.h> @@ -41,6 +42,39 @@ #define DRAM_SIZE CONFIG_DRAM_SIZE_MB #define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ +int vbe_mode_info_valid(void); +int vbe_mode_info_valid(void) +{ + return 1; +} + +void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); +void fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +{ + /* + * The address returned points at the LCD colormap base. The + * 64KiB offset points at the LCD base. + */ + framebuffer->physical_address = + (u32)cbmem_find(CBMEM_ID_CONSOLE) + 64*KiB; + printk(BIOS_SPEW, "%s: framebuffer->physical address is 0x%llx\n", + __func__, framebuffer->physical_address); + + framebuffer->x_resolution = 1366; + framebuffer->y_resolution = 768; + framebuffer->bytes_per_line = 1366*2; /* FIXME: is this correct? */ + framebuffer->bits_per_pixel = 16; + framebuffer->red_mask_pos = 11; + framebuffer->red_mask_size = 5; + framebuffer->green_mask_pos = 6; + framebuffer->green_mask_size = 5; + framebuffer->blue_mask_pos = 0; + framebuffer->blue_mask_size = 5; + framebuffer->reserved_mask_pos = 0; + framebuffer->reserved_mask_size = 0; +} + + void hardwaremain(int boot_complete); void main(void) {

1 0

Patch set updated for coreboot: c30c9d9 cbmem utility: compatibility with older coreboot versions
by Stefan Reinauer 19 Apr '13

19 Apr '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3117 -gerrit commit c30c9d928c8b78fba8d9161758e4b31f060e4e73 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Apr 19 14:22:29 2013 -0700 cbmem utility: compatibility with older coreboot versions Commit b8ad224 changed the memory address in lb_cbmem_ref coreboot table entries from a pointer to a uint64_t. This change was introduced to make the cbmem utility work on both 32bit and 64bit userland. Unfortunately, this broke the cbmem utility running on older versions of coreboot because they were still providing a 32bit only field for the address while the cbmem utility would now take the following 4 bytes as upper 32bits of a pointer that can obviously not be mmapped. This change checks if the size of the lb_cbmem_ref structure provided by coreboot is smaller than expected, and if so, ignore the upper 32bit of the address read. Also make the memory mapping more robust by using O_SYNC and O_DIRECT when opening /dev/mem and fix a potential type conflict in a debug message. Change-Id: I9dff766a89663322b1854b425ca5fd32e9e502d7 --- util/cbmem/cbmem.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 1ff9a08..99a826e 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -21,6 +21,7 @@ #include <stdlib.h> #include <string.h> #include <unistd.h> +#include <inttypes.h> #include <getopt.h> #include <errno.h> #include <fcntl.h> @@ -127,12 +128,31 @@ static struct lb_cbmem_ref timestamps; static struct lb_cbmem_ref console; static struct lb_memory_range cbmem; +/* This is a work-around for a nasty problem introduced by initially having + * pointer sized entries in the lb_cbmem_ref structures. This caused problems + * on 64bit x86 systems because coreboot is 32bit on those systems. + * When the problem was found, it was corrected, but there are a lot of + * systems out there with a firmware that does not produce the right + * lb_cbmem_ref structure. Hence we try to autocorrect this issue here. + */ +static struct lb_cbmem_ref parse_cbmem_ref(struct lb_cbmem_ref *cbmem_ref) +{ + struct lb_cbmem_ref ret; + + ret = *cbmem_ref; + + if (cbmem_ref->size < sizeof(*cbmem_ref)) + ret.cbmem_addr = (uint32_t)ret.cbmem_addr; + + return ret; +} + static int parse_cbtable(u64 address) { int i, found = 0; void *buf; - debug("Looking for coreboot table at %llx\n", address); + debug("Looking for coreboot table at %" PRIx64 "\n", address); buf = map_memory(address); /* look at every 16 bytes within 4K of the base */ @@ -183,12 +203,12 @@ static int parse_cbtable(u64 address) } case LB_TAG_TIMESTAMPS: { debug(" Found timestamp table.\n"); - timestamps = *(struct lb_cbmem_ref *) lbr_p; + timestamps = parse_cbmem_ref((struct lb_cbmem_ref *) lbr_p); continue; } case LB_TAG_CBMEM_CONSOLE: { debug(" Found cbmem console.\n"); - console = *(struct lb_cbmem_ref *) lbr_p; + console = parse_cbmem_ref((struct lb_cbmem_ref *) lbr_p); continue; } case LB_TAG_FORWARD: { @@ -603,7 +623,7 @@ int main(int argc, char** argv) } } - fd = open("/dev/mem", O_RDONLY, 0); + fd = open("/dev/mem", O_RDONLY | O_SYNC | O_DIRECT, 0); if (fd < 0) { fprintf(stderr, "Failed to gain memory access: %s\n", strerror(errno));

1 0

New patch to review for coreboot: 249dda0 cbmem utility: compatibility with older coreboot versions
by Stefan Reinauer 19 Apr '13

19 Apr '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3117 -gerrit commit 249dda0e71c19b25487451a1bfba0af4a85163ae Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Apr 19 14:22:29 2013 -0700 cbmem utility: compatibility with older coreboot versions Commit b8ad224 changed the memory address in lb_cbmem_ref coreboot table entries from a pointer to a uint64_t. This change was introduced to make the cbmem utility work on both 32bit and 64bit userland. Unfortunately, this broke the cbmem utility running on older versions of coreboot because they were still providing a 32bit only field for the address while the cbmem utility would now take the following 4 bytes as upper 32bits of a pointer that can obviously not be mmapped. This change checks if the size of the lb_cbmem_ref structure provided by coreboot is smaller than expected, and if so, ignore the upper 32bit of the address read. Also make the memory mapping more robust by using O_SYNC and O_DIRECT when opening /dev/mem and fix a potential type conflict in a debug message. Change-Id: I9dff766a89663322b1854b425ca5fd32e9e502d7 --- util/cbmem/cbmem.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 1ff9a08..7e22b18 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -21,6 +21,7 @@ #include <stdlib.h> #include <string.h> #include <unistd.h> +#include <inttypes.h> #include <getopt.h> #include <errno.h> #include <fcntl.h> @@ -127,12 +128,31 @@ static struct lb_cbmem_ref timestamps; static struct lb_cbmem_ref console; static struct lb_memory_range cbmem; +/* This is a work-around for a nasty problem introduced by initially having + * pointer sized entries in the lb_cbmem_ref structures. This caused problems + * on 64bit x86 systems because coreboot is 32bit on those systems. + * When the problem was found, it was corrected, but there are a lot of systems + * out there with a firmware that does not produce the right lb_cbmem_ref structure. + * Hence we try to autocorrect this issue here. + */ +static struct lb_cbmem_ref parse_cbmem_ref(struct lb_cbmem_ref *cbmem_ref) +{ + struct lb_cbmem_ref ret; + + ret = *cbmem_ref; + + if (cbmem_ref->size < sizeof(*cbmem_ref)) + ret.cbmem_addr = (uint32_t)ret.cbmem_addr; + + return ret; +} + static int parse_cbtable(u64 address) { int i, found = 0; void *buf; - debug("Looking for coreboot table at %llx\n", address); + debug("Looking for coreboot table at %" PRIx64 "\n", address); buf = map_memory(address); /* look at every 16 bytes within 4K of the base */ @@ -183,12 +203,12 @@ static int parse_cbtable(u64 address) } case LB_TAG_TIMESTAMPS: { debug(" Found timestamp table.\n"); - timestamps = *(struct lb_cbmem_ref *) lbr_p; + timestamps = parse_cbmem_ref((struct lb_cbmem_ref *) lbr_p); continue; } case LB_TAG_CBMEM_CONSOLE: { debug(" Found cbmem console.\n"); - console = *(struct lb_cbmem_ref *) lbr_p; + console = parse_cbmem_ref((struct lb_cbmem_ref *) lbr_p); continue; } case LB_TAG_FORWARD: { @@ -603,7 +623,7 @@ int main(int argc, char** argv) } } - fd = open("/dev/mem", O_RDONLY, 0); + fd = open("/dev/mem", O_RDONLY | O_SYNC | O_DIRECT, 0); if (fd < 0) { fprintf(stderr, "Failed to gain memory access: %s\n", strerror(errno));

1 0

Patch set updated for coreboot: cbedbb4 Eliminate use of pointers in coreboot table
by Stefan Reinauer 19 Apr '13

19 Apr '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3115 -gerrit commit cbedbb4096b76ede506d635864fa35b4d6de0921 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Apr 18 18:01:34 2013 -0700 Eliminate use of pointers in coreboot table Because pointers can be 32bit or 64bit big, using them in the coreboot table requires the OS and the firmware to operate in the same mode which is not always the case. Hence, use 64bit for all pointers stored in the coreboot table. Guess we'll have to fix this up once we port to the first 128bit machines. Change-Id: I46fc1dad530e5230986f7aa5740595428ede4f93 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/libpayload/include/coreboot_tables.h | 6 +++--- src/include/boot/coreboot_tables.h | 4 ++-- src/lib/coreboot_table.c | 2 +- src/vendorcode/google/chromeos/gnvs.c | 4 ++-- src/vendorcode/google/chromeos/gnvs.h | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 02c9449..3889ede 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -188,7 +188,7 @@ struct cb_gpios { struct cb_vdat { uint32_t tag; uint32_t size; /* size of the entire entry */ - void *vdat_addr; + uint64_t vdat_addr; uint32_t vdat_size; }; @@ -198,7 +198,7 @@ struct cb_vdat { struct cb_cbmem_tab { uint32_t tag; uint32_t size; - void *cbmem_tab; + uint64_t cbmem_tab; }; #define CB_TAG_VBNV 0x0019 @@ -213,7 +213,7 @@ struct cb_vbnv { struct cb_vboot_handoff { uint32_t tag; uint32_t size; - void *vboot_handoff_addr; + uint64_t vboot_handoff_addr; uint32_t vboot_handoff_size; }; diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index a7e4ab0..ee1c29f 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -218,7 +218,7 @@ struct lb_vdat { uint32_t tag; uint32_t size; - void *vdat_addr; + uint64_t vdat_addr; uint32_t vdat_size; }; @@ -246,7 +246,7 @@ struct lb_vboot_handoff { uint32_t tag; uint32_t size; - void *vboot_handoff_addr; + uint64_t vboot_handoff_addr; uint32_t vboot_handoff_size; }; diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 765c510..d25b59d 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -232,7 +232,7 @@ static void lb_vboot_handoff(struct lb_header *header) vbho = (struct lb_vboot_handoff *)lb_new_record(header); vbho->tag = LB_TAB_VBOOT_HANDOFF; vbho->size = sizeof(*vbho); - vbho->vboot_handoff_addr = addr; + vbho->vboot_handoff_addr = (intptr_t)addr; vbho->vboot_handoff_size = size; } #else diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 0d40950..5ee3665 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -79,8 +79,8 @@ void chromeos_set_me_hash(u32 *hash, int len) memcpy(me_hash_saved, hash, len*sizeof(u32)); } -void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size) +void acpi_get_vdat_info(uint64_t *vdat_addr, uint32_t *vdat_size) { - *vdat_addr = vboot_data; + *vdat_addr = (intptr_t)vboot_data; *vdat_size = sizeof(*vboot_data); } diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 4067494..00fe443 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -64,6 +64,6 @@ typedef struct { extern chromeos_acpi_t *vboot_data; void chromeos_init_vboot(chromeos_acpi_t *chromeos); void chromeos_set_me_hash(u32*, int); -void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size); +void acpi_get_vdat_info(uint64_t *vdat_addr, uint32_t *vdat_size); #endif

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Patch merged into coreboot/master: 8d5bc9f google/snow: disable unused USB3.0 PLL to save power
by gerrit＠coreboot.org 19 Apr '13

19 Apr '13

the following patch was just integrated into master: commit 8d5bc9f7726ac70e1c1a4f293827d67628650824 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Apr 18 13:46:00 2013 -0700 google/snow: disable unused USB3.0 PLL to save power This PLL is unused and can be disabled to save about 250mW. Change-Id: I1be37304d6ea5ff78696e05ad1023ce3c57f636c Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/3109 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Apr 19 22:29:46 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri Apr 19 23:10:05 2013, giving +2 See http://review.coreboot.org/3109 for details. -gerrit

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Patch set updated for coreboot: 742368a GOOGLE/SNOW: get graphics working
by David Hendricks 19 Apr '13

19 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3116 -gerrit commit 742368ac893bad6a39fee9ae531737e5500421f2 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Apr 18 18:09:24 2013 -0700 GOOGLE/SNOW: get graphics working draft patch, needs cleanup, but we've got pictures. Change-Id: I16e711c97e9d02c916824f621e2313297448732b Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5-common/exynos-fb.c | 71 +++++++++++++++++++++++++---- src/cpu/samsung/exynos5-common/s5p-dp-reg.c | 6 +++ src/cpu/samsung/exynos5250/cpu.c | 2 +- src/mainboard/google/snow/Kconfig | 2 + src/mainboard/google/snow/chromeos.c | 4 +- src/mainboard/google/snow/ramstage.c | 51 ++++++++++++++++++++- 6 files changed, 123 insertions(+), 13 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index 54a2d7a..1bb97a7 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -27,6 +27,7 @@ #include <arch/io.h> #include <stdlib.h> #include <string.h> +#include <time.h> #include <console/console.h> #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/power.h> @@ -41,6 +42,24 @@ #include "cpu/samsung/exynos5250/s5p-dp.h" #include "s5p-dp-core.h" +/* useful information. Here is the rough outline of how we bring up the display. + *1. Upon power-on Sink generates a hot plug detection pulse thru HPD + *2. Source determines video mode by reading DPCD receiver capability field (DPCD 00000h to + * 0000Dh) including eDP CP capability register (DPCD 0000Dh) + *3. Sink replies DPCD receiver capability field. + *4. Source starts EDID read thru I2C-over-AUX + *5. Sink replies EDID thru I2C-over-AUX + *6. Source determines link configuration, such as MAX_LINK_RATE and + * MAX_LANE_COUNT. Source also determines which type of eDP Authentication method + * to use and writes DPCD link configuration field (DPCD 00100h to 0010Ah) including eDP + * configuration set (DPCD 0010Ah). + *7. Source starts link training. Sink does clock recovery and equalization + *8. Source reads DPCD link status field (DPCD 00200h to 0020Bh) + *9. Sink replies DPCD link status field. If main link is not stable, Source repeats Step 7. + *10. Source sends MSA (Main Stream Attribute) data. Sink extracts video parameters and + * recovers stream clock. + *11. Source sends video data + */ /* To help debug any init errors here, define a list of possible errors */ enum { ERR_PLL_NOT_UNLOCKED = 2, @@ -126,38 +145,51 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, { unsigned int val; u32 fbsize; - struct exynos5_fimd *fimd = + struct exynos5_fimd *fimd = //14400000 samsung_get_base_fimd(); - struct exynos5_disp_ctrl *disp_ctrl = + struct exynos5_disp_ctrl *disp_ctrl = //14420000 samsung_get_base_disp_ctrl(); + printk(BIOS_SPEW, "%s: fimd %p disp_ctrl %p\n", __func__, fimd, disp_ctrl); + printk(BIOS_SPEW, "pd %p\n", pd); + printk(BIOS_SPEW, "lcdbase %p\n", lcdbase); + printk(BIOS_SPEW, "pd->xres %d pd->yres %d\n", pd->xres, pd->yres); + printk(BIOS_SPEW, "Write %08x to %p\n", pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); writel(pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); val = ENVID_ON | ENVID_F_ON | (pd->clkval_f << CLKVAL_F_OFFSET); + printk(BIOS_SPEW, "Write %08x to fimd->vidcon0\n", val); writel(val, &fimd->vidcon0); val = (pd->vsync << VSYNC_PULSE_WIDTH_OFFSET) | (pd->lower_margin << V_FRONT_PORCH_OFFSET) | (pd->upper_margin << V_BACK_PORCH_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon0); writel(val, &disp_ctrl->vidtcon0); val = (pd->hsync << HSYNC_PULSE_WIDTH_OFFSET) | (pd->right_margin << H_FRONT_PORCH_OFFSET) | (pd->left_margin << H_BACK_PORCH_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon1); writel(val, &disp_ctrl->vidtcon1); val = ((pd->xres - 1) << HOZVAL_OFFSET) | ((pd->yres - 1) << LINEVAL_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon2); writel(val, &disp_ctrl->vidtcon2); + printk(BIOS_SPEW, "Write %08x to %p\n", (unsigned int)lcdbase, &fimd->vidw00add0b0); writel((unsigned int)lcdbase, &fimd->vidw00add0b0); fbsize = calc_fbsize(panel_info); + printk(BIOS_SPEW, "Write %08x to %p\n", (unsigned int)fbsize, &fimd->vidw00add1b0); writel((unsigned int)lcdbase + fbsize, &fimd->vidw00add1b0); + printk(BIOS_SPEW, "Write %08x to %p\n", (unsigned int)pd->xres*2, &fimd->vidw00add0b0); writel(pd->xres * 2, &fimd->vidw00add2); val = ((pd->xres - 1) << OSD_RIGHTBOTX_F_OFFSET); val |= ((pd->yres - 1) << OSD_RIGHTBOTY_F_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &fimd->vidosd0b); writel(val, &fimd->vidosd0b); writel(pd->xres * pd->yres, &fimd->vidosd0c); @@ -165,6 +197,7 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, val = BPPMODE_F_RGB_16BIT_565 << BPPMODE_F_OFFSET; val |= ENWIN_F_ENABLE | HALF_WORD_SWAP_EN; + printk(BIOS_SPEW, "Write %08x to %p\n", val, &fimd->wincon0); writel(val, &fimd->wincon0); /* DPCLKCON_ENABLE */ @@ -191,7 +224,7 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, struct video_info *video_info) { int timeout = 0; - u32 start; + u32 start, end; struct exynos5_dp *base = dp->base; s5p_dp_config_video_slave_mode(dp, video_info); @@ -206,16 +239,17 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, return -ERR_PLL_NOT_UNLOCKED; } - start = get_timer(0); + start = timer_us(); + end = start + STREAM_ON_TIMEOUT*1000; do { if (s5p_dp_is_slave_video_stream_clock_on(dp) == 0) { timeout++; break; } - } while (get_timer(start) <= STREAM_ON_TIMEOUT); + } while (timer_us() < end); if (!timeout) { - printk(BIOS_DEBUG, "Video Clock Not ok\n"); + printk(BIOS_DEBUG, "Video Clock Not ok after %d microseconds waiting\n", timer_us() - start); return -ERR_VIDEO_CLOCK_BAD; } @@ -255,7 +289,7 @@ static int s5p_dp_enable_rx_to_enhanced_mode(struct s5p_dp_device *dp) printk(BIOS_DEBUG, "DPCD read error\n"); return -ERR_DPCD_READ_ERROR1; } - + /* let's not do this and see if it gets better */ if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, DPCD_ENHANCED_FRAME_EN | (data & DPCD_LANE_COUNT_SET_MASK))) { @@ -408,23 +442,25 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, unsigned int max_lane, unsigned int max_rate) { + int pll_is_locked = 0; u32 data; u32 start; int lane; struct exynos5_dp *base = dp->base; + printk(BIOS_SPEW, "%s: start\n", __func__); /* Stop Video */ clrbits_le32(&base->video_ctl_1, VIDEO_EN); start = get_timer(0); - while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + while ((pll_is_locked = s5p_dp_get_pll_lock_status(dp)) == PLL_UNLOCKED) { if (get_timer(start) > PLL_LOCK_TIMEOUT) { /* Ignore this error, and try to continue */ printk(BIOS_ERR, "PLL is not locked yet.\n"); break; } } - + printk(BIOS_SPEW, "PLL is %slocked\n", pll_is_locked == PLL_LOCKED ? "": "un"); /* Reset Macro */ setbits_le32(&base->dp_phy_test, MACRO_RST); @@ -448,6 +484,9 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, s5p_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); s5p_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); + printk(BIOS_SPEW, "%s: rate 0x%x, lane_count %d\n", __func__, + dp->link_train.link_rate, dp->link_train.lane_count); + if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { printk(BIOS_DEBUG, "Rx Max Link Rate is abnormal :%x !\n", @@ -470,21 +509,27 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, dp->link_train.link_rate = max_rate; /* Set link rate and count as you want to establish*/ + printk(BIOS_SPEW, "Set link rate and count\n"); writel(dp->link_train.lane_count, &base->lane_count_set); writel(dp->link_train.link_rate, &base->link_bw_set); /* Set sink to D0 (Sink Not Ready) mode. */ + printk(BIOS_SPEW, "Set sink rate to D0\n"); s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE, DPCD_SET_POWER_STATE_D0); /* Start HW link training */ + printk(BIOS_SPEW, "Start Link hardware training\n"); writel(HW_TRAINING_EN, &base->dp_hw_link_training); - /* Wait unitl HW link training done */ + /* Wait until HW link training done */ + printk(BIOS_SPEW, "Wait until HW link training done\n"); s5p_dp_wait_hw_link_training_done(dp); + printk(BIOS_SPEW, "HW link training done\n"); /* Get hardware link training status */ data = readl(&base->dp_hw_link_training); + printk(BIOS_SPEW, "hardware link training status: 0x%08x\n", data); if (data != 0) { printk(BIOS_DEBUG, " H/W link training failure: 0x%x\n", data); return -ERR_LINK_TRAINING_FAILURE; @@ -497,6 +542,8 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, data = readl(&base->lane_count_set); dp->link_train.lane_count = data; + printk(BIOS_SPEW, "Done training: Link bandwidth: 0x%x, lane_count: %d\n", + dp->link_train.link_rate, data); return 0; } @@ -533,12 +580,14 @@ int dp_controller_init(struct s5p_dp_device *dp_device) /* Minimum delay after H/w Link training */ udelay(1000); + printk(BIOS_DEBUG, "call s5p_dp_enable_scramble\n"); ret = s5p_dp_enable_scramble(dp); if (ret) { printk(BIOS_DEBUG, "unable to set scramble mode\n"); return ret; } + printk(BIOS_DEBUG, "call s5p_dp_enable_rx_to_enhanced_mode\n"); ret = s5p_dp_enable_rx_to_enhanced_mode(dp); if (ret) { printk(BIOS_DEBUG, "unable to set enhanced mode\n"); @@ -553,7 +602,9 @@ int dp_controller_init(struct s5p_dp_device *dp_device) writel(dp->link_train.lane_count, &base->lane_count_set); writel(dp->link_train.link_rate, &base->link_bw_set); + printk(BIOS_DEBUG, "call s5p_dp_init_video\n"); s5p_dp_init_video(dp); + printk(BIOS_DEBUG, "call s5p_dp_config_video\n"); ret = s5p_dp_config_video(dp, dp->video_info); if (ret) { printk(BIOS_DEBUG, "unable to config video\n"); diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c index 60e1398..49fe1cb 100644 --- a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c +++ b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c @@ -102,6 +102,7 @@ unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp) u32 reg; reg = readl(&dp->base->dp_debug_ctl); + printk(BIOS_SPEW, "%s: reg is 0x%x, PLL_LOCK is 0x%x\n", __func__, reg, PLL_LOCK); if (reg & PLL_LOCK) return PLL_LOCKED; else @@ -351,11 +352,13 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp) u32 reg; struct exynos5_dp *base = dp->base; + printk(BIOS_SPEW, "%s: sys_ctl_1 is %p\n", __func__, &base->sys_ctl_1); reg = readl(&base->sys_ctl_1); writel(reg, &base->sys_ctl_1); reg = readl(&base->sys_ctl_1); + printk(BIOS_SPEW, "%s: sys_ctl_1 is %08x, DET_STA is 0x%x\n", __func__, reg, DET_STA); if (!(reg & DET_STA)) return -1; @@ -364,6 +367,7 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp) reg = readl(&base->sys_ctl_2); + printk(BIOS_SPEW, "%s: sys_ctl_2 is %08x, CHA_STA is 0x%x\n", __func__, reg, CHA_STA); if (reg & CHA_STA) { printk(BIOS_DEBUG, "Input stream clk is changing\n"); return -1; @@ -452,6 +456,7 @@ void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp, u32 reg; struct exynos5_dp *base = dp->base; + printk(BIOS_SPEW, "%s: Start\n", __func__); reg = readl(&base->func_en_1); reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N); reg |= MASTER_VID_FUNC_EN_N; @@ -474,6 +479,7 @@ void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp, reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; writel(reg, &base->soc_general_ctl); + printk(BIOS_SPEW, "%s: Done\n", __func__); } void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp) diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 09b670e..b061433 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -32,7 +32,6 @@ static void exynos_displayport_init(device_t dev) unsigned long int fb_size; u32 lcdbase; - printk(BIOS_SPEW, "%s: dev 0x%p, conf 0x%p\n", __func__, dev, conf); memset(&vi, 0, sizeof(vi)); memset(&panel, 0, sizeof(panel)); @@ -71,6 +70,7 @@ static void exynos_displayport_init(device_t dev) mmio_resource(dev, 1, lcdbase/KiB, fb_size + (KiB-1)/KiB); printk(BIOS_DEBUG, "Initializing exynos VGA, base %p\n",(void *)lcdbase); + memset((void *)lcdbase, 0x55, 0x100000); ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase); } diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index 6d3d7c8..3df0b87 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -33,6 +33,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EXYNOS_DISPLAYPORT select CHROMEOS select DRIVER_TI_TPS65090 + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_DO_NATIVE_VGA_INIT config MAINBOARD_DIR string diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index 6e46d13..e3bab8b 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -98,7 +98,9 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_developer_mode_switch(void) { - return 0; + /* This should return 0, but we hardcode it to 1 to ensure coreboot + draws the dev mode screen while we're working on this patch. */ + return 1; } int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 1cd84e8..dc7b4f5 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -23,6 +23,7 @@ #include <drivers/ti/tps65090/tps65090.h> #include <cbmem.h> #include <delay.h> +#include <boot/coreboot_tables.h> #include <arch/cache.h> #include <arch/exception.h> #include <arch/gpio.h> @@ -41,6 +42,51 @@ #define DRAM_SIZE CONFIG_DRAM_SIZE_MB #define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ +int vbe_mode_info_valid(void); +int vbe_mode_info_valid(void) +{ + return 1; +} + +void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); +void fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +{ + /* + * FIXME: The address returned points at the LCD colormap base. The + * 64KiB offset points at the LCD base. Is this what we want? + */ + framebuffer->physical_address = + (u32)cbmem_find(CBMEM_ID_CONSOLE) + 64*KiB; + printk(BIOS_SPEW, "%s: framebuffer->physical address is 0x%llx\n", + __func__, framebuffer->physical_address); +/* + register "xres" = "1366" + register "yres" = "768" + register "bpp" = "16" + # complex magic timing! + register "clkval_f" = "2" + register "upper_margin" = "14" + register "lower_margin" = "3" + register "vsync" = "5" + register "left_margin" = "80" + register "right_margin" = "48" + register "hsync" = "32" +*/ + framebuffer->x_resolution = 1366; + framebuffer->y_resolution = 768; + framebuffer->bytes_per_line = 1366*2; + framebuffer->bits_per_pixel = 16; + framebuffer->red_mask_pos = 11; + framebuffer->red_mask_size = 5; + framebuffer->green_mask_pos = 6; + framebuffer->green_mask_size = 5; + framebuffer->blue_mask_pos = 0; + framebuffer->blue_mask_size = 5; + framebuffer->reserved_mask_pos = 0; + framebuffer->reserved_mask_size = 0; +} + + void hardwaremain(int boot_complete); void main(void) { @@ -221,6 +267,9 @@ static void mainboard_init(device_t dev) } while (!exynos_dp_hotplug()); exynos_dp_bridge_setup(); + snow_backlight_vdd(); + snow_backlight_pwm(); + snow_backlight_en(); for (dp_tries = 1; dp_tries <= SNOW_MAX_DP_TRIES; dp_tries++) { exynos_dp_bridge_init(); if (exynos_dp_hotplug()) { @@ -229,7 +278,7 @@ static void mainboard_init(device_t dev) } if (dp_controller_init(&dp_device)) - continue; + break; // continue; udelay(LCD_T3_DELAY_MS * 1000);

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Patch set updated for coreboot: 8247a4e GOOGLE/SNOW: get graphics working
by David Hendricks 19 Apr '13

19 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3116 -gerrit commit 8247a4e950dd80328a95512be97d46728e7124a5 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Apr 18 18:09:24 2013 -0700 GOOGLE/SNOW: get graphics working draft patch, needs cleanup, but we've got pictures. Change-Id: I16e711c97e9d02c916824f621e2313297448732b Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5-common/exynos-fb.c | 71 +++++++++++++++++++++++++---- src/cpu/samsung/exynos5-common/s5p-dp-reg.c | 6 +++ src/cpu/samsung/exynos5250/cpu.c | 2 +- src/mainboard/google/snow/Kconfig | 2 + src/mainboard/google/snow/chromeos.c | 4 +- src/mainboard/google/snow/ramstage.c | 46 ++++++++++++++++++- 6 files changed, 118 insertions(+), 13 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index 54a2d7a..1bb97a7 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -27,6 +27,7 @@ #include <arch/io.h> #include <stdlib.h> #include <string.h> +#include <time.h> #include <console/console.h> #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/power.h> @@ -41,6 +42,24 @@ #include "cpu/samsung/exynos5250/s5p-dp.h" #include "s5p-dp-core.h" +/* useful information. Here is the rough outline of how we bring up the display. + *1. Upon power-on Sink generates a hot plug detection pulse thru HPD + *2. Source determines video mode by reading DPCD receiver capability field (DPCD 00000h to + * 0000Dh) including eDP CP capability register (DPCD 0000Dh) + *3. Sink replies DPCD receiver capability field. + *4. Source starts EDID read thru I2C-over-AUX + *5. Sink replies EDID thru I2C-over-AUX + *6. Source determines link configuration, such as MAX_LINK_RATE and + * MAX_LANE_COUNT. Source also determines which type of eDP Authentication method + * to use and writes DPCD link configuration field (DPCD 00100h to 0010Ah) including eDP + * configuration set (DPCD 0010Ah). + *7. Source starts link training. Sink does clock recovery and equalization + *8. Source reads DPCD link status field (DPCD 00200h to 0020Bh) + *9. Sink replies DPCD link status field. If main link is not stable, Source repeats Step 7. + *10. Source sends MSA (Main Stream Attribute) data. Sink extracts video parameters and + * recovers stream clock. + *11. Source sends video data + */ /* To help debug any init errors here, define a list of possible errors */ enum { ERR_PLL_NOT_UNLOCKED = 2, @@ -126,38 +145,51 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, { unsigned int val; u32 fbsize; - struct exynos5_fimd *fimd = + struct exynos5_fimd *fimd = //14400000 samsung_get_base_fimd(); - struct exynos5_disp_ctrl *disp_ctrl = + struct exynos5_disp_ctrl *disp_ctrl = //14420000 samsung_get_base_disp_ctrl(); + printk(BIOS_SPEW, "%s: fimd %p disp_ctrl %p\n", __func__, fimd, disp_ctrl); + printk(BIOS_SPEW, "pd %p\n", pd); + printk(BIOS_SPEW, "lcdbase %p\n", lcdbase); + printk(BIOS_SPEW, "pd->xres %d pd->yres %d\n", pd->xres, pd->yres); + printk(BIOS_SPEW, "Write %08x to %p\n", pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); writel(pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); val = ENVID_ON | ENVID_F_ON | (pd->clkval_f << CLKVAL_F_OFFSET); + printk(BIOS_SPEW, "Write %08x to fimd->vidcon0\n", val); writel(val, &fimd->vidcon0); val = (pd->vsync << VSYNC_PULSE_WIDTH_OFFSET) | (pd->lower_margin << V_FRONT_PORCH_OFFSET) | (pd->upper_margin << V_BACK_PORCH_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon0); writel(val, &disp_ctrl->vidtcon0); val = (pd->hsync << HSYNC_PULSE_WIDTH_OFFSET) | (pd->right_margin << H_FRONT_PORCH_OFFSET) | (pd->left_margin << H_BACK_PORCH_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon1); writel(val, &disp_ctrl->vidtcon1); val = ((pd->xres - 1) << HOZVAL_OFFSET) | ((pd->yres - 1) << LINEVAL_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon2); writel(val, &disp_ctrl->vidtcon2); + printk(BIOS_SPEW, "Write %08x to %p\n", (unsigned int)lcdbase, &fimd->vidw00add0b0); writel((unsigned int)lcdbase, &fimd->vidw00add0b0); fbsize = calc_fbsize(panel_info); + printk(BIOS_SPEW, "Write %08x to %p\n", (unsigned int)fbsize, &fimd->vidw00add1b0); writel((unsigned int)lcdbase + fbsize, &fimd->vidw00add1b0); + printk(BIOS_SPEW, "Write %08x to %p\n", (unsigned int)pd->xres*2, &fimd->vidw00add0b0); writel(pd->xres * 2, &fimd->vidw00add2); val = ((pd->xres - 1) << OSD_RIGHTBOTX_F_OFFSET); val |= ((pd->yres - 1) << OSD_RIGHTBOTY_F_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &fimd->vidosd0b); writel(val, &fimd->vidosd0b); writel(pd->xres * pd->yres, &fimd->vidosd0c); @@ -165,6 +197,7 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, val = BPPMODE_F_RGB_16BIT_565 << BPPMODE_F_OFFSET; val |= ENWIN_F_ENABLE | HALF_WORD_SWAP_EN; + printk(BIOS_SPEW, "Write %08x to %p\n", val, &fimd->wincon0); writel(val, &fimd->wincon0); /* DPCLKCON_ENABLE */ @@ -191,7 +224,7 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, struct video_info *video_info) { int timeout = 0; - u32 start; + u32 start, end; struct exynos5_dp *base = dp->base; s5p_dp_config_video_slave_mode(dp, video_info); @@ -206,16 +239,17 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, return -ERR_PLL_NOT_UNLOCKED; } - start = get_timer(0); + start = timer_us(); + end = start + STREAM_ON_TIMEOUT*1000; do { if (s5p_dp_is_slave_video_stream_clock_on(dp) == 0) { timeout++; break; } - } while (get_timer(start) <= STREAM_ON_TIMEOUT); + } while (timer_us() < end); if (!timeout) { - printk(BIOS_DEBUG, "Video Clock Not ok\n"); + printk(BIOS_DEBUG, "Video Clock Not ok after %d microseconds waiting\n", timer_us() - start); return -ERR_VIDEO_CLOCK_BAD; } @@ -255,7 +289,7 @@ static int s5p_dp_enable_rx_to_enhanced_mode(struct s5p_dp_device *dp) printk(BIOS_DEBUG, "DPCD read error\n"); return -ERR_DPCD_READ_ERROR1; } - + /* let's not do this and see if it gets better */ if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, DPCD_ENHANCED_FRAME_EN | (data & DPCD_LANE_COUNT_SET_MASK))) { @@ -408,23 +442,25 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, unsigned int max_lane, unsigned int max_rate) { + int pll_is_locked = 0; u32 data; u32 start; int lane; struct exynos5_dp *base = dp->base; + printk(BIOS_SPEW, "%s: start\n", __func__); /* Stop Video */ clrbits_le32(&base->video_ctl_1, VIDEO_EN); start = get_timer(0); - while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + while ((pll_is_locked = s5p_dp_get_pll_lock_status(dp)) == PLL_UNLOCKED) { if (get_timer(start) > PLL_LOCK_TIMEOUT) { /* Ignore this error, and try to continue */ printk(BIOS_ERR, "PLL is not locked yet.\n"); break; } } - + printk(BIOS_SPEW, "PLL is %slocked\n", pll_is_locked == PLL_LOCKED ? "": "un"); /* Reset Macro */ setbits_le32(&base->dp_phy_test, MACRO_RST); @@ -448,6 +484,9 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, s5p_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); s5p_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); + printk(BIOS_SPEW, "%s: rate 0x%x, lane_count %d\n", __func__, + dp->link_train.link_rate, dp->link_train.lane_count); + if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { printk(BIOS_DEBUG, "Rx Max Link Rate is abnormal :%x !\n", @@ -470,21 +509,27 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, dp->link_train.link_rate = max_rate; /* Set link rate and count as you want to establish*/ + printk(BIOS_SPEW, "Set link rate and count\n"); writel(dp->link_train.lane_count, &base->lane_count_set); writel(dp->link_train.link_rate, &base->link_bw_set); /* Set sink to D0 (Sink Not Ready) mode. */ + printk(BIOS_SPEW, "Set sink rate to D0\n"); s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE, DPCD_SET_POWER_STATE_D0); /* Start HW link training */ + printk(BIOS_SPEW, "Start Link hardware training\n"); writel(HW_TRAINING_EN, &base->dp_hw_link_training); - /* Wait unitl HW link training done */ + /* Wait until HW link training done */ + printk(BIOS_SPEW, "Wait until HW link training done\n"); s5p_dp_wait_hw_link_training_done(dp); + printk(BIOS_SPEW, "HW link training done\n"); /* Get hardware link training status */ data = readl(&base->dp_hw_link_training); + printk(BIOS_SPEW, "hardware link training status: 0x%08x\n", data); if (data != 0) { printk(BIOS_DEBUG, " H/W link training failure: 0x%x\n", data); return -ERR_LINK_TRAINING_FAILURE; @@ -497,6 +542,8 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, data = readl(&base->lane_count_set); dp->link_train.lane_count = data; + printk(BIOS_SPEW, "Done training: Link bandwidth: 0x%x, lane_count: %d\n", + dp->link_train.link_rate, data); return 0; } @@ -533,12 +580,14 @@ int dp_controller_init(struct s5p_dp_device *dp_device) /* Minimum delay after H/w Link training */ udelay(1000); + printk(BIOS_DEBUG, "call s5p_dp_enable_scramble\n"); ret = s5p_dp_enable_scramble(dp); if (ret) { printk(BIOS_DEBUG, "unable to set scramble mode\n"); return ret; } + printk(BIOS_DEBUG, "call s5p_dp_enable_rx_to_enhanced_mode\n"); ret = s5p_dp_enable_rx_to_enhanced_mode(dp); if (ret) { printk(BIOS_DEBUG, "unable to set enhanced mode\n"); @@ -553,7 +602,9 @@ int dp_controller_init(struct s5p_dp_device *dp_device) writel(dp->link_train.lane_count, &base->lane_count_set); writel(dp->link_train.link_rate, &base->link_bw_set); + printk(BIOS_DEBUG, "call s5p_dp_init_video\n"); s5p_dp_init_video(dp); + printk(BIOS_DEBUG, "call s5p_dp_config_video\n"); ret = s5p_dp_config_video(dp, dp->video_info); if (ret) { printk(BIOS_DEBUG, "unable to config video\n"); diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c index 60e1398..49fe1cb 100644 --- a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c +++ b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c @@ -102,6 +102,7 @@ unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp) u32 reg; reg = readl(&dp->base->dp_debug_ctl); + printk(BIOS_SPEW, "%s: reg is 0x%x, PLL_LOCK is 0x%x\n", __func__, reg, PLL_LOCK); if (reg & PLL_LOCK) return PLL_LOCKED; else @@ -351,11 +352,13 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp) u32 reg; struct exynos5_dp *base = dp->base; + printk(BIOS_SPEW, "%s: sys_ctl_1 is %p\n", __func__, &base->sys_ctl_1); reg = readl(&base->sys_ctl_1); writel(reg, &base->sys_ctl_1); reg = readl(&base->sys_ctl_1); + printk(BIOS_SPEW, "%s: sys_ctl_1 is %08x, DET_STA is 0x%x\n", __func__, reg, DET_STA); if (!(reg & DET_STA)) return -1; @@ -364,6 +367,7 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp) reg = readl(&base->sys_ctl_2); + printk(BIOS_SPEW, "%s: sys_ctl_2 is %08x, CHA_STA is 0x%x\n", __func__, reg, CHA_STA); if (reg & CHA_STA) { printk(BIOS_DEBUG, "Input stream clk is changing\n"); return -1; @@ -452,6 +456,7 @@ void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp, u32 reg; struct exynos5_dp *base = dp->base; + printk(BIOS_SPEW, "%s: Start\n", __func__); reg = readl(&base->func_en_1); reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N); reg |= MASTER_VID_FUNC_EN_N; @@ -474,6 +479,7 @@ void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp, reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; writel(reg, &base->soc_general_ctl); + printk(BIOS_SPEW, "%s: Done\n", __func__); } void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp) diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 09b670e..b061433 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -32,7 +32,6 @@ static void exynos_displayport_init(device_t dev) unsigned long int fb_size; u32 lcdbase; - printk(BIOS_SPEW, "%s: dev 0x%p, conf 0x%p\n", __func__, dev, conf); memset(&vi, 0, sizeof(vi)); memset(&panel, 0, sizeof(panel)); @@ -71,6 +70,7 @@ static void exynos_displayport_init(device_t dev) mmio_resource(dev, 1, lcdbase/KiB, fb_size + (KiB-1)/KiB); printk(BIOS_DEBUG, "Initializing exynos VGA, base %p\n",(void *)lcdbase); + memset((void *)lcdbase, 0x55, 0x100000); ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase); } diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index 6d3d7c8..3df0b87 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -33,6 +33,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EXYNOS_DISPLAYPORT select CHROMEOS select DRIVER_TI_TPS65090 + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_DO_NATIVE_VGA_INIT config MAINBOARD_DIR string diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index 6e46d13..e3bab8b 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -98,7 +98,9 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_developer_mode_switch(void) { - return 0; + /* This should return 0, but we hardcode it to 1 to ensure coreboot + draws the dev mode screen while we're working on this patch. */ + return 1; } int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 1cd84e8..bd2a595 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -23,6 +23,7 @@ #include <drivers/ti/tps65090/tps65090.h> #include <cbmem.h> #include <delay.h> +#include <boot/coreboot_tables.h> #include <arch/cache.h> #include <arch/exception.h> #include <arch/gpio.h> @@ -41,6 +42,46 @@ #define DRAM_SIZE CONFIG_DRAM_SIZE_MB #define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ +int vbe_mode_info_valid(void); +int vbe_mode_info_valid(void) +{ + return 1; +} + +void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); +void fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +{ + framebuffer->physical_address = (u32)cbmem_find(CBMEM_ID_CONSOLE); + printk(BIOS_SPEW, "%s: framebuffer->physical address is 0x%llx\n", + __func__, framebuffer->physical_address); +/* + register "xres" = "1366" + register "yres" = "768" + register "bpp" = "16" + # complex magic timing! + register "clkval_f" = "2" + register "upper_margin" = "14" + register "lower_margin" = "3" + register "vsync" = "5" + register "left_margin" = "80" + register "right_margin" = "48" + register "hsync" = "32" +*/ + framebuffer->x_resolution = 1366; + framebuffer->y_resolution = 768; + framebuffer->bytes_per_line = 1366*2; + framebuffer->bits_per_pixel = 16; + framebuffer->red_mask_pos = 11; + framebuffer->red_mask_size = 5; + framebuffer->green_mask_pos = 6; + framebuffer->green_mask_size = 5; + framebuffer->blue_mask_pos = 0; + framebuffer->blue_mask_size = 5; + framebuffer->reserved_mask_pos = 0; + framebuffer->reserved_mask_size = 0; +} + + void hardwaremain(int boot_complete); void main(void) { @@ -221,6 +262,9 @@ static void mainboard_init(device_t dev) } while (!exynos_dp_hotplug()); exynos_dp_bridge_setup(); + snow_backlight_vdd(); + snow_backlight_pwm(); + snow_backlight_en(); for (dp_tries = 1; dp_tries <= SNOW_MAX_DP_TRIES; dp_tries++) { exynos_dp_bridge_init(); if (exynos_dp_hotplug()) { @@ -229,7 +273,7 @@ static void mainboard_init(device_t dev) } if (dp_controller_init(&dp_device)) - continue; + break; // continue; udelay(LCD_T3_DELAY_MS * 1000);

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coreboot-gerrit April 2013