coreboot-gerrit April 2013

coreboot-gerrit@coreboot.org

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506 discussions

Patch set updated for coreboot: 5896f9c Google/Snow: Enable suspend/resume.
by Hung-Te Lin 25 Apr '13

25 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3102 -gerrit commit 5896f9c5e6e4bf35e6e994d7927e3ee199f25b83 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Apr 25 19:49:40 2013 +0800 Google/Snow: Enable suspend/resume. Add the suspend/resume feature into bootblock and romstage. Verified by built and boot successfully on Google/Snow, and then executed the "suspend_stress_test" in ChromiumOS succesfully. Change-Id: I65681c42eeef2736e55bb906595f42a5b1dfdf11 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/mainboard/google/snow/bootblock.c | 17 ++++++++++++----- src/mainboard/google/snow/romstage.c | 13 ++++++++++--- 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index d2e0b50..d6411b5 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -25,16 +25,23 @@ #include <console/console.h> #include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/pinmux.h> +#include "mainboard.h" void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { - /* kick off the microsecond timer. We want to do this as early - * as we can. - */ - timer_start(); + switch (board_get_wakeup_state()) { + case BOARD_WAKEUP_DIRECT: + board_wakeup(); + break; - exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); + case BOARD_IS_NOT_WAKEUP: + /* kick off the microsecond timer. + * We want to do this as early as we can. + */ + timer_start(); + break; + } #if CONFIG_EARLY_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); console_init(); diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 52391ef..11d5d61 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -170,15 +170,22 @@ void main(void) { struct mem_timings *mem; void *entry; + int is_resume = (board_get_wakeup_state() != BOARD_IS_NOT_WAKEUP); /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ mem = board_setup_clock(); - console_init(); - board_setup_power(); + if (!is_resume) { + console_init(); + board_setup_power(); + } + + board_setup_memory(mem, is_resume); - board_setup_memory(mem, 0); + if (is_resume) { + board_wakeup(); + } board_setup_storage(); board_setup_gpio();

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New patch to review for coreboot: fc1a942 google/snow: Revise romstage initialization code.
by Hung-Te Lin 25 Apr '13

25 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3130 -gerrit commit fc1a9422b341d68d96f6362c3ba19ec24415fc56 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Apr 25 19:30:19 2013 +0800 google/snow: Revise romstage initialization code. Move board setup procedure to board_setup_* functions, with better function names and comments. Verified by successfully built and boot on Google/Snow. Change-Id: I2942d75064135093eeb1c1da188a005fd255111d Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/mainboard/google/snow/romstage.c | 92 ++++++++++++++++++------------------ 1 file changed, 47 insertions(+), 45 deletions(-) diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 6e312fa..52391ef 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -46,10 +46,16 @@ #define PMIC_BUS 0 #define MMC0_GPIO_PIN (58) -static int setup_pmic(void) +static void board_setup_power(void) { int error = 0; + power_init(); + + /* Initialize I2C bus to configure PMIC. */ + i2c_init(0, CONFIG_SYS_I2C_SPEED, 0x00); + + printk(BIOS_DEBUG, "%s: Setting up pmic...\n", __func__); /* * We're using CR1616 coin cell battery that is non-rechargeable * battery. But, BBCHOSTEN bit of the BBAT Charger Register in @@ -81,19 +87,19 @@ static int setup_pmic(void) error |= max77686_enable_32khz_cp(PMIC_BUS); - if (error) - printk(BIOS_CRIT, "%s: Error during PMIC setup\n", __func__); - - return error; + if (error) { + printk(BIOS_CRIT, "%s: PMIC error: %#x\n", __func__, error); + die("Failed to intialize PMIC.\n"); + } } -static void initialize_s5p_mshc(void) +static void board_setup_storage(void) { /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ if (clock_set_mshci(PERIPH_ID_SDMMC0)) - printk(BIOS_CRIT, "Failed to set clock for SDMMC0.\n"); + print_crit("Failed to set clock for SDMMC0.\n"); if (gpio_direction_output(MMC0_GPIO_PIN, 1)) { - printk(BIOS_CRIT, "Unable to power on SDMMC0.\n"); + print_crit("Unable to power on SDMMC0.\n"); } gpio_set_pull(MMC0_GPIO_PIN, EXYNOS_GPIO_PULL_NONE); gpio_set_drv(MMC0_GPIO_PIN, EXYNOS_GPIO_DRV_4X); @@ -104,12 +110,12 @@ static void initialize_s5p_mshc(void) exynos_pinmux_config(PERIPH_ID_SDMMC2, 0); } -static void graphics(void) +static void board_setup_graphics(void) { exynos_pinmux_config(PERIPH_ID_DPHPD, 0); } -static void chromeos_gpios(void) +static void board_setup_gpio(void) { struct exynos5_gpio_part1 *gpio_pt1; struct exynos5_gpio_part2 *gpio_pt2; @@ -137,53 +143,49 @@ static void chromeos_gpios(void) s5p_gpio_set_pull(&gpio_pt2->x1, POWER_GPIO, EXYNOS_GPIO_PULL_NONE); } +static void board_setup_memory(struct mem_timings *mem, int is_resume) +{ + printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n", + mem->mem_manuf, + mem->mem_type, + mem->mpll_mdiv, + mem->frequency_mhz); + if (ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, !is_resume)) { + die("Failed to initialize memory controller.\n"); + } +} + +static struct mem_timings *board_setup_clock(void) +{ + struct mem_timings *mem = get_mem_timings(); + struct arm_clk_ratios *arm_ratios = get_arm_clk_ratios(); + if (!mem) { + die("Unable to auto-detect memory timings\n"); + } + system_clock_init(mem, arm_ratios); + return mem; +} + void main(void) { struct mem_timings *mem; - struct arm_clk_ratios *arm_ratios; - int ret; void *entry; - clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ - /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ - mem = get_mem_timings(); - arm_ratios = get_arm_clk_ratios(); - system_clock_init(mem, arm_ratios); + mem = board_setup_clock(); console_init(); + board_setup_power(); - i2c_init(0, CONFIG_SYS_I2C_SPEED, 0x00); - if (power_init()) - power_shutdown(); - printk(BIOS_DEBUG, "%s: setting up pmic...\n", __func__); - if (setup_pmic()) - power_shutdown(); - - if (!mem) { - printk(BIOS_CRIT, "Unable to auto-detect memory timings\n"); - while(1); - } - printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n", - mem->mem_manuf, - mem->mem_type, - mem->mpll_mdiv, - mem->frequency_mhz); - - ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, 1); - if (ret) { - printk(BIOS_ERR, "Memory controller init failed, err: %x\n", - ret); - while(1); - } - - initialize_s5p_mshc(); - - chromeos_gpios(); + board_setup_memory(mem, 0); - graphics(); + board_setup_storage(); + board_setup_gpio(); + board_setup_graphics(); + /* Set SPI (primary CBFS media) clock to 50MHz. */ + clock_set_rate(PERIPH_ID_SPI1, 50000000); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);

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New patch to review for coreboot: badb325 google/snow: Add "wakup" module for suspend/resume.
by Hung-Te Lin 25 Apr '13

25 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3129 -gerrit commit badb325241ac84b6711fb82565191378658efffc Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Apr 25 17:38:55 2013 +0800 google/snow: Add "wakup" module for suspend/resume. The "wakeup" procedure will be shared by bootblock and romstage for different types of resume process. Note, this commit does not include changes in romstage/bootblock to enable suspend/resume feature. Simply adding functions to handle suspend/resume. Verified by successfully built and boot Google/Snow firmware image. Change-Id: I17a256afb99f2f8b5e0eac3393cdf6959b239341 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/cpu/samsung/exynos5250/Makefile.inc | 2 +- src/mainboard/google/snow/Makefile.inc | 3 ++ src/mainboard/google/snow/mainboard.h | 9 +++++ src/mainboard/google/snow/romstage.c | 13 ------- src/mainboard/google/snow/wakeup.c | 60 +++++++++++++++++++++++++++++++++ 5 files changed, 73 insertions(+), 14 deletions(-) diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 8788a6c..25d1bc5 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -3,7 +3,7 @@ # image outside of CBFS #INTERMEDIATE += exynos5250_add_bl1 -bootblock-y += pinmux.c mct.c +bootblock-y += pinmux.c mct.c power.c # Clock is required for UART bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc index 46e366f..84a8c05 100644 --- a/src/mainboard/google/snow/Makefile.inc +++ b/src/mainboard/google/snow/Makefile.inc @@ -17,9 +17,12 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +bootblock-y += wakeup.c + romstage-y += mainboard.c romstage-y += memory.c romstage-y += romstage.c +romstage-y += wakeup.c # ramstage-y += ec.c ramstage-y += ramstage.c diff --git a/src/mainboard/google/snow/mainboard.h b/src/mainboard/google/snow/mainboard.h index 6fe371f..9650bea 100644 --- a/src/mainboard/google/snow/mainboard.h +++ b/src/mainboard/google/snow/mainboard.h @@ -35,4 +35,13 @@ enum snow_board_config { int board_get_config(void); +enum { + BOARD_IS_NOT_WAKEUP, + BOARD_WAKEUP_DIRECT, + BOARD_WAKEUP_NEED_CLOCK_RESET, +}; + +int board_get_wakeup_state(void); +void board_wakeup(void); + #endif /* MAINBOARD_H */ diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index edbe009..6e312fa 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -46,19 +46,6 @@ #define PMIC_BUS 0 #define MMC0_GPIO_PIN (58) -#if 0 -static int board_wakeup_permitted(void) -{ - const int gpio = GPIO_Y10; - int is_bad_wake; - - /* We're a bad wakeup if the gpio was defined and was high */ - is_bad_wake = ((gpio != -1) && gpio_get_value(gpio)); - - return !is_bad_wake; -} -#endif - static int setup_pmic(void) { int error = 0; diff --git a/src/mainboard/google/snow/wakeup.c b/src/mainboard/google/snow/wakeup.c new file mode 100644 index 0000000..49867af --- /dev/null +++ b/src/mainboard/google/snow/wakeup.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/gpio.h> +#include <arch/hlt.h> +#include <cpu/samsung/exynos5250/gpio.h> +#include <cpu/samsung/exynos5250/power.h> +#include <cpu/samsung/exynos5-common/exynos5-common.h> + +#include "mainboard.h" + +static int wakeup_need_reset(void) +{ + /* We're a bad wakeup if the gpio is high */ + return gpio_get_value(GPIO_Y10); +} + +void board_wakeup(void) +{ + if (wakeup_need_reset()) + power_reset(); + + power_init(); /* Ensure ps_hold_setup() for early wakeup. */ + power_exit_wakeup(); + /* Should never return. */ + hlt(); +} + +int board_get_wakeup_state() +{ + uint32_t status = power_read_reset_status(); + + /* DIDLE/LPA can be resumed without clock reset (ex, bootblock), + * and SLEEP requires resetting clock (should be done in ROM stage). + */ + + if (status == S5P_CHECK_DIDLE || status == S5P_CHECK_LPA) + return BOARD_WAKEUP_DIRECT; + + if (status == S5P_CHECK_SLEEP) + return BOARD_WAKEUP_NEED_CLOCK_RESET; + + return BOARD_IS_NOT_WAKEUP; +}

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New patch to review for coreboot: 3bb4361 arm/exynos: Allow DRAM controller to be initialized without clearing RAM content.
by Hung-Te Lin 25 Apr '13

25 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3128 -gerrit commit 3bb4361674863c3343b59db56f8793468b269da3 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Apr 25 16:14:19 2013 +0800 arm/exynos: Allow DRAM controller to be initialized without clearing RAM content. To support suspend/resume, PHY control must be reseted only on normal boot path. This commit adds a new param "mem_reset" to specify that. Verified to boot successfully on Google/Snow. Change-Id: Id49bc6c6239cf71a67ba091092dd3ebf18e83e33 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/cpu/samsung/exynos5250/dmc_init_ddr3.c | 14 ++++++++++---- src/cpu/samsung/exynos5250/setup.h | 4 +++- src/mainboard/google/snow/romstage.c | 2 +- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c index 5bb8a37..132471d 100644 --- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c @@ -61,7 +61,8 @@ static void reset_phy_ctrl(void) udelay(500); } -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) +int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, + int mem_reset) { unsigned int val; struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl; @@ -71,9 +72,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE; phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE; dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE; - printk(BIOS_SPEW, "ddr3_mem_ctrl_init: reset phy: "); - reset_phy_ctrl(); - printk(BIOS_SPEW, "done\n"); + + if (mem_reset) { + printk(BIOS_SPEW, "%s: reset phy: ", __func__); + reset_phy_ctrl(); + printk(BIOS_SPEW, "done\n"); + } else { + printk(BIOS_SPEW, "%s: skip mem_reset.\n", __func__); + } /* Set Impedance Output Driver */ printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Set Impedance Output Driver\n"); diff --git a/src/cpu/samsung/exynos5250/setup.h b/src/cpu/samsung/exynos5250/setup.h index 4f7f58c..952c125 100644 --- a/src/cpu/samsung/exynos5250/setup.h +++ b/src/cpu/samsung/exynos5250/setup.h @@ -702,9 +702,11 @@ void mem_ctrl_init(void); * which the DMC uses to decide how to split a memory * chunk into smaller chunks to support concurrent * accesses; may vary across boards. + * @param mem_reset Reset memory when initialization. * @return 0 if ok, SETUP_ERR_... if there is a problem */ -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size); +int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, + int mem_reset); void tzpc_init(void); /* diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 41b88e1..edbe009 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -184,7 +184,7 @@ void main(void) mem->mpll_mdiv, mem->frequency_mhz); - ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE); + ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, 1); if (ret) { printk(BIOS_ERR, "Memory controller init failed, err: %x\n", ret);

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Patch set updated for coreboot: bbf726f AMD Hudson A55E: Remove GEC Options from Build
by Bruce Griffith 24 Apr '13

24 Apr '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3127 -gerrit commit bbf726fe6694de6b78bcf685ae3091a9a8f6e120 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Tue Apr 23 14:31:55 2013 -0600 AMD Hudson A55E: Remove GEC Options from Build Remove the GEC kconfig option from AMD Hudson builds. The GEC blobs are proprietary to AMD and there is no plan to release these into open-source. The "gigabit ethernet controller" (GEC) block was added to AMD Hudson A55E to integrate ethernet capabilities into an AMD southbridge. The GEC block requires an opaque firmware blob to function and only works with B50610 and B50610M gigabit PHY chips from Broadcom. Change-Id: I7a7bf4d41e453390ecf987c9c45ef2434fc1f1a3 Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/mainboard/amd/parmer/BiosCallOuts.c | 2 +- src/mainboard/amd/parmer/agesawrapper.c | 1 - src/mainboard/amd/thatcher/BiosCallOuts.c | 2 +- src/mainboard/amd/thatcher/agesawrapper.c | 1 - src/southbridge/amd/agesa/hudson/Kconfig | 15 ++------------- src/southbridge/amd/agesa/hudson/Makefile.inc | 25 +++---------------------- 6 files changed, 7 insertions(+), 39 deletions(-) diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index 924ea19..c77d78d 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -269,7 +269,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) * Fch Oem setting callback * * Configure platform specific Hudson device, - * such Azalia, SATA, GEC, IMC etc. + * such Azalia, SATA, IMC etc. */ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) { diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index aecd1ea..a81a997 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -557,7 +557,6 @@ STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams) FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; - FchParams->Gec.GecShadowRomBase = UserOptions.FchBldCfg->CfgGecShadowRomBase; FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index e0af994..9a3f61c 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -269,7 +269,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) * Fch Oem setting callback * * Configure platform specific Hudson device, - * such Azalia, SATA, GEC, IMC etc. + * such Azalia, SATA, IMC etc. */ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) { diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index df45148..f7577fd 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -559,7 +559,6 @@ STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams) FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; - FchParams->Gec.GecShadowRomBase = UserOptions.FchBldCfg->CfgGecShadowRomBase; FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 52692f9..b9038dd 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -55,12 +55,6 @@ config HUDSON_IMC_FWM help Add Hudson 2/3/4 IMC Firmware to support the onboard fan control -config HUDSON_GEC_FWM - bool "Add gec firmware" - default n - help - Add Hudson 2/3/4 GEC Firmware - config HUDSON_XHCI_FWM_FILE string "XHCI firmware path and filename" default "3rdparty/southbridge/amd/hudson/xhci.bin" @@ -71,15 +65,10 @@ config HUDSON_IMC_FWM_FILE default "3rdparty/southbridge/amd/hudson/imc.bin" depends on HUDSON_IMC_FWM -config HUDSON_GEC_FWM_FILE - string "GEC firmware path and filename" - default "3rdparty/southbridge/amd/hudson/gec.bin" - depends on HUDSON_GEC_FWM - config HUDSON_FWM bool - default y if HUDSON_XHCI_FWM || HUDSON_IMC_FWM || HUDSON_GEC_FWM - default n if !HUDSON_XHCI_FWM && !HUDSON_IMC_FWM && !HUDSON_GEC_FWM + default y if HUDSON_XHCI_FWM || HUDSON_IMC_FWM + default n if !HUDSON_XHCI_FWM && !HUDSON_IMC_FWM if HUDSON_FWM diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index da029a0..9d06a24 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -17,7 +17,7 @@ ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c # ROMSIG At ROMBASE + 0x20000: # +-----------+---------------+----------------+------------+ -# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# |0x55AA55AA |EC ROM Address |Rsvd 0x00000000 |USB3 ROM | # +-----------+---------------+----------------+------------+ # EC ROM should be 64K aligned. HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) @@ -33,19 +33,9 @@ HUDSON_XHCI_POSITION=0 XHCI_FWM_SIZE=0 endif -ifeq ($(CONFIG_HUDSON_GEC_FWM), y) -HUDSON_GEC_POSITION=$(shell echo $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) 128 \ - $(XHCI_FWM_SIZE) 128 \ - | awk '{printf("%.0f", $$1 + $$2 + $$3 + $$4 + $$5)}') -GEC_FWM_SIZE=$(word 5,$(shell ls -l $(CONFIG_HUDSON_GEC_FWM_FILE))) -else -HUDSON_GEC_POSITION=0 -GEC_FWM_SIZE=0 -endif - ifeq ($(CONFIG_HUDSON_IMC_FWM), y) HUDSON_IMC_POSITION_UNALIGN=$(shell echo $(HUDSON_FWM_POSITION) \ - $(ROMSIG_SIZE) 128 $(XHCI_FWM_SIZE) 128 $(GEC_FWM_SIZE) 128 65535 \ + $(ROMSIG_SIZE) 128 $(XHCI_FWM_SIZE) 128 0x00000000 128 65535 \ | awk '{printf("%.0f", $$1 + $$2 + $$3 + $$4 + $$5 + $$6 + $$7 + $$8)}') HUDSON_IMC_POSITION=$(shell echo $(HUDSON_IMC_POSITION_UNALIGN) \ | awk '{printf("%.0f", $$1 - $$1 % 65536)}') @@ -55,12 +45,11 @@ endif $(obj)/coreboot_hudson_romsig.bin: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ $(obj)/config.h echo " Hudson FW $@" for fwm in 1437226410 \ $(HUDSON_IMC_POSITION) \ - $(HUDSON_GEC_POSITION) \ + 0x00000000 \ $(HUDSON_XHCI_POSITION) ; do \ echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ done > $@ @@ -88,14 +77,6 @@ hudson/imc-type := raw hudson/imc-required := Hudson IMC Firmware (available in coreboot/3rdparty if enabled) endif -ifeq ($(CONFIG_HUDSON_GEC_FWM), y) -cbfs-files-y += hudson/gec -hudson/gec-file := $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) -hudson/gec-position := $(HUDSON_GEC_POSITION) -hudson/gec-type := raw -hudson/gec-required := Hudson Gigabit Ethernet Controller Firmware (Contact your AMD representative) -endif - #ifeq ($(CONFIG_HUDSON_SATA_AHCI), y) ifdef CONFIG_HUDSON_AHCI_ROM stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID))

1 0

New patch to review for coreboot: 16742d5 AMD Hudson A55E: Remove GEC Options from Build
by Bruce Griffith 24 Apr '13

24 Apr '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3127 -gerrit commit 16742d5a98dac5aa19d82d8cc4bc4b700e72abcb Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Tue Apr 23 14:31:55 2013 -0600 AMD Hudson A55E: Remove GEC Options from Build Remove the GEC kconfig option from AMD Hudson builds. The GEC blobs are proprietary to AMD and there is no plan to release these into open-source. The "gigabit ethernet controller" (GEC) block was added to AMD Hudson A55E to integrate ethernet capabilities into an AMD southbridge. The GEC block requires an opaque firmware blob to function and only works with B50610 and B50610M gigabit PHY chips from Broadcom. Change-Id: I7a7bf4d41e453390ecf987c9c45ef2434fc1f1a3 Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/mainboard/amd/parmer/BiosCallOuts.c | 2 +- src/mainboard/amd/parmer/agesawrapper.c | 1 - src/mainboard/amd/thatcher/BiosCallOuts.c | 2 +- src/mainboard/amd/thatcher/agesawrapper.c | 1 - src/southbridge/amd/agesa/hudson/Kconfig | 11 ----------- src/southbridge/amd/agesa/hudson/Makefile.inc | 25 +++---------------------- 6 files changed, 5 insertions(+), 37 deletions(-) diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index 924ea19..c77d78d 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -269,7 +269,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) * Fch Oem setting callback * * Configure platform specific Hudson device, - * such Azalia, SATA, GEC, IMC etc. + * such Azalia, SATA, IMC etc. */ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) { diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index aecd1ea..a81a997 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -557,7 +557,6 @@ STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams) FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; - FchParams->Gec.GecShadowRomBase = UserOptions.FchBldCfg->CfgGecShadowRomBase; FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index e0af994..9a3f61c 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -269,7 +269,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) * Fch Oem setting callback * * Configure platform specific Hudson device, - * such Azalia, SATA, GEC, IMC etc. + * such Azalia, SATA, IMC etc. */ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) { diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index df45148..f7577fd 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -559,7 +559,6 @@ STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams) FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; - FchParams->Gec.GecShadowRomBase = UserOptions.FchBldCfg->CfgGecShadowRomBase; FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 52692f9..0234a7b 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -55,12 +55,6 @@ config HUDSON_IMC_FWM help Add Hudson 2/3/4 IMC Firmware to support the onboard fan control -config HUDSON_GEC_FWM - bool "Add gec firmware" - default n - help - Add Hudson 2/3/4 GEC Firmware - config HUDSON_XHCI_FWM_FILE string "XHCI firmware path and filename" default "3rdparty/southbridge/amd/hudson/xhci.bin" @@ -71,11 +65,6 @@ config HUDSON_IMC_FWM_FILE default "3rdparty/southbridge/amd/hudson/imc.bin" depends on HUDSON_IMC_FWM -config HUDSON_GEC_FWM_FILE - string "GEC firmware path and filename" - default "3rdparty/southbridge/amd/hudson/gec.bin" - depends on HUDSON_GEC_FWM - config HUDSON_FWM bool default y if HUDSON_XHCI_FWM || HUDSON_IMC_FWM || HUDSON_GEC_FWM diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index da029a0..9d06a24 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -17,7 +17,7 @@ ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c # ROMSIG At ROMBASE + 0x20000: # +-----------+---------------+----------------+------------+ -# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# |0x55AA55AA |EC ROM Address |Rsvd 0x00000000 |USB3 ROM | # +-----------+---------------+----------------+------------+ # EC ROM should be 64K aligned. HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) @@ -33,19 +33,9 @@ HUDSON_XHCI_POSITION=0 XHCI_FWM_SIZE=0 endif -ifeq ($(CONFIG_HUDSON_GEC_FWM), y) -HUDSON_GEC_POSITION=$(shell echo $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) 128 \ - $(XHCI_FWM_SIZE) 128 \ - | awk '{printf("%.0f", $$1 + $$2 + $$3 + $$4 + $$5)}') -GEC_FWM_SIZE=$(word 5,$(shell ls -l $(CONFIG_HUDSON_GEC_FWM_FILE))) -else -HUDSON_GEC_POSITION=0 -GEC_FWM_SIZE=0 -endif - ifeq ($(CONFIG_HUDSON_IMC_FWM), y) HUDSON_IMC_POSITION_UNALIGN=$(shell echo $(HUDSON_FWM_POSITION) \ - $(ROMSIG_SIZE) 128 $(XHCI_FWM_SIZE) 128 $(GEC_FWM_SIZE) 128 65535 \ + $(ROMSIG_SIZE) 128 $(XHCI_FWM_SIZE) 128 0x00000000 128 65535 \ | awk '{printf("%.0f", $$1 + $$2 + $$3 + $$4 + $$5 + $$6 + $$7 + $$8)}') HUDSON_IMC_POSITION=$(shell echo $(HUDSON_IMC_POSITION_UNALIGN) \ | awk '{printf("%.0f", $$1 - $$1 % 65536)}') @@ -55,12 +45,11 @@ endif $(obj)/coreboot_hudson_romsig.bin: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ $(obj)/config.h echo " Hudson FW $@" for fwm in 1437226410 \ $(HUDSON_IMC_POSITION) \ - $(HUDSON_GEC_POSITION) \ + 0x00000000 \ $(HUDSON_XHCI_POSITION) ; do \ echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ done > $@ @@ -88,14 +77,6 @@ hudson/imc-type := raw hudson/imc-required := Hudson IMC Firmware (available in coreboot/3rdparty if enabled) endif -ifeq ($(CONFIG_HUDSON_GEC_FWM), y) -cbfs-files-y += hudson/gec -hudson/gec-file := $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) -hudson/gec-position := $(HUDSON_GEC_POSITION) -hudson/gec-type := raw -hudson/gec-required := Hudson Gigabit Ethernet Controller Firmware (Contact your AMD representative) -endif - #ifeq ($(CONFIG_HUDSON_SATA_AHCI), y) ifdef CONFIG_HUDSON_AHCI_ROM stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID))

1 0

New patch to review for coreboot: 3412fd1 AMD F15: Fix warning in Proc/CPU/Feature
by Martin Roth 23 Apr '13

23 Apr '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3126 -gerrit commit 3412fd185fb0e2a1b0d9d05b30ac811534cc9db5 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Tue Apr 23 15:11:52 2013 -0600 AMD F15: Fix warning in Proc/CPU/Feature Fix Warning: cpuFeatureLeveling.c:265, GNU Compiler 4 (gcc), Priority: Normal cast to pointer from integer of different size [-Wint-to-pointer-cast] with an intermediate cast to (intptr_t) Change-Id: I3bfd2ea1e797632316675338789dabef8f73ba64 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatureLeveling.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatureLeveling.c index 1f2e708..294a18d 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatureLeveling.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatureLeveling.c @@ -262,5 +262,5 @@ GetGlobalCpuFeatureListAddress ( AddressValue = GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR; - *Address = (UINT64 *)(AddressValue); + *Address = (UINT64 *) (intptr_t) (AddressValue); }

1 0

New patch to review for coreboot: 5736000 AMD F15: Fix warnings in Proc/Common
by Martin Roth 23 Apr '13

23 Apr '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3125 -gerrit commit 5736000112c3593817157f76bcc7391db63728ba Author: Martin Roth <martin.roth(a)se-eng.com> Date: Tue Apr 23 15:02:51 2013 -0600 AMD F15: Fix warnings in Proc/Common This fixes 3 warnings in the Proc/Common directory: AmdS3Save.c:250, GNU Compiler 4 (gcc), Priority: Normal AmdS3LateRestore.c:123, GNU Compiler 4 (gcc), Priority: Normal cast from pointer to integer of different size [-Wpointer-to-int-cast] Fixed with a second cast to (intptr_t) AmdInitReset.c:153, GNU Compiler 4 (gcc), Priority: Normal statement with no effect [-Wunused-value] Fixed by commenting the line out as it is in the other families code. Change-Id: Ib35ec466671712af01568b7c2a18ee138fe883c0 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c | 2 +- src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3LateRestore.c | 2 +- src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3Save.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c index d96d21e..7a2d1a1 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c @@ -150,7 +150,7 @@ AmdInitReset ( AgesaStatus = CalledAgesaStatus; } - IDS_EXTENDED_HOOK (IDS_INIT_RESET_BEFORE, NULL, NULL, &ResetParams->StdHeader); + // IDS_EXTENDED_HOOK (IDS_INIT_RESET_BEFORE, NULL, NULL, &ResetParams->StdHeader); // Init Debug Print function IDS_HDT_CONSOLE_INIT (&ResetParams->StdHeader); diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3LateRestore.c index 22f6803..e293d46 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3LateRestore.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3LateRestore.c @@ -120,7 +120,7 @@ AmdS3LateRestore ( ASSERT (S3LateParams != NULL); BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage; - S3LateParams->StdHeader.HeapBasePtr = (UINT64) &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset]; + S3LateParams->StdHeader.HeapBasePtr = (UINT64) (intptr_t) &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset]; ASSERT (S3LateParams->StdHeader.HeapBasePtr != 0); IDS_HDT_CONSOLE_INIT (&S3LateParams->StdHeader); diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3Save.c index 6cff161..59059a3 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3Save.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3Save.c @@ -247,7 +247,7 @@ AmdS3Save ( HeapStatus = AmdS3SaveParams->StdHeader.HeapStatus; AmdS3SaveParams->StdHeader.HeapStatus = HEAP_S3_RESUME; - AmdS3SaveParams->StdHeader.HeapBasePtr = (UINT64) HeapPtr; + AmdS3SaveParams->StdHeader.HeapBasePtr = (UINT64) (intptr_t) HeapPtr; for (i = 0; i < S3LATE_TABLE_SIZE; i++) { if (HeapPtrs[i] != NULL) {

1 0

Patch set updated for coreboot: 5bbd5fc x86: use proper types for interrupt callbacks
by Aaron Durbin 23 Apr '13

23 Apr '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3124 -gerrit commit 5bbd5fc68a3eb85b89fd69d22d3e9fdf211fcdf3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 23 10:25:34 2013 -0500 x86: use proper types for interrupt callbacks The mainboard_interrupt_handlers() argument for the function pointer was using void * as the type. This does not allow the compiler to catch type differences for the arguments. Thus, some code has been committed which violates the new interrupt callbacks not taking any arguments. Make sure the compiler provides a type checking benefit. Change-Id: I268ec8e16929080955751ef518d65b91895e4308 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/include/arch/interrupt.h | 4 ++-- src/device/oprom/realmode/x86.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/include/arch/interrupt.h b/src/arch/x86/include/arch/interrupt.h index 8c9b4a9..9753c50 100644 --- a/src/arch/x86/include/arch/interrupt.h +++ b/src/arch/x86/include/arch/interrupt.h @@ -23,9 +23,9 @@ /* setup interrupt handlers for mainboard */ #if CONFIG_PCI_OPTION_ROM_RUN_REALMODE -extern void mainboard_interrupt_handlers(int intXX, void *intXX_func); +extern void mainboard_interrupt_handlers(int intXX, int (*intXX_func)(void)); #elif CONFIG_PCI_OPTION_ROM_RUN_YABEL #include <device/oprom/yabel/biosemu.h> #else -static inline void mainboard_interrupt_handlers(int intXX, void *intXX_func) { } +static inline void mainboard_interrupt_handlers(int intXX, int (*intXX_func)(void)) { } #endif diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 94b65e1..69017f4 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -118,7 +118,7 @@ static int intXX_unknown_handler(void) } /* setup interrupt handlers for mainboard */ -void mainboard_interrupt_handlers(int intXX, void *intXX_func) +void mainboard_interrupt_handlers(int intXX, int (*intXX_func)(void)) { intXX_handler[intXX] = intXX_func; }

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Patch set updated for coreboot: 9f6e038 x86: use proper types for interrupt callbacks
by Aaron Durbin 23 Apr '13

23 Apr '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3124 -gerrit commit 9f6e038cc7618dc03eb806a1aa0729e1dbd479f8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 23 10:25:34 2013 -0500 x86: use proper types for interrupt callbacks The mainboard_interrupt_handlers() argument for the function pointer was using void * as the type. This does not allow the compiler to catch type differences for the arguments. Thus, some code has been committed which violates the new interrupt callbacks not taking any arguments. Make sure the compiler provides a type checking benefit. Change-Id: I268ec8e16929080955751ef518d65b91895e4308 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/include/arch/interrupt.h | 4 ++-- src/device/oprom/realmode/x86.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/include/arch/interrupt.h b/src/arch/x86/include/arch/interrupt.h index 8c9b4a9..afe5617 100644 --- a/src/arch/x86/include/arch/interrupt.h +++ b/src/arch/x86/include/arch/interrupt.h @@ -23,9 +23,9 @@ /* setup interrupt handlers for mainboard */ #if CONFIG_PCI_OPTION_ROM_RUN_REALMODE -extern void mainboard_interrupt_handlers(int intXX, void *intXX_func); +extern void mainboard_interrupt_handlers(int intXX, void (*intXX_func)(void)); #elif CONFIG_PCI_OPTION_ROM_RUN_YABEL #include <device/oprom/yabel/biosemu.h> #else -static inline void mainboard_interrupt_handlers(int intXX, void *intXX_func) { } +static inline void mainboard_interrupt_handlers(int intXX, void (*intXX_func)(void)) { } #endif diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 94b65e1..0b45f46 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -118,7 +118,7 @@ static int intXX_unknown_handler(void) } /* setup interrupt handlers for mainboard */ -void mainboard_interrupt_handlers(int intXX, void *intXX_func) +void mainboard_interrupt_handlers(int intXX, void (*intXX_func)(void)) { intXX_handler[intXX] = intXX_func; }

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coreboot-gerrit April 2013