coreboot-gerrit April 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 7ebf2ab google/snow: Revise romstage initialization code.
by Hung-Te Lin 26 Apr '13

26 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3130 -gerrit commit 7ebf2ab0977db335817f0a344e43985ce5499a6b Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Apr 25 19:30:19 2013 +0800 google/snow: Revise romstage initialization code. Move board setup procedure to snow_setup_* functions, ans Snow board-specific (wakeup) code to snow_* for better function names and comments. Verified by successfully building and booting on Google/Snow. Change-Id: I2942d75064135093eeb1c1da188a005fd255111d Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/mainboard/google/snow/mainboard.h | 10 ++-- src/mainboard/google/snow/romstage.c | 92 ++++++++++++++++++----------------- src/mainboard/google/snow/wakeup.c | 14 +++--- 3 files changed, 59 insertions(+), 57 deletions(-) diff --git a/src/mainboard/google/snow/mainboard.h b/src/mainboard/google/snow/mainboard.h index 63a2c18..5060b72 100644 --- a/src/mainboard/google/snow/mainboard.h +++ b/src/mainboard/google/snow/mainboard.h @@ -36,14 +36,14 @@ enum snow_board_config { int board_get_config(void); enum { - BOARD_IS_NOT_WAKEUP, // A normal boot (not suspend/resume). - BOARD_WAKEUP_DIRECT, // A wake up event that can be resumed any time. - BOARD_WAKEUP_NEED_CLOCK_RESET, // A wake up event that must be resumed + SNOW_IS_NOT_WAKEUP, // A normal boot (not suspend/resume). + SNOW_WAKEUP_DIRECT, // A wake up event that can be resumed any time. + SNOW_WAKEUP_NEED_CLOCK_RESET, // A wake up event that must be resumed // only after clock and memory // controllers are re-initialized. }; -int board_get_wakeup_state(void); -void board_wakeup(void); +int snow_get_wakeup_state(void); +void snow_wakeup(void); #endif /* MAINBOARD_H */ diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 6e312fa..fd5cfce 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -46,10 +46,16 @@ #define PMIC_BUS 0 #define MMC0_GPIO_PIN (58) -static int setup_pmic(void) +static void snow_setup_power(void) { int error = 0; + power_init(); + + /* Initialize I2C bus to configure PMIC. */ + i2c_init(0, CONFIG_SYS_I2C_SPEED, 0x00); + + printk(BIOS_DEBUG, "%s: Setting up PMIC...\n", __func__); /* * We're using CR1616 coin cell battery that is non-rechargeable * battery. But, BBCHOSTEN bit of the BBAT Charger Register in @@ -81,19 +87,19 @@ static int setup_pmic(void) error |= max77686_enable_32khz_cp(PMIC_BUS); - if (error) - printk(BIOS_CRIT, "%s: Error during PMIC setup\n", __func__); - - return error; + if (error) { + printk(BIOS_CRIT, "%s: PMIC error: %#x\n", __func__, error); + die("Failed to intialize PMIC.\n"); + } } -static void initialize_s5p_mshc(void) +static void snow_setup_storage(void) { /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ if (clock_set_mshci(PERIPH_ID_SDMMC0)) - printk(BIOS_CRIT, "Failed to set clock for SDMMC0.\n"); + printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__); if (gpio_direction_output(MMC0_GPIO_PIN, 1)) { - printk(BIOS_CRIT, "Unable to power on SDMMC0.\n"); + printk(BIOS_CRIT, "%s: Unable to power on MMC0.\n", __func__); } gpio_set_pull(MMC0_GPIO_PIN, EXYNOS_GPIO_PULL_NONE); gpio_set_drv(MMC0_GPIO_PIN, EXYNOS_GPIO_DRV_4X); @@ -104,12 +110,12 @@ static void initialize_s5p_mshc(void) exynos_pinmux_config(PERIPH_ID_SDMMC2, 0); } -static void graphics(void) +static void snow_setup_graphics(void) { exynos_pinmux_config(PERIPH_ID_DPHPD, 0); } -static void chromeos_gpios(void) +static void snow_setup_gpio(void) { struct exynos5_gpio_part1 *gpio_pt1; struct exynos5_gpio_part2 *gpio_pt2; @@ -137,53 +143,49 @@ static void chromeos_gpios(void) s5p_gpio_set_pull(&gpio_pt2->x1, POWER_GPIO, EXYNOS_GPIO_PULL_NONE); } +static void snow_setup_memory(struct mem_timings *mem, int is_resume) +{ + printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n", + mem->mem_manuf, + mem->mem_type, + mem->mpll_mdiv, + mem->frequency_mhz); + if (ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, !is_resume)) { + die("Failed to initialize memory controller.\n"); + } +} + +static struct mem_timings *snow_setup_clock(void) +{ + struct mem_timings *mem = get_mem_timings(); + struct arm_clk_ratios *arm_ratios = get_arm_clk_ratios(); + if (!mem) { + die("Unable to auto-detect memory timings\n"); + } + system_clock_init(mem, arm_ratios); + return mem; +} + void main(void) { struct mem_timings *mem; - struct arm_clk_ratios *arm_ratios; - int ret; void *entry; - clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ - /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ - mem = get_mem_timings(); - arm_ratios = get_arm_clk_ratios(); - system_clock_init(mem, arm_ratios); + mem = snow_setup_clock(); console_init(); + snow_setup_power(); - i2c_init(0, CONFIG_SYS_I2C_SPEED, 0x00); - if (power_init()) - power_shutdown(); - printk(BIOS_DEBUG, "%s: setting up pmic...\n", __func__); - if (setup_pmic()) - power_shutdown(); - - if (!mem) { - printk(BIOS_CRIT, "Unable to auto-detect memory timings\n"); - while(1); - } - printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n", - mem->mem_manuf, - mem->mem_type, - mem->mpll_mdiv, - mem->frequency_mhz); - - ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, 1); - if (ret) { - printk(BIOS_ERR, "Memory controller init failed, err: %x\n", - ret); - while(1); - } - - initialize_s5p_mshc(); - - chromeos_gpios(); + snow_setup_memory(mem, 0); - graphics(); + snow_setup_storage(); + snow_setup_gpio(); + snow_setup_graphics(); + /* Set SPI (primary CBFS media) clock to 50MHz. */ + clock_set_rate(PERIPH_ID_SPI1, 50000000); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry); diff --git a/src/mainboard/google/snow/wakeup.c b/src/mainboard/google/snow/wakeup.c index 33ea9d8..8bb1724 100644 --- a/src/mainboard/google/snow/wakeup.c +++ b/src/mainboard/google/snow/wakeup.c @@ -26,16 +26,16 @@ #include "mainboard.h" -static int wakeup_need_reset(void) +static int snow_wakeup_need_reset(void) { /* The "wake up" event is not reliable (known as "bad wakeup") and needs * reset if GPIO value is high. */ return gpio_get_value(GPIO_Y10); } -void board_wakeup(void) +void snow_wakeup(void) { - if (wakeup_need_reset()) + if (snow_wakeup_need_reset()) power_reset(); power_init(); /* Ensure ps_hold_setup() for early wakeup. */ @@ -44,7 +44,7 @@ void board_wakeup(void) die("Failed to wake up.\n"); } -int board_get_wakeup_state() +int snow_get_wakeup_state() { uint32_t status = power_read_reset_status(); @@ -53,10 +53,10 @@ int board_get_wakeup_state() */ if (status == S5P_CHECK_DIDLE || status == S5P_CHECK_LPA) - return BOARD_WAKEUP_DIRECT; + return SNOW_WAKEUP_DIRECT; if (status == S5P_CHECK_SLEEP) - return BOARD_WAKEUP_NEED_CLOCK_RESET; + return SNOW_WAKEUP_NEED_CLOCK_RESET; - return BOARD_IS_NOT_WAKEUP; + return SNOW_IS_NOT_WAKEUP; }

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Patch merged into coreboot/master: dfad17d exynos5250: uncomment $(INTERMEDIATE)
by gerrit＠coreboot.org 26 Apr '13

26 Apr '13

the following patch was just integrated into master: commit dfad17de0293a56f68626ce47bfc14300f15e15c Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Apr 25 18:00:58 2013 -0700 exynos5250: uncomment $(INTERMEDIATE) This makes the intermediate rule visible so BL1 gets automatically placed in the final image. Change-Id: Iffb0268e5bbcbe135f2d39863ed64fa302409a22 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/3141 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Fri Apr 26 07:22:04 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Apr 26 03:09:01 2013, giving +2 See http://review.coreboot.org/3141 for details. -gerrit

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Patch set updated for coreboot: 2c8cfbf AMD Hudson A55E: Remove GEC firmware blob kconfig prompt
by Bruce Griffith 26 Apr '13

26 Apr '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3127 -gerrit commit 2c8cfbf9d26f5910aab86b9ee7bb9fc8fa1b702d Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Tue Apr 23 14:31:55 2013 -0600 AMD Hudson A55E: Remove GEC firmware blob kconfig prompt The "gigabit ethernet controller" (GEC) block was added to AMD Hudson A55E to integrate ethernet capabilities into an AMD southbridge. The GEC is designed to work with B50610 and B50610M gigabit PHY chips from Broadcom. These parts may not be generally available in small quantities for embedded development. The GEC block requires an opaque firmware blob to function. The GEC blob is controlled by AMD and Broadcom and is not available from coreboot.org. This change removes GEC support from AMD Parmer and AMD Thatcher mainboards since these boards do not have the Broadcom PHY. AMD has requested that the GEC be hidden for Hudson FCH since the PHY parts are not generally available. This Kconfig option can make it appear that this is a viable and supported way to add Ethernet to an embedded board. It is possible to use the Hudson GEC block with other PHYs, but this requires development of a custom GEC blob and a custom Ethernet driver. A custom GEC blob has been developed for a Micrel PHY, but there is no accompanying driver. Change-Id: I7a7bf4d41e453390ecf987c9c45ef2434fc1f1a3 Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/mainboard/amd/parmer/BiosCallOuts.c | 2 +- src/mainboard/amd/parmer/agesawrapper.c | 1 - src/mainboard/amd/thatcher/BiosCallOuts.c | 2 +- src/mainboard/amd/thatcher/agesawrapper.c | 1 - src/southbridge/amd/agesa/hudson/Kconfig | 5 +++-- 5 files changed, 5 insertions(+), 6 deletions(-) diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index 924ea19..c77d78d 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -269,7 +269,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) * Fch Oem setting callback * * Configure platform specific Hudson device, - * such Azalia, SATA, GEC, IMC etc. + * such Azalia, SATA, IMC etc. */ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) { diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index aecd1ea..a81a997 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -557,7 +557,6 @@ STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams) FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; - FchParams->Gec.GecShadowRomBase = UserOptions.FchBldCfg->CfgGecShadowRomBase; FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index e0af994..9a3f61c 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -269,7 +269,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) * Fch Oem setting callback * * Configure platform specific Hudson device, - * such Azalia, SATA, GEC, IMC etc. + * such Azalia, SATA, IMC etc. */ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) { diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index df45148..f7577fd 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -559,7 +559,6 @@ STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams) FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; - FchParams->Gec.GecShadowRomBase = UserOptions.FchBldCfg->CfgGecShadowRomBase; FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 52692f9..3e58563 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -56,10 +56,11 @@ config HUDSON_IMC_FWM Add Hudson 2/3/4 IMC Firmware to support the onboard fan control config HUDSON_GEC_FWM - bool "Add gec firmware" + bool default n help - Add Hudson 2/3/4 GEC Firmware + Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC. + Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard. config HUDSON_XHCI_FWM_FILE string "XHCI firmware path and filename"

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New patch to review for coreboot: da9b302 exynos5250: uncomment $(INTERMEDIATE)
by David Hendricks 26 Apr '13

26 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3141 -gerrit commit da9b30280ea7111832e38d2f42ff98f48f65f0c4 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Apr 25 18:00:58 2013 -0700 exynos5250: uncomment $(INTERMEDIATE) This makes the intermediate rule visible so BL1 gets automatically placed in the final image. Change-Id: Iffb0268e5bbcbe135f2d39863ed64fa302409a22 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 25d1bc5..403c198 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -1,7 +1,7 @@ # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS -#INTERMEDIATE += exynos5250_add_bl1 +INTERMEDIATE += exynos5250_add_bl1 bootblock-y += pinmux.c mct.c power.c # Clock is required for UART

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Patch merged into coreboot/master: 64a69e8 armv7: invoke intermediate build rules
by gerrit＠coreboot.org 26 Apr '13

26 Apr '13

the following patch was just integrated into master: commit 64a69e8e4d942b08732e77fb82b0ea364eb2f398 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jan 2 17:48:49 2013 -0800 armv7: invoke intermediate build rules This adds $$(INTERMEDIATE) as a pre-requisite for coreboot.rom on armv7. It is modeled after the $(obj)/coreboot.rom rule for x86. Change-Id: I483a88035fa2288829b6e042e51ef932c8c4f23c Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2095 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Mon Jan 14 19:40:48 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Jan 16 18:29:34 2013, giving +2 See http://review.coreboot.org/2095 for details. -gerrit

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Patch set updated for coreboot: 0cd7b2d snow: cleanup legacy board_* function naming
by David Hendricks 25 Apr '13

25 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3140 -gerrit commit 0cd7b2defd2369adeb49185ccc5ada88f692f28e Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Apr 25 15:44:11 2013 -0700 snow: cleanup legacy board_* function naming These functions got their names from u-boot where board-specific functions get called from CPU code and various drivers, usually to fetch some kind of board-specific information. Coreboot's code flow is such that CPU and driver code gets called from mainboard code and is given the necessary parameters as function arguments. Thus CPU and driver code is isolated and does not need to call board-specific functions to determine things like I2C topology, what DRAM module is used for a particular board, etc. Change-Id: Ibc597af33c2162b0e33f62f6b6872cbe035066c6 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/mainboard.c | 2 +- src/mainboard/google/snow/mainboard.h | 6 +++--- src/mainboard/google/snow/memory.c | 2 +- src/mainboard/google/snow/wakeup.c | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index 4a0d181..5339dc5 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -46,7 +46,7 @@ struct { { LOGIC_Z, LOGIC_1, SNOW_CONFIG_RSVD }, }; -int board_get_config(void) +int get_board_config(void) { int i; int id0, id1; diff --git a/src/mainboard/google/snow/mainboard.h b/src/mainboard/google/snow/mainboard.h index 63a2c18..e3a4d01 100644 --- a/src/mainboard/google/snow/mainboard.h +++ b/src/mainboard/google/snow/mainboard.h @@ -33,7 +33,7 @@ enum snow_board_config { SNOW_CONFIG_RSVD, }; -int board_get_config(void); +int get_board_config(void); enum { BOARD_IS_NOT_WAKEUP, // A normal boot (not suspend/resume). @@ -43,7 +43,7 @@ enum { // controllers are re-initialized. }; -int board_get_wakeup_state(void); -void board_wakeup(void); +int get_wakeup_state(void); +void wakeup(void); #endif /* MAINBOARD_H */ diff --git a/src/mainboard/google/snow/memory.c b/src/mainboard/google/snow/memory.c index ba8c91f..a228ec4 100644 --- a/src/mainboard/google/snow/memory.c +++ b/src/mainboard/google/snow/memory.c @@ -459,7 +459,7 @@ struct mem_timings *get_mem_timings(void) enum mem_manuf mem_manuf; struct mem_timings *mem; - board_config = board_get_config(); + board_config = get_board_config(); switch (board_config) { case SNOW_CONFIG_ELPIDA_EVT: case SNOW_CONFIG_ELPIDA_DVT: diff --git a/src/mainboard/google/snow/wakeup.c b/src/mainboard/google/snow/wakeup.c index 33ea9d8..452752d 100644 --- a/src/mainboard/google/snow/wakeup.c +++ b/src/mainboard/google/snow/wakeup.c @@ -33,7 +33,7 @@ static int wakeup_need_reset(void) return gpio_get_value(GPIO_Y10); } -void board_wakeup(void) +void wakeup(void) { if (wakeup_need_reset()) power_reset(); @@ -44,7 +44,7 @@ void board_wakeup(void) die("Failed to wake up.\n"); } -int board_get_wakeup_state() +int get_wakeup_state() { uint32_t status = power_read_reset_status();

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New patch to review for coreboot: baf2061 snow: cleanup legacy "board_*" functions
by David Hendricks 25 Apr '13

25 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3140 -gerrit commit baf20613cbdfdcb603234bcacaf05ca0895110e2 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Apr 25 15:44:11 2013 -0700 snow: cleanup legacy "board_*" functions These functions got their names from u-boot where board-specific functions get called from CPU code and various drivers, usually to fetch some kind of board-specific information. Coreboot's code flow is such that CPU and driver code gets called from mainboard code and is given the necessary parameters as function arguments, and thus code is better isolated. Change-Id: Ibc597af33c2162b0e33f62f6b6872cbe035066c6 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/mainboard.c | 2 +- src/mainboard/google/snow/mainboard.h | 6 +++--- src/mainboard/google/snow/memory.c | 2 +- src/mainboard/google/snow/wakeup.c | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index 4a0d181..fda2703 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -46,7 +46,7 @@ struct { { LOGIC_Z, LOGIC_1, SNOW_CONFIG_RSVD }, }; -int board_get_config(void) +enum snow_board_config get_board_config(void) { int i; int id0, id1; diff --git a/src/mainboard/google/snow/mainboard.h b/src/mainboard/google/snow/mainboard.h index 63a2c18..e69cdbb 100644 --- a/src/mainboard/google/snow/mainboard.h +++ b/src/mainboard/google/snow/mainboard.h @@ -33,7 +33,7 @@ enum snow_board_config { SNOW_CONFIG_RSVD, }; -int board_get_config(void); +enum snow_board_config get_board_config(void); enum { BOARD_IS_NOT_WAKEUP, // A normal boot (not suspend/resume). @@ -43,7 +43,7 @@ enum { // controllers are re-initialized. }; -int board_get_wakeup_state(void); -void board_wakeup(void); +int get_wakeup_state(void); +void wakeup(void); #endif /* MAINBOARD_H */ diff --git a/src/mainboard/google/snow/memory.c b/src/mainboard/google/snow/memory.c index ba8c91f..a228ec4 100644 --- a/src/mainboard/google/snow/memory.c +++ b/src/mainboard/google/snow/memory.c @@ -459,7 +459,7 @@ struct mem_timings *get_mem_timings(void) enum mem_manuf mem_manuf; struct mem_timings *mem; - board_config = board_get_config(); + board_config = get_board_config(); switch (board_config) { case SNOW_CONFIG_ELPIDA_EVT: case SNOW_CONFIG_ELPIDA_DVT: diff --git a/src/mainboard/google/snow/wakeup.c b/src/mainboard/google/snow/wakeup.c index 33ea9d8..452752d 100644 --- a/src/mainboard/google/snow/wakeup.c +++ b/src/mainboard/google/snow/wakeup.c @@ -33,7 +33,7 @@ static int wakeup_need_reset(void) return gpio_get_value(GPIO_Y10); } -void board_wakeup(void) +void wakeup(void) { if (wakeup_need_reset()) power_reset(); @@ -44,7 +44,7 @@ void board_wakeup(void) die("Failed to wake up.\n"); } -int board_get_wakeup_state() +int get_wakeup_state() { uint32_t status = power_read_reset_status();

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Patch set updated for coreboot: 2b03d09 boot state: rebalance payload load vs actual boot
by Aaron Durbin 25 Apr '13

25 Apr '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3139 -gerrit commit 2b03d09ca7bb6a7399b4f939ce3252268a1d0847 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 24 22:59:45 2013 -0500 boot state: rebalance payload load vs actual boot The notion of loading a payload in the current boot state machine isn't actually loading the payload. The reason is that cbfs is just walked to find the payload. The actual loading and booting were occuring in selfboot(). Change this balance so that loading occurs in one function and actual booting happens in another. This allows for ample opportunity to delay work until just before booting. Change-Id: Ic91ed6050fc5d8bb90c8c33a44eea3b1ec84e32d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/cbfs.h | 3 ++- src/lib/hardwaremain.c | 12 +++++++++--- src/lib/selfboot.c | 18 +++++++++++------- 3 files changed, 22 insertions(+), 11 deletions(-) diff --git a/src/include/cbfs.h b/src/include/cbfs.h index ac249aa..c0098ea 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -78,7 +78,8 @@ int run_address(void *f); /* Defined in src/lib/selfboot.c */ struct lb_memory; -int selfboot(struct lb_memory *mem, struct cbfs_payload *payload); +void *selfload(struct lb_memory *mem, struct cbfs_payload *payload); +void selfboot(void *entry); /* Defined in individual arch / board implementation. */ int init_default_cbfs_media(struct cbfs_media *media); diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 54f58dc..e0c8d5c 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -194,6 +194,7 @@ static boot_state_t bs_write_tables(void *arg) static boot_state_t bs_payload_load(void *arg) { void *payload; + void *entry; timestamp_add_now(TS_LOAD_PAYLOAD); @@ -202,15 +203,20 @@ static boot_state_t bs_payload_load(void *arg) if (! payload) die("Could not find a payload\n"); + entry = selfload(get_lb_mem(), payload); + + if (! entry) + die("Could not load payload\n"); + /* Pass the payload to the next state. */ - boot_states[BS_PAYLOAD_BOOT].arg = payload; + boot_states[BS_PAYLOAD_BOOT].arg = entry; return BS_PAYLOAD_BOOT; } -static boot_state_t bs_payload_boot(void *payload) +static boot_state_t bs_payload_boot(void *entry) { - selfboot(get_lb_mem(), payload); + selfboot(entry); printk(BIOS_EMERG, "Boot failed"); /* Returning from this state will fail because the following signals diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 324d43e..4ebe109 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -512,7 +512,7 @@ static int load_self_segments( return 1; } -int selfboot(struct lb_memory *mem, struct cbfs_payload *payload) +void *selfload(struct lb_memory *mem, struct cbfs_payload *payload) { u32 entry=0; struct segment head; @@ -527,10 +527,18 @@ int selfboot(struct lb_memory *mem, struct cbfs_payload *payload) printk(BIOS_SPEW, "Loaded segments\n"); + return (void *)entry; + +out: + return NULL; +} + +void selfboot(void *entry) +{ /* Reset to booting from this image as late as possible */ boot_successful(); - printk(BIOS_DEBUG, "Jumping to boot code at %x\n", entry); + printk(BIOS_DEBUG, "Jumping to boot code at %p\n", entry); post_code(POST_ENTER_ELF_BOOT); #if CONFIG_COLLECT_TIMESTAMPS @@ -543,9 +551,5 @@ int selfboot(struct lb_memory *mem, struct cbfs_payload *payload) checkstack(_estack, 0); /* Jump to kernel */ - jmp_to_elf_entry((void*)entry, bounce_buffer, bounce_size); - return 1; - -out: - return 0; + jmp_to_elf_entry(entry, bounce_buffer, bounce_size); }

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Patch set updated for coreboot: c31845e x86: use boot state callbacks to disable rom cache
by Aaron Durbin 25 Apr '13

25 Apr '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3138 -gerrit commit c31845e86aa36bb33d819b40f07f007c9e056c84 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 24 20:59:43 2013 -0500 x86: use boot state callbacks to disable rom cache On x86 systems there is a concept of cachings the ROM. However, the typical policy is that the boot cpu is the only one with it enabled. In order to ensure the MTRRs are the same across cores the rom cache needs to be disabled prior to OS resume or boot handoff. Therefore, utilize the boot state callbacks to schedule the disabling of the ROM cache at the ramstage exit points. Change-Id: I4da5886d9f1cf4c6af2f09bb909f0d0f0faa4e62 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/boot/acpi.c | 3 --- src/cpu/x86/mtrr/mtrr.c | 10 +++++++++- src/include/cpu/cpu.h | 3 --- src/lib/selfboot.c | 4 ---- 4 files changed, 9 insertions(+), 11 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index a3bf718..3b77caa 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -637,9 +637,6 @@ void acpi_resume(void *wake_vec) /* Call mainboard resume handler first, if defined. */ if (mainboard_suspend_resume) mainboard_suspend_resume(); - /* Tear down the caching of the ROM. */ - if (disable_cache_rom) - disable_cache_rom(); post_code(POST_OS_RESUME); acpi_jump_to_wakeup(wake_vec); diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 6089127..b69787b 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -27,6 +27,7 @@ #include <stddef.h> #include <stdlib.h> #include <string.h> +#include <bootstate.h> #include <console/console.h> #include <device/device.h> #include <cpu/cpu.h> @@ -408,10 +409,17 @@ void x86_mtrr_disable_rom_caching(void) enable_cache(); } -void disable_cache_rom(void) +static void disable_cache_rom(void *unused) { x86_mtrr_disable_rom_caching(); } + +BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { + BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, + disable_cache_rom, NULL), + BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, + disable_cache_rom, NULL), +}; #endif struct var_mtrr_state { diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index a2272f3..bed77de 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -9,9 +9,6 @@ struct bus; void initialize_cpus(struct bus *cpu_bus); void asmlinkage secondary_cpu_init(unsigned int cpu_index); -/* If a ROM cache was set up disable it before jumping to the payload or OS. */ -void __attribute__((weak)) disable_cache_rom(void); - #if CONFIG_HAVE_SMI_HANDLER void smm_init(void); void smm_lock(void); diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 934c131..324d43e 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -537,10 +537,6 @@ int selfboot(struct lb_memory *mem, struct cbfs_payload *payload) timestamp_add_now(TS_SELFBOOT_JUMP); #endif - /* Tear down the caching of the ROM. */ - if (disable_cache_rom) - disable_cache_rom(); - /* Before we go off to run the payload, see if * we stayed within our bounds. */

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Patch set updated for coreboot: f886e5d boot: remove cbmem_post_handling()
by Aaron Durbin 25 Apr '13

25 Apr '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3137 -gerrit commit f886e5d79ecc0a6b795d9c3715f5084901977b5b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 24 17:31:49 2013 -0500 boot: remove cbmem_post_handling() The cbmem_post_handling() function was implemented by 2 chipsets in order to save memory configuration in flash. Convert both of these chipsets to use the boot state machine callbacks to perform the saving of the memory configuration. Change-Id: I697e5c946281b85a71d8533437802d7913135af3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/cbmem.h | 1 - src/lib/hardwaremain.c | 4 ---- src/northbridge/intel/haswell/haswell.h | 2 -- src/northbridge/intel/haswell/mrccache.c | 8 +++++++- src/northbridge/intel/haswell/northbridge.c | 5 ----- src/northbridge/intel/sandybridge/mrccache.c | 8 +++++++- src/northbridge/intel/sandybridge/northbridge.c | 5 ----- src/northbridge/intel/sandybridge/sandybridge.h | 2 -- 8 files changed, 14 insertions(+), 21 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index ca2c50b..67cb1cb 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -159,7 +159,6 @@ void *cbmem_find(u32 id); /* Ramstage only functions. */ void cbmem_list(void); void cbmem_arch_init(void); -void __attribute__((weak)) cbmem_post_handling(void); void cbmem_print_entry(int n, u32 id, u64 start, u64 size); #else static inline void cbmem_arch_init(void) {} diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index e39827d..54f58dc 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -37,7 +37,6 @@ #if CONFIG_HAVE_ACPI_RESUME #include <arch/acpi.h> #endif -#include <cbmem.h> #include <timestamp.h> #define BS_DEBUG_LVL BIOS_NEVER @@ -182,9 +181,6 @@ static boot_state_t bs_os_resume(void *wake_vector) static boot_state_t bs_write_tables(void *arg) { - if (cbmem_post_handling) - cbmem_post_handling(); - timestamp_add_now(TS_WRITE_TABLES); /* Now that we have collected all of our information diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index ba88722..96438ad 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -237,8 +237,6 @@ struct mrc_data_container { struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) -void update_mrc_cache(void); - #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion); #endif diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 032bae4..f60d0f7 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <string.h> +#include <bootstate.h> #include <console/console.h> #include <cbfs.h> #include <ip_checksum.h> @@ -153,7 +154,7 @@ static struct mrc_data_container *find_next_mrc_cache return mrc_cache; } -void update_mrc_cache(void) +static void update_mrc_cache(void *unused) { printk(BIOS_DEBUG, "Updating MRC cache data.\n"); struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); @@ -222,6 +223,11 @@ void update_mrc_cache(void) flash->write(flash, to_flash_offset(cache), current->mrc_data_size + sizeof(*current), current); } + +BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { + BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, + update_mrc_cache, NULL), +}; #endif struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 16196ad..5c1ab3e 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -53,11 +53,6 @@ int bridge_silicon_revision(void) return bridge_revision_id; } -void cbmem_post_handling(void) -{ - update_mrc_cache(); -} - static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index 9c6330c..745958a 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <string.h> +#include <bootstate.h> #include <console/console.h> #include <cbfs.h> #include <ip_checksum.h> @@ -153,7 +154,7 @@ static struct mrc_data_container *find_next_mrc_cache return mrc_cache; } -void update_mrc_cache(void) +static void update_mrc_cache(void *unused) { printk(BIOS_DEBUG, "Updating MRC cache data.\n"); struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); @@ -222,6 +223,11 @@ void update_mrc_cache(void) flash->write(flash, to_flash_offset(cache), current->mrc_data_size + sizeof(*current), current); } + +BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { + BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, + update_mrc_cache, NULL), +}; #endif struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index b8022b8..0a413b4 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -60,11 +60,6 @@ int bridge_silicon_revision(void) static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 384; -void cbmem_post_handling(void) -{ - update_mrc_cache(); -} - static int get_pcie_bar(u32 *base, u32 *len) { device_t dev; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index bb1b1a3..291ea46 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -233,8 +233,6 @@ struct mrc_data_container { struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) -void update_mrc_cache(void); - #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion); #endif

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coreboot-gerrit April 2013