April 2013 - coreboot-gerrit - mail.coreboot.org

New patch to review for coreboot: d3e799c AMD SATA: Correct »them implement« to »then implement« in comments
by Paul Menzel April 28, 2013

April 28, 2013

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3145 -gerrit commit d3e799c89fe268dd62e1dbc77c37f083f4d926ee Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Apr 28 14:44:08 2013 +0200 AMD SATA: Correct »them implement« to »then implement« in comments The following command was used to correct all occurences of this typo. $ git grep -l "them implem" | xargs sed -i 's/them implem/then implem/' Change-Id: Iebd4635867d67861aaf4d4d64ca8a67e87833f38 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciMid.c | 2 +- src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeMid.c | 2 +- src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciMid.c | 2 +- src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeMid.c | 2 +- src/vendorcode/amd/cimx/sb800/SATA.c | 2 +- src/vendorcode/amd/cimx/sb900/Sata.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciMid.c index d866d56..7b75acb 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciMid.c +++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciMid.c @@ -68,7 +68,7 @@ FchInitMidSataIde2Ahci ( SataBar5setting (LocalCfgPtr, &Bar5); // - //If this is not S3 resume and also if SATA set to one of IDE mode, them implement drive detection workaround. + //If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround. // if ( ! (LocalCfgPtr->Misc.S3Resume) ) { SataDriveDetection (LocalCfgPtr, &Bar5); diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeMid.c index c4a75dd..6b4d75d 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeMid.c +++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeMid.c @@ -67,7 +67,7 @@ FchInitMidSataIde ( Bar5 = 0; SataBar5setting (LocalCfgPtr, &Bar5); // - //If this is not S3 resume and also if SATA set to one of IDE mode, them implement drive detection workaround. + //If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround. // if ( ! (LocalCfgPtr->Misc.S3Resume) ) { SataDriveDetection (LocalCfgPtr, &Bar5); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciMid.c index 8cb2fc9..e6d7798 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciMid.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciMid.c @@ -95,7 +95,7 @@ FchInitMidSataIde2Ahci ( SataBar5setting (LocalCfgPtr, &Bar5); // - //If this is not S3 resume and also if SATA set to one of IDE mode, them implement drive detection workaround. + //If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround. // if ( ! (LocalCfgPtr->Misc.S3Resume) ) { SataDriveDetection (LocalCfgPtr, &Bar5); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeMid.c index ba89d45..2f30fd3 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeMid.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeMid.c @@ -94,7 +94,7 @@ FchInitMidSataIde ( Bar5 = 0; SataBar5setting (LocalCfgPtr, &Bar5); // - //If this is not S3 resume and also if SATA set to one of IDE mode, them implement drive detection workaround. + //If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround. // if ( ! (LocalCfgPtr->Misc.S3Resume) ) { SataDriveDetection (LocalCfgPtr, &Bar5); diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c index 4aa3be7..5966ec8 100644 --- a/src/vendorcode/amd/cimx/sb800/SATA.c +++ b/src/vendorcode/amd/cimx/sb800/SATA.c @@ -544,7 +544,7 @@ sataInitMidPost ( { UINT32 ddBar5; sataBar5setting (pConfig, &ddBar5); - //If this is not S3 resume and also if SATA set to one of IDE mode, them implement drive detection workaround. + //If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround. if ( ! (pConfig->S3Resume) && ( ((pConfig->SataClass) != AHCI_MODE) && ((pConfig->SataClass) != RAID_MODE) ) ) { sataDriveDetection (pConfig, &ddBar5); } diff --git a/src/vendorcode/amd/cimx/sb900/Sata.c b/src/vendorcode/amd/cimx/sb900/Sata.c index 98e1f57..fca8005 100644 --- a/src/vendorcode/amd/cimx/sb900/Sata.c +++ b/src/vendorcode/amd/cimx/sb900/Sata.c @@ -852,7 +852,7 @@ sataInitMidPost ( { UINT32 ddBar5; sataBar5setting (pConfig, &ddBar5); - //If this is not S3 resume and also if SATA set to one of IDE mode, them implement drive detection workaround. + //If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround. if ( ! (pConfig->S3Resume) && ( ((pConfig->SataClass) != AHCI_MODE) && ((pConfig->SataClass) != RAID_MODE) ) ) { sataDriveDetection (pConfig, &ddBar5); }

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Patch set updated for coreboot: 8f9e637 Google/Snow: Enable suspend/resume.
by Ronald G. Minnich April 26, 2013

April 26, 2013

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3102 -gerrit commit 8f9e637b9ffcd247590ff0c272dd995acb4d0971 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Apr 25 19:49:40 2013 +0800 Google/Snow: Enable suspend/resume. Add the suspend/resume feature into bootblock and romstage. Note, resuming with X and touchpad driver may be still unstable. Verified by building and booting successfully on Google/Snow, and then executing the "suspend_stress_test" in text mode ("stop ui; suspend_stress_test") in Chromium OS, passed at least 20 iterations. Change-Id: I65681c42eeef2736e55bb906595f42a5b1dfdf11 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/mainboard/google/snow/bootblock.c | 17 ++++++++++++----- src/mainboard/google/snow/romstage.c | 13 ++++++++++--- 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index d2e0b50..6fca69c 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -25,16 +25,23 @@ #include <console/console.h> #include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/pinmux.h> +#include "mainboard.h" void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { - /* kick off the microsecond timer. We want to do this as early - * as we can. - */ - timer_start(); + switch (snow_get_wakeup_state()) { + case SNOW_WAKEUP_DIRECT: + snow_wakeup(); + break; - exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); + case SNOW_IS_NOT_WAKEUP: + /* kick off the microsecond timer. + * We want to do this as early as we can. + */ + timer_start(); + break; + } #if CONFIG_EARLY_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); console_init(); diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index fd5cfce..f131e81 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -170,15 +170,22 @@ void main(void) { struct mem_timings *mem; void *entry; + int is_resume = (snow_get_wakeup_state() != SNOW_IS_NOT_WAKEUP); /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ mem = snow_setup_clock(); - console_init(); - snow_setup_power(); + if (!is_resume) { + console_init(); + snow_setup_power(); + } + + snow_setup_memory(mem, is_resume); - snow_setup_memory(mem, 0); + if (is_resume) { + snow_wakeup(); + } snow_setup_storage(); snow_setup_gpio();

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Patch merged into coreboot/master: 31039e3 google/snow: Revise romstage initialization code.
by gerrit＠coreboot.org April 26, 2013

April 26, 2013

the following patch was just integrated into master: commit 31039e315c78b1b8a2cbef108ec4c07cb95c5e60 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Apr 25 19:30:19 2013 +0800 google/snow: Revise romstage initialization code. Move board setup procedure to snow_setup_* functions, and Snow board-specific (wakeup) code to snow_* for better function names and comments. Verified by successfully building and booting on Google/Snow. Change-Id: I2942d75064135093eeb1c1da188a005fd255111d Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: http://review.coreboot.org/3130 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Fri Apr 26 19:52:47 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri Apr 26 18:34:21 2013, giving +2 See http://review.coreboot.org/3130 for details. -gerrit

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New patch to review for coreboot: 0269f71 string: Add STRINGIFY macro
by Aaron Durbin April 26, 2013

April 26, 2013

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3144 -gerrit commit 0269f719b4bb6e270d9409d7ff3a42193312a16d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Apr 26 11:58:35 2013 -0500 string: Add STRINGIFY macro STRINGIFY makes a string from a token. It is generally useful. Even though STRINGIFY is not defined to be in the C library it's placed in string.h because it does make a string. Change-Id: I368e14792a90d1fdce2a3d4d7a48b5d400623160 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/string.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/include/string.h b/src/include/string.h index 44f244c..77985e1 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -4,6 +4,12 @@ #include <stddef.h> #include <stdlib.h> +/* Stringify a token */ +#ifndef STRINGIFY +#define _STRINGIFY(x) #x +#define STRINGIFY(x) _STRINGIFY(x) +#endif + void *memcpy(void *dest, const void *src, size_t n); void *memmove(void *dest, const void *src, size_t n); void *memset(void *s, int c, size_t n);

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Patch set updated for coreboot: c84fe58 x86: use boot state callbacks to disable rom cache
by Aaron Durbin April 26, 2013

April 26, 2013

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3138 -gerrit commit c84fe58364268df6bdd8193fdb065365d7a358bc Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 24 20:59:43 2013 -0500 x86: use boot state callbacks to disable rom cache On x86 systems there is a concept of cachings the ROM. However, the typical policy is that the boot cpu is the only one with it enabled. In order to ensure the MTRRs are the same across cores the rom cache needs to be disabled prior to OS resume or boot handoff. Therefore, utilize the boot state callbacks to schedule the disabling of the ROM cache at the ramstage exit points. Change-Id: I4da5886d9f1cf4c6af2f09bb909f0d0f0faa4e62 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/boot/acpi.c | 3 --- src/cpu/x86/mtrr/mtrr.c | 10 +++++++++- src/include/cpu/cpu.h | 3 --- src/lib/selfboot.c | 4 ---- 4 files changed, 9 insertions(+), 11 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index a3bf718..3b77caa 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -637,9 +637,6 @@ void acpi_resume(void *wake_vec) /* Call mainboard resume handler first, if defined. */ if (mainboard_suspend_resume) mainboard_suspend_resume(); - /* Tear down the caching of the ROM. */ - if (disable_cache_rom) - disable_cache_rom(); post_code(POST_OS_RESUME); acpi_jump_to_wakeup(wake_vec); diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 6089127..b69787b 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -27,6 +27,7 @@ #include <stddef.h> #include <stdlib.h> #include <string.h> +#include <bootstate.h> #include <console/console.h> #include <device/device.h> #include <cpu/cpu.h> @@ -408,10 +409,17 @@ void x86_mtrr_disable_rom_caching(void) enable_cache(); } -void disable_cache_rom(void) +static void disable_cache_rom(void *unused) { x86_mtrr_disable_rom_caching(); } + +BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { + BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, + disable_cache_rom, NULL), + BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, + disable_cache_rom, NULL), +}; #endif struct var_mtrr_state { diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index a2272f3..bed77de 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -9,9 +9,6 @@ struct bus; void initialize_cpus(struct bus *cpu_bus); void asmlinkage secondary_cpu_init(unsigned int cpu_index); -/* If a ROM cache was set up disable it before jumping to the payload or OS. */ -void __attribute__((weak)) disable_cache_rom(void); - #if CONFIG_HAVE_SMI_HANDLER void smm_init(void); void smm_lock(void); diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 934c131..324d43e 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -537,10 +537,6 @@ int selfboot(struct lb_memory *mem, struct cbfs_payload *payload) timestamp_add_now(TS_SELFBOOT_JUMP); #endif - /* Tear down the caching of the ROM. */ - if (disable_cache_rom) - disable_cache_rom(); - /* Before we go off to run the payload, see if * we stayed within our bounds. */

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Patch set updated for coreboot: df4885f boot state: rebalance payload load vs actual boot
by Aaron Durbin April 26, 2013

April 26, 2013

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3139 -gerrit commit df4885fa1cba12aa8cf9238e72f315ebad54629b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 24 22:59:45 2013 -0500 boot state: rebalance payload load vs actual boot The notion of loading a payload in the current boot state machine isn't actually loading the payload. The reason is that cbfs is just walked to find the payload. The actual loading and booting were occuring in selfboot(). Change this balance so that loading occurs in one function and actual booting happens in another. This allows for ample opportunity to delay work until just before booting. Change-Id: Ic91ed6050fc5d8bb90c8c33a44eea3b1ec84e32d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/cbfs.h | 3 ++- src/lib/hardwaremain.c | 12 +++++++++--- src/lib/selfboot.c | 18 +++++++++++------- 3 files changed, 22 insertions(+), 11 deletions(-) diff --git a/src/include/cbfs.h b/src/include/cbfs.h index ac249aa..c0098ea 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -78,7 +78,8 @@ int run_address(void *f); /* Defined in src/lib/selfboot.c */ struct lb_memory; -int selfboot(struct lb_memory *mem, struct cbfs_payload *payload); +void *selfload(struct lb_memory *mem, struct cbfs_payload *payload); +void selfboot(void *entry); /* Defined in individual arch / board implementation. */ int init_default_cbfs_media(struct cbfs_media *media); diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index adee3ca..ed2a516 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -198,6 +198,7 @@ static boot_state_t bs_write_tables(void *arg) static boot_state_t bs_payload_load(void *arg) { void *payload; + void *entry; timestamp_add_now(TS_LOAD_PAYLOAD); @@ -206,15 +207,20 @@ static boot_state_t bs_payload_load(void *arg) if (! payload) die("Could not find a payload\n"); + entry = selfload(get_lb_mem(), payload); + + if (! entry) + die("Could not load payload\n"); + /* Pass the payload to the next state. */ - boot_states[BS_PAYLOAD_BOOT].arg = payload; + boot_states[BS_PAYLOAD_BOOT].arg = entry; return BS_PAYLOAD_BOOT; } -static boot_state_t bs_payload_boot(void *payload) +static boot_state_t bs_payload_boot(void *entry) { - selfboot(get_lb_mem(), payload); + selfboot(entry); printk(BIOS_EMERG, "Boot failed"); /* Returning from this state will fail because the following signals diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 324d43e..4ebe109 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -512,7 +512,7 @@ static int load_self_segments( return 1; } -int selfboot(struct lb_memory *mem, struct cbfs_payload *payload) +void *selfload(struct lb_memory *mem, struct cbfs_payload *payload) { u32 entry=0; struct segment head; @@ -527,10 +527,18 @@ int selfboot(struct lb_memory *mem, struct cbfs_payload *payload) printk(BIOS_SPEW, "Loaded segments\n"); + return (void *)entry; + +out: + return NULL; +} + +void selfboot(void *entry) +{ /* Reset to booting from this image as late as possible */ boot_successful(); - printk(BIOS_DEBUG, "Jumping to boot code at %x\n", entry); + printk(BIOS_DEBUG, "Jumping to boot code at %p\n", entry); post_code(POST_ENTER_ELF_BOOT); #if CONFIG_COLLECT_TIMESTAMPS @@ -543,9 +551,5 @@ int selfboot(struct lb_memory *mem, struct cbfs_payload *payload) checkstack(_estack, 0); /* Jump to kernel */ - jmp_to_elf_entry((void*)entry, bounce_buffer, bounce_size); - return 1; - -out: - return 0; + jmp_to_elf_entry(entry, bounce_buffer, bounce_size); }

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Patch set updated for coreboot: e7292f1 boot: remove cbmem_post_handling()
by Aaron Durbin April 26, 2013

April 26, 2013

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3137 -gerrit commit e7292f11c15ec75d8d389c5a30b75c3436b98028 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 24 17:31:49 2013 -0500 boot: remove cbmem_post_handling() The cbmem_post_handling() function was implemented by 2 chipsets in order to save memory configuration in flash. Convert both of these chipsets to use the boot state machine callbacks to perform the saving of the memory configuration. Change-Id: I697e5c946281b85a71d8533437802d7913135af3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/cbmem.h | 1 - src/lib/hardwaremain.c | 4 ---- src/northbridge/intel/haswell/haswell.h | 2 -- src/northbridge/intel/haswell/mrccache.c | 8 +++++++- src/northbridge/intel/haswell/northbridge.c | 5 ----- src/northbridge/intel/sandybridge/mrccache.c | 8 +++++++- src/northbridge/intel/sandybridge/northbridge.c | 5 ----- src/northbridge/intel/sandybridge/sandybridge.h | 2 -- 8 files changed, 14 insertions(+), 21 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index ca2c50b..67cb1cb 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -159,7 +159,6 @@ void *cbmem_find(u32 id); /* Ramstage only functions. */ void cbmem_list(void); void cbmem_arch_init(void); -void __attribute__((weak)) cbmem_post_handling(void); void cbmem_print_entry(int n, u32 id, u64 start, u64 size); #else static inline void cbmem_arch_init(void) {} diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index dc2afa4..adee3ca 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -37,7 +37,6 @@ #if CONFIG_HAVE_ACPI_RESUME #include <arch/acpi.h> #endif -#include <cbmem.h> #include <timestamp.h> #if BOOT_STATE_DEBUG @@ -186,9 +185,6 @@ static boot_state_t bs_os_resume(void *wake_vector) static boot_state_t bs_write_tables(void *arg) { - if (cbmem_post_handling) - cbmem_post_handling(); - timestamp_add_now(TS_WRITE_TABLES); /* Now that we have collected all of our information diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index ba88722..96438ad 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -237,8 +237,6 @@ struct mrc_data_container { struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) -void update_mrc_cache(void); - #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion); #endif diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 032bae4..f60d0f7 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <string.h> +#include <bootstate.h> #include <console/console.h> #include <cbfs.h> #include <ip_checksum.h> @@ -153,7 +154,7 @@ static struct mrc_data_container *find_next_mrc_cache return mrc_cache; } -void update_mrc_cache(void) +static void update_mrc_cache(void *unused) { printk(BIOS_DEBUG, "Updating MRC cache data.\n"); struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); @@ -222,6 +223,11 @@ void update_mrc_cache(void) flash->write(flash, to_flash_offset(cache), current->mrc_data_size + sizeof(*current), current); } + +BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { + BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, + update_mrc_cache, NULL), +}; #endif struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 16196ad..5c1ab3e 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -53,11 +53,6 @@ int bridge_silicon_revision(void) return bridge_revision_id; } -void cbmem_post_handling(void) -{ - update_mrc_cache(); -} - static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index 9c6330c..745958a 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <string.h> +#include <bootstate.h> #include <console/console.h> #include <cbfs.h> #include <ip_checksum.h> @@ -153,7 +154,7 @@ static struct mrc_data_container *find_next_mrc_cache return mrc_cache; } -void update_mrc_cache(void) +static void update_mrc_cache(void *unused) { printk(BIOS_DEBUG, "Updating MRC cache data.\n"); struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); @@ -222,6 +223,11 @@ void update_mrc_cache(void) flash->write(flash, to_flash_offset(cache), current->mrc_data_size + sizeof(*current), current); } + +BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { + BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, + update_mrc_cache, NULL), +}; #endif struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index b8022b8..0a413b4 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -60,11 +60,6 @@ int bridge_silicon_revision(void) static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 384; -void cbmem_post_handling(void) -{ - update_mrc_cache(); -} - static int get_pcie_bar(u32 *base, u32 *len) { device_t dev; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index bb1b1a3..291ea46 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -233,8 +233,6 @@ struct mrc_data_container { struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) -void update_mrc_cache(void); - #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion); #endif

1 0

Patch set updated for coreboot: e0608c2 cbmem: use boot state machine
by Aaron Durbin April 26, 2013

April 26, 2013

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3136 -gerrit commit e0608c238623579ba38ab595cc0d4e249afd7814 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 24 16:39:08 2013 -0500 cbmem: use boot state machine There were previously 2 functions, init_cbmem_pre_device() and init_cbmem_post_device(), where the 2 cbmem implementations implemented one or the other. These 2 functions are no longer needed to be called in the boot flow once the boot state callbacks are utilized. Change-Id: Ida71f1187bdcc640ae600705ddb3517e1410a80d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/cbmem.h | 5 ----- src/lib/cbmem.c | 12 +++++++----- src/lib/dynamic_cbmem.c | 8 ++++++-- src/lib/hardwaremain.c | 3 --- 4 files changed, 13 insertions(+), 15 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 219dbfc..ca2c50b 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -161,11 +161,6 @@ void cbmem_list(void); void cbmem_arch_init(void); void __attribute__((weak)) cbmem_post_handling(void); void cbmem_print_entry(int n, u32 id, u64 start, u64 size); -/* The pre|post device cbmem initialization functions are for the - * ramstage main to call. When cbmem is actually initialized depends on - * the cbmem implementation. */ -void init_cbmem_pre_device(void); -void init_cbmem_post_device(void); #else static inline void cbmem_arch_init(void) {} #endif /* __PRE_RAM__ */ diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index ad98082..e8200b6 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -19,6 +19,7 @@ #include <types.h> #include <string.h> +#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) @@ -232,11 +233,7 @@ int cbmem_initialize(void) #endif #ifndef __PRE_RAM__ -/* cbmem cannot be initialized before device drivers, but it can be initialized - * after the drivers have run. */ -void init_cbmem_pre_device(void) {} - -void init_cbmem_post_device(void) +static void init_cbmem_post_device(void *unused) { cbmem_initialize(); #if CONFIG_CONSOLE_CBMEM @@ -244,6 +241,11 @@ void init_cbmem_post_device(void) #endif } +BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { + BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, + init_cbmem_post_device, NULL), +}; + void cbmem_list(void) { struct cbmem_entry *cbmem_toc; diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index ae6c87a..5c269a0 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <bootstate.h> #include <boot/tables.h> #include <console/console.h> #include <cbmem.h> @@ -411,7 +412,7 @@ void *cbmem_entry_start(const struct cbmem_entry *entry) /* selected cbmem can be initialized early in ramstage. Additionally, that * means cbmem console can be reinitialized early as well. The post_device * function is empty since cbmem was initialized early in ramstage. */ -void init_cbmem_pre_device(void) +static void init_cbmem_pre_device(void *unused) { cbmem_initialize(); #if CONFIG_CONSOLE_CBMEM @@ -419,7 +420,10 @@ void init_cbmem_pre_device(void) #endif /* CONFIG_CONSOLE_CBMEM */ } -void init_cbmem_post_device(void) {} +BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { + BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, + init_cbmem_pre_device, NULL), +}; void cbmem_add_lb_mem(struct lb_memory *mem) { diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index e4b2659..dc2afa4 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -97,7 +97,6 @@ static struct boot_state boot_states[] = { static boot_state_t bs_pre_device(void *arg) { - init_cbmem_pre_device(); return BS_DEV_INIT_CHIPS; } @@ -154,8 +153,6 @@ static boot_state_t bs_post_device(void *arg) { timestamp_stash(TS_DEVICE_DONE); - init_cbmem_post_device(); - timestamp_sync(); return BS_OS_RESUME_CHECK;

1 0

Patch set updated for coreboot: f9c4d54 ramstage: introduce boot state machine
by Aaron Durbin April 26, 2013

April 26, 2013

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3132 -gerrit commit f9c4d5416ee89c9739198e5bd6e2eba4d539c255 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 24 15:14:01 2013 -0500 ramstage: introduce boot state machine The boot flow currently has a fixed ordering. The ordering is dictated by the device tree and on x86 the PCI device ordering for when actions are performed. Many of the new machines and configurations have dependencies that do not follow the device ordering. In order to be more flexible the concept of a boot state machine is introduced. At the boundaries (entry and exit) of each state there is opportunity to run callbacks. This ability allows one to schedule actions to be performed without adding board-specific code to the shared boot flow. Change-Id: I757f406c97445f6d9b69c003bb9610b16b132aa6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/bootstate.h | 161 ++++++++++++++++++++++++++ src/lib/hardwaremain.c | 300 ++++++++++++++++++++++++++++++++++++++---------- 2 files changed, 401 insertions(+), 60 deletions(-) diff --git a/src/include/bootstate.h b/src/include/bootstate.h new file mode 100644 index 0000000..a2eacfb --- /dev/null +++ b/src/include/bootstate.h @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef BOOTSTATE_H +#define BOOTSTATE_H + +#include <string.h> + +/* Control debugging of the boot state machine. */ +#define BOOT_STATE_DEBUG 0 + +/* + * The boot state machine provides a mechanism for calls to be made through- + * out the main boot process. The boot process is separated into discrete + * states. Upon a state's entry and exit and callbacks can be made. For + * example: + * + * Enter State + * + + * | + * V + * +-----------------+ + * | Entry callbacks | + * +-----------------+ + * | State Actions | + * +-----------------+ + * | Exit callbacks | + * +-------+---------+ + * | + * V + * Next State + * + * Below is the current flow from top to bottom: + * + * start + * | + * BS_PRE_DEVICE + * | + * BS_DEV_INIT_CHIPS + * | + * BS_DEV_ENUMERATE + * | + * BS_DEV_RESOURCES + * | + * BS_DEV_ENABLE + * | + * BS_DEV_INIT + * | + * BS_POST_DEVICE + * | + * BS_OS_RESUME_CHECK -------- BS_OS_RESUME + * | | + * BS_WRITE_TABLES os handoff + * | + * BS_PAYLOAD_LOAD + * | + * BS_PAYLOAD_BOOT + * | + * payload run + * + * Brief description of states: + * BS_PRE_DEVICE - before any device tree actions take place + * BS_DEV_INIT_CHIPS - init all chips in device tree + * BS_DEV_ENUMERATE - device tree probing + * BS_DEV_RESOURCES - device tree resource allocation and assignment + * BS_DEV_ENABLE - device tree enabling/disabling of devices + * BS_DEV_INIT - device tree device initialization + * BS_POST_DEVICE - all device tree actions performed + * BS_OS_RESUME_CHECK - check for OS resume + * BS_OS_RESUME - resume to OS + * BS_WRITE_TABLES - write coreboot tables + * BS_PAYLOAD_LOAD - Load payload into memory + * BS_PAYLOAD_BOOT - Boot to payload + */ + +typedef enum { + BS_PRE_DEVICE, + BS_DEV_INIT_CHIPS, + BS_DEV_ENUMERATE, + BS_DEV_RESOURCES, + BS_DEV_ENABLE, + BS_DEV_INIT, + BS_POST_DEVICE, + BS_OS_RESUME, + BS_WRITE_TABLES, + BS_PAYLOAD_LOAD, + BS_PAYLOAD_BOOT, +} boot_state_t; + +/* The boot_state_sequence_t describes when a callback is to be made. It is + * called either before a state is entered or when a state is exited. */ +typedef enum { + BS_ON_ENTRY, + BS_ON_EXIT +} boot_state_sequence_t; + +struct boot_state_callback { + void *arg; + void (*callback)(void *arg); + /* For use internal to the boot state machine. */ + struct boot_state_callback *next; +#if BOOT_STATE_DEBUG + const char *location; +#endif +}; + +#if BOOT_STATE_DEBUG +#define BOOT_STATE_CALLBACK_LOC __FILE__ ":" STRINGIFY(__LINE__) +#define BOOT_STATE_CALLBACK_INIT_DEBUG .location = BOOT_STATE_CALLBACK_LOC, +#define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \ + bscb_->location = BOOT_STATE_CALLBACK_LOC; +#else +#define BOOT_STATE_CALLBACK_INIT_DEBUG +#define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) +#endif + +#define BOOT_STATE_CALLBACK_INIT(func_, arg_) \ + { \ + .arg = arg_, \ + .callback = func_, \ + .next = NULL, \ + BOOT_STATE_CALLBACK_INIT_DEBUG \ + } + +#define BOOT_STATE_CALLBACK(name_, func_, arg_) \ + struct boot_state_callback name_ = BOOT_STATE_CALLBACK_INIT(func_, arg_) + +/* Initialize an allocated boot_state_callback. */ +#define INIT_BOOT_STATE_CALLBACK(bscb_, func_, arg_) \ + INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \ + bscb_->callback = func_; \ + bscb_->arg = arg_ + +/* The following 2 functions schedule a callback to be called on entry/exit + * to a given state. Note that thare are no ordering guarantees between the + * individual callbacks on a given state. 0 is returned on success < 0 on + * error. */ +int boot_state_sched_on_entry(struct boot_state_callback *bscb, + boot_state_t state); +int boot_state_sched_on_exit(struct boot_state_callback *bscb, + boot_state_t state); + +/* Entry into the boot state machine. */ +void hardwaremain(int boot_complete); + +#endif /* BOOTSTATE_H */ diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index a3ee10b..dba47a7 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -1,23 +1,20 @@ /* -This software and ancillary information (herein called SOFTWARE ) -called LinuxBIOS is made available under the terms described -here. The SOFTWARE has been approved for release with associated -LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has -been authored by an employee or employees of the University of -California, operator of the Los Alamos National Laboratory under -Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The -U.S. Government has rights to use, reproduce, and distribute this -SOFTWARE. The public may copy, distribute, prepare derivative works -and publicly display this SOFTWARE without charge, provided that this -Notice and any statement of authorship are reproduced on all copies. -Neither the Government nor the University makes any warranty, express -or implied, or assumes any liability or responsibility for the use of -this SOFTWARE. If SOFTWARE is modified to produce derivative works, -such modified SOFTWARE should be clearly marked, so as not to confuse -it with the version available from LANL. - */ -/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL - * rminnich(a)lanl.gov + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ @@ -25,6 +22,7 @@ it with the version available from LANL. * C Bootstrap code for the coreboot */ +#include <bootstate.h> #include <console/console.h> #include <version.h> #include <device/device.h> @@ -43,80 +41,127 @@ it with the version available from LANL. #include <coverage.h> #include <timestamp.h> -/** - * @brief Main function of the RAM part of coreboot. - * - * Coreboot is divided into Pre-RAM part and RAM part. - * - * Device Enumeration: - * In the dev_enumerate() phase, - */ - -void hardwaremain(int boot_complete); - -void hardwaremain(int boot_complete) -{ - struct lb_memory *lb_mem; - void *payload; - - timestamp_stash(TS_START_RAMSTAGE); - post_code(POST_ENTRY_RAMSTAGE); - -#if CONFIG_COVERAGE - coverage_init(); +#if BOOT_STATE_DEBUG +#define BS_DEBUG_LVL BIOS_DEBUG +#else +#define BS_DEBUG_LVL BIOS_NEVER #endif - /* console_init() MUST PRECEDE ALL printk()! */ - console_init(); - - post_code(POST_CONSOLE_READY); - - printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n", - coreboot_version, coreboot_extra_version, coreboot_build, - (boot_complete)?"rebooting":"booting"); - - post_code(POST_CONSOLE_BOOT_MSG); - - /* If we have already booted attempt a hard reboot */ - if (boot_complete) { - hard_reset(); +static boot_state_t bs_pre_device(void *arg); +static boot_state_t bs_dev_init_chips(void *arg); +static boot_state_t bs_dev_enumerate(void *arg); +static boot_state_t bs_dev_resources(void *arg); +static boot_state_t bs_dev_eanble(void *arg); +static boot_state_t bs_dev_init(void *arg); +static boot_state_t bs_post_device(void *arg); +static boot_state_t bs_os_resume(void *arg); +static boot_state_t bs_write_tables(void *arg); +static boot_state_t bs_payload_load(void *arg); +static boot_state_t bs_payload_boot(void *arg); + +struct boot_state { + const char *name; + boot_state_t id; + struct boot_state_callback *seq_callbacks[2]; + boot_state_t (*run_state)(void *arg); + void *arg; + int complete; +}; + +#define BS_INIT(state_, run_func_) \ + { \ + .name = #state_, \ + .id = state_, \ + .seq_callbacks = { NULL, NULL },\ + .run_state = run_func_, \ + .arg = NULL, \ + .complete = 0 \ } - - /* FIXME: Is there a better way to handle this? */ - init_timer(); - +#define BS_INIT_ENTRY(state_, run_func_) \ + [state_] = BS_INIT(state_, run_func_) + +static struct boot_state boot_states[] = { + BS_INIT_ENTRY(BS_PRE_DEVICE, bs_pre_device), + BS_INIT_ENTRY(BS_DEV_INIT_CHIPS, bs_dev_init_chips), + BS_INIT_ENTRY(BS_DEV_ENUMERATE, bs_dev_enumerate), + BS_INIT_ENTRY(BS_DEV_RESOURCES, bs_dev_resources), + BS_INIT_ENTRY(BS_DEV_ENABLE, bs_dev_eanble), + BS_INIT_ENTRY(BS_DEV_INIT, bs_dev_init), + BS_INIT_ENTRY(BS_POST_DEVICE, bs_post_device), + BS_INIT_ENTRY(BS_OS_RESUME, bs_os_resume), + BS_INIT_ENTRY(BS_WRITE_TABLES, bs_write_tables), + BS_INIT_ENTRY(BS_PAYLOAD_LOAD, bs_payload_load), + BS_INIT_ENTRY(BS_PAYLOAD_BOOT, bs_payload_boot), +}; + +static boot_state_t bs_pre_device(void *arg) +{ init_cbmem_pre_device(); + return BS_DEV_INIT_CHIPS; +} +static boot_state_t bs_dev_init_chips(void *arg) +{ timestamp_stash(TS_DEVICE_ENUMERATE); /* Initialize chips early, they might disable unused devices. */ dev_initialize_chips(); + return BS_DEV_ENUMERATE; +} + +static boot_state_t bs_dev_enumerate(void *arg) +{ /* Find the devices we don't have hard coded knowledge about. */ dev_enumerate(); post_code(POST_DEVICE_ENUMERATION_COMPLETE); + return BS_DEV_RESOURCES; +} + +static boot_state_t bs_dev_resources(void *arg) +{ timestamp_stash(TS_DEVICE_CONFIGURE); /* Now compute and assign the bus resources. */ dev_configure(); post_code(POST_DEVICE_CONFIGURATION_COMPLETE); + return BS_DEV_ENABLE; +} + +static boot_state_t bs_dev_eanble(void *arg) +{ timestamp_stash(TS_DEVICE_ENABLE); /* Now actually enable devices on the bus */ dev_enable(); post_code(POST_DEVICES_ENABLED); + return BS_DEV_INIT; +} + +static boot_state_t bs_dev_init(void *arg) +{ timestamp_stash(TS_DEVICE_INITIALIZE); /* And of course initialize devices on the bus */ dev_initialize(); post_code(POST_DEVICES_INITIALIZED); + return BS_POST_DEVICE; +} + +static boot_state_t bs_post_device(void *arg) +{ timestamp_stash(TS_DEVICE_DONE); init_cbmem_post_device(); timestamp_sync(); + return BS_OS_RESUME; +} + +static boot_state_t bs_os_resume(void *arg) +{ #if CONFIG_HAVE_ACPI_RESUME suspend_resume(); post_code(0x8a); @@ -124,6 +169,11 @@ void hardwaremain(int boot_complete) timestamp_add_now(TS_CBMEM_POST); + return BS_WRITE_TABLES; +} + +static boot_state_t bs_write_tables(void *arg) +{ if (cbmem_post_handling) cbmem_post_handling(); @@ -132,7 +182,14 @@ void hardwaremain(int boot_complete) /* Now that we have collected all of our information * write our configuration tables. */ - lb_mem = write_tables(); + write_tables(); + + return BS_PAYLOAD_LOAD; +} + +static boot_state_t bs_payload_load(void *arg) +{ + void *payload; timestamp_add_now(TS_LOAD_PAYLOAD); @@ -141,7 +198,130 @@ void hardwaremain(int boot_complete) if (! payload) die("Could not find a payload\n"); - selfboot(lb_mem, payload); + /* Pass the payload to the next state. */ + boot_states[BS_PAYLOAD_BOOT].arg = payload; + + return BS_PAYLOAD_BOOT; +} + +static boot_state_t bs_payload_boot(void *payload) +{ + selfboot(get_lb_mem(), payload); + printk(BIOS_EMERG, "Boot failed"); + /* Returning from this state will fail because the following signals + * return to a completed state. */ + return BS_PAYLOAD_BOOT; +} + +static void bs_call_callbacks(struct boot_state *state, + boot_state_sequence_t seq) +{ + while (state->seq_callbacks[seq] != NULL) { + struct boot_state_callback *bscb; + + /* Remove the first callback. */ + bscb = state->seq_callbacks[seq]; + state->seq_callbacks[seq] = bscb->next; + bscb->next = NULL; + +#if BOOT_STATE_DEBUG + printk(BS_DEBUG_LVL, "BS: callback (%p) @ %s.\n", + bscb, bscb->location); +#endif + bscb->callback(bscb->arg); + } +} + +static void bs_walk_state_machine(boot_state_t current_state_id) +{ + + while (1) { + struct boot_state *state; + + state = &boot_states[current_state_id]; + + if (state->complete) { + printk(BIOS_EMERG, "BS: %s state already executed.\n", + state->name); + break; + } + + printk(BS_DEBUG_LVL, "BS: Entering %s state.\n", state->name); + bs_call_callbacks(state, BS_ON_ENTRY); + + current_state_id = state->run_state(state->arg); + + printk(BS_DEBUG_LVL, "BS: Exiting %s state.\n", state->name); + bs_call_callbacks(state, BS_ON_EXIT); + + state->complete = 1; + } +} + +static int boot_state_sched_callback(struct boot_state *state, + struct boot_state_callback *bscb, + boot_state_sequence_t seq) +{ + if (state->complete) { + printk(BIOS_WARNING, + "Tried to schedule callback on completed state %s.\n", + state->name); + + return -1; + } + + bscb->next = state->seq_callbacks[seq]; + state->seq_callbacks[seq] = bscb; + + return 0; +} + +int boot_state_sched_on_entry(struct boot_state_callback *bscb, + boot_state_t state_id) +{ + struct boot_state *state = &boot_states[state_id]; + + return boot_state_sched_callback(state, bscb, BS_ON_ENTRY); +} + +int boot_state_sched_on_exit(struct boot_state_callback *bscb, + boot_state_t state_id) +{ + struct boot_state *state = &boot_states[state_id]; + + return boot_state_sched_callback(state, bscb, BS_ON_EXIT); +} + +void hardwaremain(int boot_complete) +{ + timestamp_stash(TS_START_RAMSTAGE); + post_code(POST_ENTRY_RAMSTAGE); + +#if CONFIG_COVERAGE + coverage_init(); +#endif + + /* console_init() MUST PRECEDE ALL printk()! */ + console_init(); + + post_code(POST_CONSOLE_READY); + + printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n", + coreboot_version, coreboot_extra_version, coreboot_build, + (boot_complete)?"rebooting":"booting"); + + post_code(POST_CONSOLE_BOOT_MSG); + + /* If we have already booted attempt a hard reboot */ + if (boot_complete) { + hard_reset(); + } + + /* FIXME: Is there a better way to handle this? */ + init_timer(); + + bs_walk_state_machine(BS_PRE_DEVICE); + die("Boot state machine failure.\n"); }

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Patch set updated for coreboot: afcc976 acpi: split resume check and actual resume code
by Aaron Durbin April 26, 2013

April 26, 2013

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3134 -gerrit commit afcc976f2c15d7015fe595135ff9017181feda1a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 24 22:33:08 2013 -0500 acpi: split resume check and actual resume code It's helpful to provide a distinct state that affirmatively describes that OS resume will occur. The previous code included the check and the actual resuming in one function. Because of this grouping one had to annotate the innards of the ACPI resume path to perform specific actions before OS resume. By providing a distinct state in the boot state machine the necessary actions can be scheduled accordingly without modifying the ACPI code. Change-Id: I8b00aacaf820cbfbb21cb851c422a143371878bd Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/boot/acpi.c | 40 +++++++++++++++++----------------------- src/arch/x86/include/arch/acpi.h | 2 +- src/include/bootstate.h | 1 + src/lib/hardwaremain.c | 24 ++++++++++++++++++++---- 4 files changed, 39 insertions(+), 28 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 96ece06..1c373ac 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -622,37 +622,31 @@ void acpi_write_hest(acpi_hest_t *hest) } #if CONFIG_HAVE_ACPI_RESUME -void suspend_resume(void) +void acpi_resume(void *wake_vec) { - void *wake_vec; - - /* If we happen to be resuming find wakeup vector and jump to OS. */ - wake_vec = acpi_find_wakeup_vector(); - if (wake_vec) { #if CONFIG_HAVE_SMI_HANDLER - u32 *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS_PTR); + u32 *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS_PTR); - /* Restore GNVS pointer in SMM if found */ - if (gnvs_address && *gnvs_address) { - printk(BIOS_DEBUG, "Restore GNVS pointer to 0x%08x\n", - *gnvs_address); - smm_setup_structures((void *)*gnvs_address, NULL, NULL); - } + /* Restore GNVS pointer in SMM if found */ + if (gnvs_address && *gnvs_address) { + printk(BIOS_DEBUG, "Restore GNVS pointer to 0x%08x\n", + *gnvs_address); + smm_setup_structures((void *)*gnvs_address, NULL, NULL); + } #endif - /* Call mainboard resume handler first, if defined. */ - if (mainboard_suspend_resume) - mainboard_suspend_resume(); + /* Call mainboard resume handler first, if defined. */ + if (mainboard_suspend_resume) + mainboard_suspend_resume(); #if CONFIG_COVERAGE - coverage_exit(); + coverage_exit(); #endif - /* Tear down the caching of the ROM. */ - if (disable_cache_rom) - disable_cache_rom(); + /* Tear down the caching of the ROM. */ + if (disable_cache_rom) + disable_cache_rom(); - post_code(POST_OS_RESUME); - acpi_jump_to_wakeup(wake_vec); - } + post_code(POST_OS_RESUME); + acpi_jump_to_wakeup(wake_vec); } /* This is to be filled by SB code - startup value what was found. */ diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 022a45f..306f7da 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -558,7 +558,7 @@ void acpi_save_gnvs(u32 gnvs_address); /* 0 = S0, 1 = S1 ...*/ extern u8 acpi_slp_type; -void suspend_resume(void); +void acpi_resume(void *wake_vec); void __attribute__((weak)) mainboard_suspend_resume(void); void *acpi_find_wakeup_vector(void); void *acpi_get_wakeup_rsdp(void); diff --git a/src/include/bootstate.h b/src/include/bootstate.h index d11d2e7..7c259df 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -96,6 +96,7 @@ typedef enum { BS_DEV_ENABLE, BS_DEV_INIT, BS_POST_DEVICE, + BS_OS_RESUME_CHECK, BS_OS_RESUME, BS_WRITE_TABLES, BS_PAYLOAD_LOAD, diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 0a5a522..d8b9d43 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -54,6 +54,7 @@ static boot_state_t bs_dev_resources(void *arg); static boot_state_t bs_dev_eanble(void *arg); static boot_state_t bs_dev_init(void *arg); static boot_state_t bs_post_device(void *arg); +static boot_state_t bs_os_resume_check(void *arg); static boot_state_t bs_os_resume(void *arg); static boot_state_t bs_write_tables(void *arg); static boot_state_t bs_payload_load(void *arg); @@ -88,6 +89,7 @@ static struct boot_state boot_states[] = { BS_INIT_ENTRY(BS_DEV_ENABLE, bs_dev_eanble), BS_INIT_ENTRY(BS_DEV_INIT, bs_dev_init), BS_INIT_ENTRY(BS_POST_DEVICE, bs_post_device), + BS_INIT_ENTRY(BS_OS_RESUME_CHECK, bs_os_resume_check), BS_INIT_ENTRY(BS_OS_RESUME, bs_os_resume), BS_INIT_ENTRY(BS_WRITE_TABLES, bs_write_tables), BS_INIT_ENTRY(BS_PAYLOAD_LOAD, bs_payload_load), @@ -157,21 +159,35 @@ static boot_state_t bs_post_device(void *arg) timestamp_sync(); - return BS_OS_RESUME; + return BS_OS_RESUME_CHECK; } -static boot_state_t bs_os_resume(void *arg) +static boot_state_t bs_os_resume_check(void *arg) { #if CONFIG_HAVE_ACPI_RESUME - suspend_resume(); + void *wake_vector; + + wake_vector = acpi_find_wakeup_vector(); + + if (wake_vector != NULL) { + boot_states[BS_OS_RESUME].arg = wake_vector; + return BS_OS_RESUME; + } post_code(0x8a); #endif - timestamp_add_now(TS_CBMEM_POST); return BS_WRITE_TABLES; } +static boot_state_t bs_os_resume(void *wake_vector) +{ +#if CONFIG_HAVE_ACPI_RESUME + acpi_resume(wake_vector); +#endif + return BS_WRITE_TABLES; +} + static boot_state_t bs_write_tables(void *arg) { if (cbmem_post_handling)

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