Patch set updated for coreboot: e7292f1 boot: remove cbmem_post_handling()
Aaron Durbin (adurbin@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3137 -gerrit commit e7292f11c15ec75d8d389c5a30b75c3436b98028 Author: Aaron Durbin <adurbin@chromium.org> Date: Wed Apr 24 17:31:49 2013 -0500 boot: remove cbmem_post_handling() The cbmem_post_handling() function was implemented by 2 chipsets in order to save memory configuration in flash. Convert both of these chipsets to use the boot state machine callbacks to perform the saving of the memory configuration. Change-Id: I697e5c946281b85a71d8533437802d7913135af3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> --- src/include/cbmem.h | 1 - src/lib/hardwaremain.c | 4 ---- src/northbridge/intel/haswell/haswell.h | 2 -- src/northbridge/intel/haswell/mrccache.c | 8 +++++++- src/northbridge/intel/haswell/northbridge.c | 5 ----- src/northbridge/intel/sandybridge/mrccache.c | 8 +++++++- src/northbridge/intel/sandybridge/northbridge.c | 5 ----- src/northbridge/intel/sandybridge/sandybridge.h | 2 -- 8 files changed, 14 insertions(+), 21 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index ca2c50b..67cb1cb 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -159,7 +159,6 @@ void *cbmem_find(u32 id); /* Ramstage only functions. */ void cbmem_list(void); void cbmem_arch_init(void); -void __attribute__((weak)) cbmem_post_handling(void); void cbmem_print_entry(int n, u32 id, u64 start, u64 size); #else static inline void cbmem_arch_init(void) {} diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index dc2afa4..adee3ca 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -37,7 +37,6 @@ #if CONFIG_HAVE_ACPI_RESUME #include <arch/acpi.h> #endif -#include <cbmem.h> #include <timestamp.h> #if BOOT_STATE_DEBUG @@ -186,9 +185,6 @@ static boot_state_t bs_os_resume(void *wake_vector) static boot_state_t bs_write_tables(void *arg) { - if (cbmem_post_handling) - cbmem_post_handling(); - timestamp_add_now(TS_WRITE_TABLES); /* Now that we have collected all of our information diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index ba88722..96438ad 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -237,8 +237,6 @@ struct mrc_data_container { struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) -void update_mrc_cache(void); - #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion); #endif diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 032bae4..f60d0f7 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <string.h> +#include <bootstate.h> #include <console/console.h> #include <cbfs.h> #include <ip_checksum.h> @@ -153,7 +154,7 @@ static struct mrc_data_container *find_next_mrc_cache return mrc_cache; } -void update_mrc_cache(void) +static void update_mrc_cache(void *unused) { printk(BIOS_DEBUG, "Updating MRC cache data.\n"); struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); @@ -222,6 +223,11 @@ void update_mrc_cache(void) flash->write(flash, to_flash_offset(cache), current->mrc_data_size + sizeof(*current), current); } + +BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { + BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, + update_mrc_cache, NULL), +}; #endif struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 16196ad..5c1ab3e 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -53,11 +53,6 @@ int bridge_silicon_revision(void) return bridge_revision_id; } -void cbmem_post_handling(void) -{ - update_mrc_cache(); -} - static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index 9c6330c..745958a 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <string.h> +#include <bootstate.h> #include <console/console.h> #include <cbfs.h> #include <ip_checksum.h> @@ -153,7 +154,7 @@ static struct mrc_data_container *find_next_mrc_cache return mrc_cache; } -void update_mrc_cache(void) +static void update_mrc_cache(void *unused) { printk(BIOS_DEBUG, "Updating MRC cache data.\n"); struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); @@ -222,6 +223,11 @@ void update_mrc_cache(void) flash->write(flash, to_flash_offset(cache), current->mrc_data_size + sizeof(*current), current); } + +BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { + BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, + update_mrc_cache, NULL), +}; #endif struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index b8022b8..0a413b4 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -60,11 +60,6 @@ int bridge_silicon_revision(void) static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 384; -void cbmem_post_handling(void) -{ - update_mrc_cache(); -} - static int get_pcie_bar(u32 *base, u32 *len) { device_t dev; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index bb1b1a3..291ea46 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -233,8 +233,6 @@ struct mrc_data_container { struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) -void update_mrc_cache(void); - #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion); #endif
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Aaron Durbin