coreboot-gerrit April 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: afcc976 acpi: split resume check and actual resume code
by Aaron Durbin 26 Apr '13

26 Apr '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3134 -gerrit commit afcc976f2c15d7015fe595135ff9017181feda1a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 24 22:33:08 2013 -0500 acpi: split resume check and actual resume code It's helpful to provide a distinct state that affirmatively describes that OS resume will occur. The previous code included the check and the actual resuming in one function. Because of this grouping one had to annotate the innards of the ACPI resume path to perform specific actions before OS resume. By providing a distinct state in the boot state machine the necessary actions can be scheduled accordingly without modifying the ACPI code. Change-Id: I8b00aacaf820cbfbb21cb851c422a143371878bd Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/boot/acpi.c | 40 +++++++++++++++++----------------------- src/arch/x86/include/arch/acpi.h | 2 +- src/include/bootstate.h | 1 + src/lib/hardwaremain.c | 24 ++++++++++++++++++++---- 4 files changed, 39 insertions(+), 28 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 96ece06..1c373ac 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -622,37 +622,31 @@ void acpi_write_hest(acpi_hest_t *hest) } #if CONFIG_HAVE_ACPI_RESUME -void suspend_resume(void) +void acpi_resume(void *wake_vec) { - void *wake_vec; - - /* If we happen to be resuming find wakeup vector and jump to OS. */ - wake_vec = acpi_find_wakeup_vector(); - if (wake_vec) { #if CONFIG_HAVE_SMI_HANDLER - u32 *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS_PTR); + u32 *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS_PTR); - /* Restore GNVS pointer in SMM if found */ - if (gnvs_address && *gnvs_address) { - printk(BIOS_DEBUG, "Restore GNVS pointer to 0x%08x\n", - *gnvs_address); - smm_setup_structures((void *)*gnvs_address, NULL, NULL); - } + /* Restore GNVS pointer in SMM if found */ + if (gnvs_address && *gnvs_address) { + printk(BIOS_DEBUG, "Restore GNVS pointer to 0x%08x\n", + *gnvs_address); + smm_setup_structures((void *)*gnvs_address, NULL, NULL); + } #endif - /* Call mainboard resume handler first, if defined. */ - if (mainboard_suspend_resume) - mainboard_suspend_resume(); + /* Call mainboard resume handler first, if defined. */ + if (mainboard_suspend_resume) + mainboard_suspend_resume(); #if CONFIG_COVERAGE - coverage_exit(); + coverage_exit(); #endif - /* Tear down the caching of the ROM. */ - if (disable_cache_rom) - disable_cache_rom(); + /* Tear down the caching of the ROM. */ + if (disable_cache_rom) + disable_cache_rom(); - post_code(POST_OS_RESUME); - acpi_jump_to_wakeup(wake_vec); - } + post_code(POST_OS_RESUME); + acpi_jump_to_wakeup(wake_vec); } /* This is to be filled by SB code - startup value what was found. */ diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 022a45f..306f7da 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -558,7 +558,7 @@ void acpi_save_gnvs(u32 gnvs_address); /* 0 = S0, 1 = S1 ...*/ extern u8 acpi_slp_type; -void suspend_resume(void); +void acpi_resume(void *wake_vec); void __attribute__((weak)) mainboard_suspend_resume(void); void *acpi_find_wakeup_vector(void); void *acpi_get_wakeup_rsdp(void); diff --git a/src/include/bootstate.h b/src/include/bootstate.h index d11d2e7..7c259df 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -96,6 +96,7 @@ typedef enum { BS_DEV_ENABLE, BS_DEV_INIT, BS_POST_DEVICE, + BS_OS_RESUME_CHECK, BS_OS_RESUME, BS_WRITE_TABLES, BS_PAYLOAD_LOAD, diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 0a5a522..d8b9d43 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -54,6 +54,7 @@ static boot_state_t bs_dev_resources(void *arg); static boot_state_t bs_dev_eanble(void *arg); static boot_state_t bs_dev_init(void *arg); static boot_state_t bs_post_device(void *arg); +static boot_state_t bs_os_resume_check(void *arg); static boot_state_t bs_os_resume(void *arg); static boot_state_t bs_write_tables(void *arg); static boot_state_t bs_payload_load(void *arg); @@ -88,6 +89,7 @@ static struct boot_state boot_states[] = { BS_INIT_ENTRY(BS_DEV_ENABLE, bs_dev_eanble), BS_INIT_ENTRY(BS_DEV_INIT, bs_dev_init), BS_INIT_ENTRY(BS_POST_DEVICE, bs_post_device), + BS_INIT_ENTRY(BS_OS_RESUME_CHECK, bs_os_resume_check), BS_INIT_ENTRY(BS_OS_RESUME, bs_os_resume), BS_INIT_ENTRY(BS_WRITE_TABLES, bs_write_tables), BS_INIT_ENTRY(BS_PAYLOAD_LOAD, bs_payload_load), @@ -157,21 +159,35 @@ static boot_state_t bs_post_device(void *arg) timestamp_sync(); - return BS_OS_RESUME; + return BS_OS_RESUME_CHECK; } -static boot_state_t bs_os_resume(void *arg) +static boot_state_t bs_os_resume_check(void *arg) { #if CONFIG_HAVE_ACPI_RESUME - suspend_resume(); + void *wake_vector; + + wake_vector = acpi_find_wakeup_vector(); + + if (wake_vector != NULL) { + boot_states[BS_OS_RESUME].arg = wake_vector; + return BS_OS_RESUME; + } post_code(0x8a); #endif - timestamp_add_now(TS_CBMEM_POST); return BS_WRITE_TABLES; } +static boot_state_t bs_os_resume(void *wake_vector) +{ +#if CONFIG_HAVE_ACPI_RESUME + acpi_resume(wake_vector); +#endif + return BS_WRITE_TABLES; +} + static boot_state_t bs_write_tables(void *arg) { if (cbmem_post_handling)

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Patch set updated for coreboot: 068b03d coverage: use boot state callbacks
by Aaron Durbin 26 Apr '13

26 Apr '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3135 -gerrit commit 068b03d9b072fdf0b86dadf1d2777798d1e46219 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 24 16:28:52 2013 -0500 coverage: use boot state callbacks Utilize the static boot state callback scheduling to initialize and tear down the coverage infrastructure at the appropriate points. The coverage initialization is performed at BS_PRE_DEVICE which is the earliest point a callback can be called. The tear down occurs at the 2 exit points of ramstage: OS resume and payload boot. Change-Id: Ie5ee51268e1f473f98fa517710a266e38dc01b6d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/boot/acpi.c | 4 ---- src/include/coverage.h | 21 --------------------- src/lib/gcov-glue.c | 12 ++++++++---- src/lib/hardwaremain.c | 5 ----- src/lib/selfboot.c | 4 ---- 5 files changed, 8 insertions(+), 38 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 1c373ac..a3bf718 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -36,7 +36,6 @@ #if CONFIG_COLLECT_TIMESTAMPS #include <timestamp.h> #endif -#include <coverage.h> /* FIXME: Kconfig doesn't support overridable defaults :-( */ #ifndef CONFIG_HPET_MIN_TICKS @@ -638,9 +637,6 @@ void acpi_resume(void *wake_vec) /* Call mainboard resume handler first, if defined. */ if (mainboard_suspend_resume) mainboard_suspend_resume(); -#if CONFIG_COVERAGE - coverage_exit(); -#endif /* Tear down the caching of the ROM. */ if (disable_cache_rom) disable_cache_rom(); diff --git a/src/include/coverage.h b/src/include/coverage.h deleted file mode 100644 index e1c50c5..0000000 --- a/src/include/coverage.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA - */ - -void coverage_init(void); -void coverage_exit(void); diff --git a/src/lib/gcov-glue.c b/src/lib/gcov-glue.c index 4e2b290..ab9062b 100644 --- a/src/lib/gcov-glue.c +++ b/src/lib/gcov-glue.c @@ -18,8 +18,8 @@ */ #include <stdint.h> +#include <bootstate.h> #include <cbmem.h> -#include <coverage.h> typedef struct file { uint32_t magic; @@ -128,7 +128,7 @@ static void setbuf(FILE *stream, char *buf) gcc_assert(buf == 0); } -void coverage_init(void) +static void coverage_init(void *unused) { extern long __CTOR_LIST__; typedef void (*func_ptr)(void) ; @@ -142,7 +142,7 @@ void coverage_init(void) } void __gcov_flush(void); -void coverage_exit(void) +static void coverage_exit(void *unused) { #if CONFIG_DEBUG_COVERAGE printk(BIOS_DEBUG, "Syncing coverage data.\n"); @@ -150,4 +150,8 @@ void coverage_exit(void) __gcov_flush(); } - +BOOT_STATE_INIT_ENTRIES(gcov_bscb) = { + BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, coverage_init, NULL), + BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, coverage_exit, NULL), + BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, coverage_exit, NULL), +}; diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index d8b9d43..e4b2659 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -38,7 +38,6 @@ #include <arch/acpi.h> #endif #include <cbmem.h> -#include <coverage.h> #include <timestamp.h> #if BOOT_STATE_DEBUG @@ -331,10 +330,6 @@ void hardwaremain(int boot_complete) timestamp_stash(TS_START_RAMSTAGE); post_code(POST_ENTRY_RAMSTAGE); -#if CONFIG_COVERAGE - coverage_init(); -#endif - /* console_init() MUST PRECEDE ALL printk()! */ console_init(); diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index be03b85..934c131 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -33,7 +33,6 @@ #if CONFIG_COLLECT_TIMESTAMPS #include <timestamp.h> #endif -#include <coverage.h> /* Maximum physical address we can use for the coreboot bounce buffer. */ #ifndef MAX_ADDR @@ -537,9 +536,6 @@ int selfboot(struct lb_memory *mem, struct cbfs_payload *payload) #if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_SELFBOOT_JUMP); #endif -#if CONFIG_COVERAGE - coverage_exit(); -#endif /* Tear down the caching of the ROM. */ if (disable_cache_rom)

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Patch merged into coreboot/master: 526a46e Intel 82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2
by gerrit＠coreboot.org 26 Apr '13

26 Apr '13

the following patch was just integrated into master: commit 526a46ed7e4feb9e2cb02dffccbf40182c8cc014 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 13:00:34 2013 +0200 Intel 82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2 Commit »Support for the Intel ICH7 southbridge.« (debb11fc) [1] used `1 << 25` to set the I/O APIC ID of 2. Instead using `2 << 24`, which is the same value, makes it clear, that the I/O APIC ID is 2. Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2« (8c937c7e) [2] is used as a template. [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=debb11fc1fe5f55… [2] http://review.coreboot.org/3100 Change-Id: Ib688500944cd78a1cc1c8082bb138fa9468bdbfb Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3122 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Apr 26 17:48:31 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri Apr 26 18:36:58 2013, giving +2 See http://review.coreboot.org/3122 for details. -gerrit

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Patch set updated for coreboot: 8896f4b google/snow: Revise romstage initialization code.
by Paul Menzel 26 Apr '13

26 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3130 -gerrit commit 8896f4be1077a8bfdeeb482dcad8d5806325397b Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Apr 25 19:30:19 2013 +0800 google/snow: Revise romstage initialization code. Move board setup procedure to snow_setup_* functions, and Snow board-specific (wakeup) code to snow_* for better function names and comments. Verified by successfully building and booting on Google/Snow. Change-Id: I2942d75064135093eeb1c1da188a005fd255111d Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/mainboard/google/snow/mainboard.h | 10 ++-- src/mainboard/google/snow/romstage.c | 92 ++++++++++++++++++----------------- src/mainboard/google/snow/wakeup.c | 14 +++--- 3 files changed, 59 insertions(+), 57 deletions(-) diff --git a/src/mainboard/google/snow/mainboard.h b/src/mainboard/google/snow/mainboard.h index 63a2c18..5060b72 100644 --- a/src/mainboard/google/snow/mainboard.h +++ b/src/mainboard/google/snow/mainboard.h @@ -36,14 +36,14 @@ enum snow_board_config { int board_get_config(void); enum { - BOARD_IS_NOT_WAKEUP, // A normal boot (not suspend/resume). - BOARD_WAKEUP_DIRECT, // A wake up event that can be resumed any time. - BOARD_WAKEUP_NEED_CLOCK_RESET, // A wake up event that must be resumed + SNOW_IS_NOT_WAKEUP, // A normal boot (not suspend/resume). + SNOW_WAKEUP_DIRECT, // A wake up event that can be resumed any time. + SNOW_WAKEUP_NEED_CLOCK_RESET, // A wake up event that must be resumed // only after clock and memory // controllers are re-initialized. }; -int board_get_wakeup_state(void); -void board_wakeup(void); +int snow_get_wakeup_state(void); +void snow_wakeup(void); #endif /* MAINBOARD_H */ diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 6e312fa..fd5cfce 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -46,10 +46,16 @@ #define PMIC_BUS 0 #define MMC0_GPIO_PIN (58) -static int setup_pmic(void) +static void snow_setup_power(void) { int error = 0; + power_init(); + + /* Initialize I2C bus to configure PMIC. */ + i2c_init(0, CONFIG_SYS_I2C_SPEED, 0x00); + + printk(BIOS_DEBUG, "%s: Setting up PMIC...\n", __func__); /* * We're using CR1616 coin cell battery that is non-rechargeable * battery. But, BBCHOSTEN bit of the BBAT Charger Register in @@ -81,19 +87,19 @@ static int setup_pmic(void) error |= max77686_enable_32khz_cp(PMIC_BUS); - if (error) - printk(BIOS_CRIT, "%s: Error during PMIC setup\n", __func__); - - return error; + if (error) { + printk(BIOS_CRIT, "%s: PMIC error: %#x\n", __func__, error); + die("Failed to intialize PMIC.\n"); + } } -static void initialize_s5p_mshc(void) +static void snow_setup_storage(void) { /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ if (clock_set_mshci(PERIPH_ID_SDMMC0)) - printk(BIOS_CRIT, "Failed to set clock for SDMMC0.\n"); + printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__); if (gpio_direction_output(MMC0_GPIO_PIN, 1)) { - printk(BIOS_CRIT, "Unable to power on SDMMC0.\n"); + printk(BIOS_CRIT, "%s: Unable to power on MMC0.\n", __func__); } gpio_set_pull(MMC0_GPIO_PIN, EXYNOS_GPIO_PULL_NONE); gpio_set_drv(MMC0_GPIO_PIN, EXYNOS_GPIO_DRV_4X); @@ -104,12 +110,12 @@ static void initialize_s5p_mshc(void) exynos_pinmux_config(PERIPH_ID_SDMMC2, 0); } -static void graphics(void) +static void snow_setup_graphics(void) { exynos_pinmux_config(PERIPH_ID_DPHPD, 0); } -static void chromeos_gpios(void) +static void snow_setup_gpio(void) { struct exynos5_gpio_part1 *gpio_pt1; struct exynos5_gpio_part2 *gpio_pt2; @@ -137,53 +143,49 @@ static void chromeos_gpios(void) s5p_gpio_set_pull(&gpio_pt2->x1, POWER_GPIO, EXYNOS_GPIO_PULL_NONE); } +static void snow_setup_memory(struct mem_timings *mem, int is_resume) +{ + printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n", + mem->mem_manuf, + mem->mem_type, + mem->mpll_mdiv, + mem->frequency_mhz); + if (ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, !is_resume)) { + die("Failed to initialize memory controller.\n"); + } +} + +static struct mem_timings *snow_setup_clock(void) +{ + struct mem_timings *mem = get_mem_timings(); + struct arm_clk_ratios *arm_ratios = get_arm_clk_ratios(); + if (!mem) { + die("Unable to auto-detect memory timings\n"); + } + system_clock_init(mem, arm_ratios); + return mem; +} + void main(void) { struct mem_timings *mem; - struct arm_clk_ratios *arm_ratios; - int ret; void *entry; - clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ - /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ - mem = get_mem_timings(); - arm_ratios = get_arm_clk_ratios(); - system_clock_init(mem, arm_ratios); + mem = snow_setup_clock(); console_init(); + snow_setup_power(); - i2c_init(0, CONFIG_SYS_I2C_SPEED, 0x00); - if (power_init()) - power_shutdown(); - printk(BIOS_DEBUG, "%s: setting up pmic...\n", __func__); - if (setup_pmic()) - power_shutdown(); - - if (!mem) { - printk(BIOS_CRIT, "Unable to auto-detect memory timings\n"); - while(1); - } - printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n", - mem->mem_manuf, - mem->mem_type, - mem->mpll_mdiv, - mem->frequency_mhz); - - ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, 1); - if (ret) { - printk(BIOS_ERR, "Memory controller init failed, err: %x\n", - ret); - while(1); - } - - initialize_s5p_mshc(); - - chromeos_gpios(); + snow_setup_memory(mem, 0); - graphics(); + snow_setup_storage(); + snow_setup_gpio(); + snow_setup_graphics(); + /* Set SPI (primary CBFS media) clock to 50MHz. */ + clock_set_rate(PERIPH_ID_SPI1, 50000000); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry); diff --git a/src/mainboard/google/snow/wakeup.c b/src/mainboard/google/snow/wakeup.c index 33ea9d8..8bb1724 100644 --- a/src/mainboard/google/snow/wakeup.c +++ b/src/mainboard/google/snow/wakeup.c @@ -26,16 +26,16 @@ #include "mainboard.h" -static int wakeup_need_reset(void) +static int snow_wakeup_need_reset(void) { /* The "wake up" event is not reliable (known as "bad wakeup") and needs * reset if GPIO value is high. */ return gpio_get_value(GPIO_Y10); } -void board_wakeup(void) +void snow_wakeup(void) { - if (wakeup_need_reset()) + if (snow_wakeup_need_reset()) power_reset(); power_init(); /* Ensure ps_hold_setup() for early wakeup. */ @@ -44,7 +44,7 @@ void board_wakeup(void) die("Failed to wake up.\n"); } -int board_get_wakeup_state() +int snow_get_wakeup_state() { uint32_t status = power_read_reset_status(); @@ -53,10 +53,10 @@ int board_get_wakeup_state() */ if (status == S5P_CHECK_DIDLE || status == S5P_CHECK_LPA) - return BOARD_WAKEUP_DIRECT; + return SNOW_WAKEUP_DIRECT; if (status == S5P_CHECK_SLEEP) - return BOARD_WAKEUP_NEED_CLOCK_RESET; + return SNOW_WAKEUP_NEED_CLOCK_RESET; - return BOARD_IS_NOT_WAKEUP; + return SNOW_IS_NOT_WAKEUP; }

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Patch set updated for coreboot: 835aebf Lenovo ThinkPad X60: Init CBMEM early for CBMEM console support.
by Paul Menzel 26 Apr '13

26 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3142 -gerrit commit 835aebf9dbdf770d0b3d3430ca8e577cee603d91 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Apr 26 12:21:41 2013 +0200 Lenovo ThinkPad X60: Init CBMEM early for CBMEM console support. Enable `EARLY_CBMEM_INIT` for CBMEM console support by looking how other boards do this. This commit is tested by enabling the CBMEM console (`CONSOLE_CBMEM` in Kconfig) and then in GRUB 2 (as a payload) with the cbmemc command from the cbmemc module and in userspace with ./cbmem -c. Both worked. Change-Id: I34618a55ded7292a411bc232eb76267eec17d91e Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/lenovo/x60/romstage.c | 14 ++++++++++---- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 611f932..1431a2f 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select USE_OPTION_TABLE select MAINBOARD_HAS_NATIVE_VGA_INIT + select EARLY_CBMEM_INIT config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 8d5f922..d3c1d8a 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -29,6 +29,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <lib.h> +#include <cbmem.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> @@ -216,6 +217,7 @@ void main(unsigned long bist) { u32 reg32; int boot_mode = 0; + int cbmem_was_initted; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; if (bist == 0) @@ -314,14 +316,13 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; -#if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; + cbmem_was_initted = !cbmem_initialize(); +#if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_was_initted) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption @@ -336,4 +337,9 @@ void main(unsigned long bist) pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } #endif + +#if CONFIG_CONSOLE_CBMEM + /* Keep this the last thing this function does. */ + cbmemc_reinit(); +#endif }

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New patch to review for coreboot: 5f07c21 Kconfig: Capitalize CBMEM in description of `EARLY_CBMEM_INIT`
by Paul Menzel 26 Apr '13

26 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3143 -gerrit commit 5f07c215f9afaa0deaa7b5cacf95c02191768853 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Apr 26 17:15:07 2013 +0200 Kconfig: Capitalize CBMEM in description of `EARLY_CBMEM_INIT` Capitalizing CBMEM seems to be the official spelling as can be seen in the descriptions around the `EARLY_CBMEM_INIT` Kconfig option. Change-Id: I046a678c3b04ef7e681de46aa137cedc405d546f Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index c3cc6bf..8ff59d0 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -174,7 +174,7 @@ config EARLY_CBMEM_INIT bool default n help - Make coreboot initialize the cbmem structures while running in ROM + Make coreboot initialize the CBMEM structures while running in ROM stage. This is useful when the ROM stage wants to communicate some, for instance, execution timestamps. It needs support in romstage.c and should be enabled by the board's Kconfig.

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Patch set updated for coreboot: 5676ba8 Lenovo ThinkPad X60: Init CBMEM early and add CBMEM console support.
by Paul Menzel 26 Apr '13

26 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3142 -gerrit commit 5676ba8563456996553f7e088f75b476424af4cb Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Apr 26 12:21:41 2013 +0200 Lenovo ThinkPad X60: Init CBMEM early and add CBMEM console support. Enable EARLY_CBMEM_INIT and add CBMEM console support. This commit is tested in GRUB 2 (as a payload) with the cbmemc command from the cbmemc module and in userspace with ./cbmem -c. Both worked. Change-Id: I34618a55ded7292a411bc232eb76267eec17d91e Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/lenovo/x60/romstage.c | 14 ++++++++++---- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 611f932..1431a2f 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select USE_OPTION_TABLE select MAINBOARD_HAS_NATIVE_VGA_INIT + select EARLY_CBMEM_INIT config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 8d5f922..d3c1d8a 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -29,6 +29,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <lib.h> +#include <cbmem.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> @@ -216,6 +217,7 @@ void main(unsigned long bist) { u32 reg32; int boot_mode = 0; + int cbmem_was_initted; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; if (bist == 0) @@ -314,14 +316,13 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; -#if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; + cbmem_was_initted = !cbmem_initialize(); +#if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_was_initted) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption @@ -336,4 +337,9 @@ void main(unsigned long bist) pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } #endif + +#if CONFIG_CONSOLE_CBMEM + /* Keep this the last thing this function does. */ + cbmemc_reinit(); +#endif }

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Patch set updated for coreboot: cda6246 Intel 82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2
by Ronald G. Minnich 26 Apr '13

26 Apr '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3122 -gerrit commit cda62461ca4fbe709befda9bd28b6c1be7cc4164 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Apr 23 13:00:34 2013 +0200 Intel 82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2 Commit »Support for the Intel ICH7 southbridge.« (debb11fc) [1] used `1 << 25` to set the I/O APIC ID of 2. Instead using `2 << 24`, which is the same value, makes it clear, that the I/O APIC ID is 2. Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2« (8c937c7e) [2] is used as a template. [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=debb11fc1fe5f55… [2] http://review.coreboot.org/3100 Change-Id: Ib688500944cd78a1cc1c8082bb138fa9468bdbfb Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/i82801gx/lpc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 3a94e84..777a6d7 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -52,12 +52,12 @@ static void i82801gx_enable_apic(struct device *dev) pci_write_config8(dev, ACPI_CNTL, ACPI_EN); *ioapic_index = 0; - *ioapic_data = (1 << 25); + *ioapic_data = (2 << 24); *ioapic_index = 0; reg32 = *ioapic_data; printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) + if (reg32 != (2 << 24)) die("APIC Error\n"); printk(BIOS_SPEW, "Dumping IOAPIC registers\n");

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New patch to review for coreboot: 11307f2 Lenovo ThinkPad X60: Add cbmem and cbmem console support.
by Denis Carikli 26 Apr '13

26 Apr '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3142 -gerrit commit 11307f22333c34e0a4d91896a7336e05574d5e21 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Apr 26 12:21:41 2013 +0200 Lenovo ThinkPad X60: Add cbmem and cbmem console support. This commit was tested in grub2(as a payload) with the cbmemc command, And in userspace with ./cbmem -c Both worked. Change-Id: I34618a55ded7292a411bc232eb76267eec17d91e Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/lenovo/x60/romstage.c | 14 ++++++++++---- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 611f932..1431a2f 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select USE_OPTION_TABLE select MAINBOARD_HAS_NATIVE_VGA_INIT + select EARLY_CBMEM_INIT config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 8d5f922..d3c1d8a 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -29,6 +29,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <lib.h> +#include <cbmem.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> @@ -216,6 +217,7 @@ void main(unsigned long bist) { u32 reg32; int boot_mode = 0; + int cbmem_was_initted; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; if (bist == 0) @@ -314,14 +316,13 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; -#if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; + cbmem_was_initted = !cbmem_initialize(); +#if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_was_initted) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption @@ -336,4 +337,9 @@ void main(unsigned long bist) pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } #endif + +#if CONFIG_CONSOLE_CBMEM + /* Keep this the last thing this function does. */ + cbmemc_reinit(); +#endif }

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Patch set updated for coreboot: 5c73a09 Google/Snow: Enable suspend/resume.
by Hung-Te Lin 26 Apr '13

26 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3102 -gerrit commit 5c73a09e9efda36b7983238ed1343eb3b4d3381f Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Apr 25 19:49:40 2013 +0800 Google/Snow: Enable suspend/resume. Add the suspend/resume feature into bootblock and romstage. Note, resuming with X and touchpad driver may be still unstable. Verified by building and booting successfully on Google/Snow, and then executing the "suspend_stress_test" in text mode ("stop ui; suspend_stress_test") in Chromium OS, passed at least 20 iterations. Change-Id: I65681c42eeef2736e55bb906595f42a5b1dfdf11 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/mainboard/google/snow/bootblock.c | 17 ++++++++++++----- src/mainboard/google/snow/romstage.c | 13 ++++++++++--- 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index d2e0b50..6fca69c 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -25,16 +25,23 @@ #include <console/console.h> #include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/pinmux.h> +#include "mainboard.h" void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { - /* kick off the microsecond timer. We want to do this as early - * as we can. - */ - timer_start(); + switch (snow_get_wakeup_state()) { + case SNOW_WAKEUP_DIRECT: + snow_wakeup(); + break; - exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); + case SNOW_IS_NOT_WAKEUP: + /* kick off the microsecond timer. + * We want to do this as early as we can. + */ + timer_start(); + break; + } #if CONFIG_EARLY_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); console_init(); diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index fd5cfce..f131e81 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -170,15 +170,22 @@ void main(void) { struct mem_timings *mem; void *entry; + int is_resume = (snow_get_wakeup_state() != SNOW_IS_NOT_WAKEUP); /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ mem = snow_setup_clock(); - console_init(); - snow_setup_power(); + if (!is_resume) { + console_init(); + snow_setup_power(); + } + + snow_setup_memory(mem, is_resume); - snow_setup_memory(mem, 0); + if (is_resume) { + snow_wakeup(); + } snow_setup_storage(); snow_setup_gpio();

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coreboot-gerrit April 2013