coreboot-gerrit April 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 802742b X86: add the Kconfig option for 64-bit builds
by Ronald G. Minnich 29 Apr '13

29 Apr '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3146 -gerrit commit 802742b5ec0dd1ebd8120fe7ed2b36c0808378c9 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Apr 29 05:34:40 2013 +0200 X86: add the Kconfig option for 64-bit builds Big memory machines -- with more memory than can be addressed with PAE -- are on their way. I had them many years ago. Time to start thinking about 64-bit coreboot. Creating the option is the first step. In a perfect world, we fix the early .S bits and have the right compiler and it all Just Works. Dream On. But on the NIX OS we found we shared over 95% of the code and the change was not hard, even when NIX was the first real 64-bit port of Plan 9. We hit a surprisingly small number of bugs. This is now an EXPERT option. To avoid dumping a giant patch set, which people do tend to not like, I'm doing this in an incremental way that breaks nothing. Change-Id: I02792ac94328a732f56073848975d2170d79cfd5 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/x86/Kconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 5f46145..34768b6 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -122,4 +122,17 @@ config ID_SECTION_OFFSET hex default 0x80 +config X86_64 + bool "Build for an x86_64 platform" + depends on EXPERT + default n + help + Build coreboot for 64-bit x86, not 32-bit. Pretty much + all the source should be the same. This will affect early + startup as we switch into long mode. On Intel platforms, + which have a binary blob, this will make calls into the + blob harder. On AMD platforms, and open Intel platforms, + this should Just Work. Though at present, this option + has no effect. + endmenu

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Patch set updated for coreboot: 666048e Google/Snow: Temporary fix for resume failure.
by Hung-Te Lin 29 Apr '13

29 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3148 -gerrit commit 666048e61c3a70adc298ad10a4cf372b5662f3c3 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Apr 29 22:11:22 2013 +0800 Google/Snow: Temporary fix for resume failure. The DDR3 memory initialization (with "mem_reset" set on normal boot) will cause resume to be unstable, especially when X is running. System may show X screen for few seconds, then crash randomly and unable to recover - although text console may still work for a while. Probably caused by corrupted memory pages. 'mem_reset' (which refers to RESET# in DDR3 spec) should be enabled according to DDR3 spec. But it seems that on Exynos 5, memory can be initialized without setting mem_reset for both normal boot and resume - at least no known failure cases are found yet. So this can be a temporary workaround. Verified by booting a Google/Snow device with X Window and ChromeOS, entering browser session with fancy web pages, closing LID to suspend for 5 seconds, then re-opening to resume. Suspend/resume worked as expected. Also tried the "suspend_stress_test" with X running and finished 100 iterations of suspend/resume test without failure. Change-Id: I7185b362ce8b545fe77b35a552245736c89d465e Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/mainboard/google/snow/romstage.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index f131e81..aa3a340 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -150,6 +150,14 @@ static void snow_setup_memory(struct mem_timings *mem, int is_resume) mem->mem_type, mem->mpll_mdiv, mem->frequency_mhz); + + /* FIXME Currently memory initialization with mem_reset on normal boot + * will cause resume to fail (even if we don't do mem_reset on resume), + * and the workaround is to temporarily always enable "is_resume". + * This should be removed when the root cause of resume issue is found. + */ + is_resume = 1; + if (ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, !is_resume)) { die("Failed to initialize memory controller.\n"); }

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Patch set updated for coreboot: 14ac3df Google/Snow: Clean up: remove unnecessary initialization in boot block.
by Hung-Te Lin 29 Apr '13

29 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3147 -gerrit commit 14ac3dfd96f0c89531fa994e5073a605d13a7f23 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Apr 29 22:20:35 2013 +0800 Google/Snow: Clean up: remove unnecessary initialization in boot block. The SPI1 interface is already initialized by iROM. The console_init has already printed some initialization message, so the "UART initialized" message is also not required. Verified by building and booting firmware image on Google/Snow successfully. Change-Id: I89390506aa825397c0d7e52ad7503f1cb808f7db Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/mainboard/google/snow/bootblock.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 09edbad..2d7beb1 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -40,12 +40,14 @@ void bootblock_mainboard_init(void) * We want to do this as early as we can. */ timer_start(); - exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); + /* The boot device (ex, SPI1) is already initialized by + * iROM (which loads the bootblock) so we don't need to + * configure pinmux for it. + */ break; } #if CONFIG_EARLY_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); console_init(); - printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__); #endif }

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Patch set updated for coreboot: ee8f865 Google/Snow: Clean up: remove unnecessary initialization in boot block.
by Hung-Te Lin 29 Apr '13

29 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3147 -gerrit commit ee8f8656c4bbc7517a3aba196bcde2ce5a8ef683 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Apr 29 22:20:35 2013 +0800 Google/Snow: Clean up: remove unnecessary initialization in boot block. The SPI1 interface is already initialized by iROM. The console_init has already printed some initialization message, so the "UART initialized" message is also not required. Verified by building and booting firmware image on Google/Snow successfully. Change-Id: I89390506aa825397c0d7e52ad7503f1cb808f7db Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/mainboard/google/snow/bootblock.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 09edbad..4b3553e 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -40,12 +40,10 @@ void bootblock_mainboard_init(void) * We want to do this as early as we can. */ timer_start(); - exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); break; } #if CONFIG_EARLY_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); console_init(); - printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__); #endif }

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Patch set updated for coreboot: 1805715 Google/Snow: Temporary fix for resume failure.
by Hung-Te Lin 29 Apr '13

29 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3148 -gerrit commit 1805715f8ce194c842d52523a886e1d79fa5fe03 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Apr 29 22:11:22 2013 +0800 Google/Snow: Temporary fix for resume failure. The DDR3 memory initialization (with "mem_reset" set on normal boot) will cause resume to be unstable. To prevent blocking development, temporarily disable mem_reset as a workaround. This will be removed once we find the root cause of mem_reset failure. Verified by booting a Google/Snow device, entering browser session with fancy web pages, closing LID to suspend for 5 seconds, then re-opening to resume. Suspend/resume worked as expected. Also tried the "suspend_stress_test" and finished 100 iterations of suspend/resume test without failure. Change-Id: I7185b362ce8b545fe77b35a552245736c89d465e Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/mainboard/google/snow/romstage.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index f131e81..aa3a340 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -150,6 +150,14 @@ static void snow_setup_memory(struct mem_timings *mem, int is_resume) mem->mem_type, mem->mpll_mdiv, mem->frequency_mhz); + + /* FIXME Currently memory initialization with mem_reset on normal boot + * will cause resume to fail (even if we don't do mem_reset on resume), + * and the workaround is to temporarily always enable "is_resume". + * This should be removed when the root cause of resume issue is found. + */ + is_resume = 1; + if (ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, !is_resume)) { die("Failed to initialize memory controller.\n"); }

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New patch to review for coreboot: de67151 Google/Snow: Temporary fix for resume failure.
by Hung-Te Lin 29 Apr '13

29 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3148 -gerrit commit de67151139d08b0b44ccd1e11b1fdec6bef53e2b Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Apr 29 22:11:22 2013 +0800 Google/Snow: Temporary fix for resume failure. The DDR3 memory initialization (with "mem_reset" set on normal boot) will cause resume to be unstable. To prevent blocking development, temporarily disable mem_reset as a workaround. This will be removed once we found the root cause of mem_reset failure. Change-Id: I7185b362ce8b545fe77b35a552245736c89d465e Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/mainboard/google/snow/romstage.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index f131e81..aa3a340 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -150,6 +150,14 @@ static void snow_setup_memory(struct mem_timings *mem, int is_resume) mem->mem_type, mem->mpll_mdiv, mem->frequency_mhz); + + /* FIXME Currently memory initialization with mem_reset on normal boot + * will cause resume to fail (even if we don't do mem_reset on resume), + * and the workaround is to temporarily always enable "is_resume". + * This should be removed when the root cause of resume issue is found. + */ + is_resume = 1; + if (ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, !is_resume)) { die("Failed to initialize memory controller.\n"); }

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New patch to review for coreboot: 5bf863f Google/Snow: Clean up: remove unnecessary initialization in boot block.
by Hung-Te Lin 29 Apr '13

29 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3147 -gerrit commit 5bf863fc58a4a8bbe68d126c8731d06cba83a35b Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Apr 29 22:20:35 2013 +0800 Google/Snow: Clean up: remove unnecessary initialization in boot block. The SPI1 interface is already initialized by iROM. The console_init has already printed some initialization message, so the "UART initialized" message is also not required. Change-Id: I89390506aa825397c0d7e52ad7503f1cb808f7db Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/mainboard/google/snow/bootblock.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 09edbad..4b3553e 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -40,12 +40,10 @@ void bootblock_mainboard_init(void) * We want to do this as early as we can. */ timer_start(); - exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); break; } #if CONFIG_EARLY_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); console_init(); - printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__); #endif }

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Patch merged into coreboot/master: 3f73eec Google/Snow: Enable suspend/resume.
by gerrit＠coreboot.org 29 Apr '13

29 Apr '13

the following patch was just integrated into master: commit 3f73eec4d3ea2bfdbece083dc0b8721e458b46fb Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Apr 25 19:49:40 2013 +0800 Google/Snow: Enable suspend/resume. Add the suspend/resume feature into bootblock and romstage. Note, resuming with X and touchpad driver may be still unstable. Verified by building and booting successfully on Google/Snow, and then executing the "suspend_stress_test" in text mode ("stop ui; suspend_stress_test") in Chromium OS, passed at least 20 iterations. Change-Id: I65681c42eeef2736e55bb906595f42a5b1dfdf11 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: http://review.coreboot.org/3102 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Build-Tested: build bot (Jenkins) at Mon Apr 29 11:25:58 2013, giving +1 Reviewed-By: Paul Menzel <paulepanter(a)users.sourceforge.net> at Mon Apr 29 12:46:45 2013, giving +1 Reviewed-By: Hung-Te Lin <hungte(a)chromium.org> at Mon Apr 29 15:34:10 2013, giving +2 See http://review.coreboot.org/3102 for details. -gerrit

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Patch set updated for coreboot: 2941089 Google/Snow: Enable suspend/resume.
by Hung-Te Lin 29 Apr '13

29 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3102 -gerrit commit 29410893c9a0b653b51d96264abfb7c3bdfd97cd Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Apr 25 19:49:40 2013 +0800 Google/Snow: Enable suspend/resume. Add the suspend/resume feature into bootblock and romstage. Note, resuming with X and touchpad driver may be still unstable. Verified by building and booting successfully on Google/Snow, and then executing the "suspend_stress_test" in text mode ("stop ui; suspend_stress_test") in Chromium OS, passed at least 20 iterations. Change-Id: I65681c42eeef2736e55bb906595f42a5b1dfdf11 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/mainboard/google/snow/bootblock.c | 18 +++++++++++++----- src/mainboard/google/snow/romstage.c | 13 ++++++++++--- 2 files changed, 23 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index d2e0b50..09edbad 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -25,16 +25,24 @@ #include <console/console.h> #include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/pinmux.h> +#include "mainboard.h" void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { - /* kick off the microsecond timer. We want to do this as early - * as we can. - */ - timer_start(); + switch (snow_get_wakeup_state()) { + case SNOW_WAKEUP_DIRECT: + snow_wakeup(); + break; - exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); + case SNOW_IS_NOT_WAKEUP: + /* kick off the microsecond timer. + * We want to do this as early as we can. + */ + timer_start(); + exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); + break; + } #if CONFIG_EARLY_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); console_init(); diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index fd5cfce..f131e81 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -170,15 +170,22 @@ void main(void) { struct mem_timings *mem; void *entry; + int is_resume = (snow_get_wakeup_state() != SNOW_IS_NOT_WAKEUP); /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ mem = snow_setup_clock(); - console_init(); - snow_setup_power(); + if (!is_resume) { + console_init(); + snow_setup_power(); + } + + snow_setup_memory(mem, is_resume); - snow_setup_memory(mem, 0); + if (is_resume) { + snow_wakeup(); + } snow_setup_storage(); snow_setup_gpio();

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New patch to review for coreboot: 4c05239 X86: add the Kconfig option for 64-bit builds
by Ronald G. Minnich 29 Apr '13

29 Apr '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3146 -gerrit commit 4c0523939eb989712138c49f87ef1a4f4f48014a Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Apr 29 05:34:40 2013 +0200 X86: add the Kconfig option for 64-bit builds Big memory machines -- with more memory than can be addressed with PAE -- are on their way. I had them many years ago. Time to start thinking about 64-bit coreboot. Creating the option is the first step. In a perfect world, we fix the early .S bits and have the right compiler and it all Just Works. Dream On. But on the NIX OS we found we shared over 95% of the code and the change was not hard, even when NIX was the first real 64-bit port of Plan 9. We hit a surprisingly small number of bugs. Change-Id: I02792ac94328a732f56073848975d2170d79cfd5 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/x86/Kconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 5f46145..fff9828 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -122,4 +122,16 @@ config ID_SECTION_OFFSET hex default 0x80 +config X86_64 + bool "Build for an x86_64 platform" + default n + help + Build coreboot for 64-bit x86, not 32-bit. Pretty much + all the source should be the same. This will affect early + startup as we switch into long mode. On Intel platforms, + which have a binary blob, this will make calls into the + blob harder. On AMD platforms, and open Intel platforms, + this should Just Work. Though at present, this option + has no effect. + endmenu

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coreboot-gerrit April 2013