coreboot-gerrit April 2013

coreboot-gerrit@coreboot.org

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506 discussions

New patch to review for coreboot: 4feac09 acpi: split resume check and actual resume code
by Aaron Durbin 25 Apr '13

25 Apr '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3134 -gerrit commit 4feac09fb7711f6e2a8d59e341d9f5f3d9f93afe Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 24 22:33:08 2013 -0500 acpi: split resume check and actual resume code It's helpful to provide a distinct state that affirmatively describes that OS resume will occur. The previous code included the check and the actual resuming in one function. Because of this grouping one had to annotate the innards of the ACPI resume path to perform specific actions before OS resume. By providing a distinct state in the boot state machine the necessary actions can be scheduled accordingly without modifying the ACPI code. Change-Id: I8b00aacaf820cbfbb21cb851c422a143371878bd Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/boot/acpi.c | 40 +++++++++++++++++----------------------- src/arch/x86/include/arch/acpi.h | 2 +- src/include/bootstate.h | 1 + src/lib/hardwaremain.c | 24 ++++++++++++++++++++---- 4 files changed, 39 insertions(+), 28 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 96ece06..1c373ac 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -622,37 +622,31 @@ void acpi_write_hest(acpi_hest_t *hest) } #if CONFIG_HAVE_ACPI_RESUME -void suspend_resume(void) +void acpi_resume(void *wake_vec) { - void *wake_vec; - - /* If we happen to be resuming find wakeup vector and jump to OS. */ - wake_vec = acpi_find_wakeup_vector(); - if (wake_vec) { #if CONFIG_HAVE_SMI_HANDLER - u32 *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS_PTR); + u32 *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS_PTR); - /* Restore GNVS pointer in SMM if found */ - if (gnvs_address && *gnvs_address) { - printk(BIOS_DEBUG, "Restore GNVS pointer to 0x%08x\n", - *gnvs_address); - smm_setup_structures((void *)*gnvs_address, NULL, NULL); - } + /* Restore GNVS pointer in SMM if found */ + if (gnvs_address && *gnvs_address) { + printk(BIOS_DEBUG, "Restore GNVS pointer to 0x%08x\n", + *gnvs_address); + smm_setup_structures((void *)*gnvs_address, NULL, NULL); + } #endif - /* Call mainboard resume handler first, if defined. */ - if (mainboard_suspend_resume) - mainboard_suspend_resume(); + /* Call mainboard resume handler first, if defined. */ + if (mainboard_suspend_resume) + mainboard_suspend_resume(); #if CONFIG_COVERAGE - coverage_exit(); + coverage_exit(); #endif - /* Tear down the caching of the ROM. */ - if (disable_cache_rom) - disable_cache_rom(); + /* Tear down the caching of the ROM. */ + if (disable_cache_rom) + disable_cache_rom(); - post_code(POST_OS_RESUME); - acpi_jump_to_wakeup(wake_vec); - } + post_code(POST_OS_RESUME); + acpi_jump_to_wakeup(wake_vec); } /* This is to be filled by SB code - startup value what was found. */ diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 022a45f..306f7da 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -558,7 +558,7 @@ void acpi_save_gnvs(u32 gnvs_address); /* 0 = S0, 1 = S1 ...*/ extern u8 acpi_slp_type; -void suspend_resume(void); +void acpi_resume(void *wake_vec); void __attribute__((weak)) mainboard_suspend_resume(void); void *acpi_find_wakeup_vector(void); void *acpi_get_wakeup_rsdp(void); diff --git a/src/include/bootstate.h b/src/include/bootstate.h index cf1b7a7..16a6321 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -27,6 +27,7 @@ typedef enum { BS_DEV_ENABLE, BS_DEV_INIT, BS_POST_DEVICE, + BS_OS_RESUME_CHECK, BS_OS_RESUME, BS_WRITE_TABLES, BS_PAYLOAD_LOAD, diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 94eeb89..47a482e 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -53,6 +53,7 @@ static boot_state_t bs_dev_resources(void *arg); static boot_state_t bs_dev_eanble(void *arg); static boot_state_t bs_dev_init(void *arg); static boot_state_t bs_post_device(void *arg); +static boot_state_t bs_os_resume_check(void *arg); static boot_state_t bs_os_resume(void *arg); static boot_state_t bs_write_tables(void *arg); static boot_state_t bs_payload_load(void *arg); @@ -87,6 +88,7 @@ static struct boot_state boot_states[] = { BS_INIT_ENTRY(BS_DEV_ENABLE, bs_dev_eanble), BS_INIT_ENTRY(BS_DEV_INIT, bs_dev_init), BS_INIT_ENTRY(BS_POST_DEVICE, bs_post_device), + BS_INIT_ENTRY(BS_OS_RESUME_CHECK, bs_os_resume_check), BS_INIT_ENTRY(BS_OS_RESUME, bs_os_resume), BS_INIT_ENTRY(BS_WRITE_TABLES, bs_write_tables), BS_INIT_ENTRY(BS_PAYLOAD_LOAD, bs_payload_load), @@ -156,21 +158,35 @@ static boot_state_t bs_post_device(void *arg) timestamp_sync(); - return BS_OS_RESUME; + return BS_OS_RESUME_CHECK; } -static boot_state_t bs_os_resume(void *arg) +static boot_state_t bs_os_resume_check(void *arg) { #if CONFIG_HAVE_ACPI_RESUME - suspend_resume(); + void *wake_vector; + + wake_vector = acpi_find_wakeup_vector(); + + if (wake_vector != NULL) { + boot_states[BS_OS_RESUME].arg = wake_vector; + return BS_OS_RESUME; + } post_code(0x8a); #endif - timestamp_add_now(TS_CBMEM_POST); return BS_WRITE_TABLES; } +static boot_state_t bs_os_resume(void *wake_vector) +{ +#if CONFIG_HAVE_ACPI_RESUME + acpi_resume(wake_vector); +#endif + return BS_WRITE_TABLES; +} + static boot_state_t bs_write_tables(void *arg) { if (cbmem_post_handling)

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New patch to review for coreboot: 7906f4a coverage: use boot state callbacks
by Aaron Durbin 25 Apr '13

25 Apr '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3135 -gerrit commit 7906f4a57aba4390ff28fc9df260d50976dad986 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 24 16:28:52 2013 -0500 coverage: use boot state callbacks Utilize the static boot state callback scheduling to initialize and tear down the coverage infrastructure at the appropriate points. The coverage initialization is performed at BS_PRE_DEVICE which is the earliest point a callback can be called. The tear down occurs at the 2 exit points of ramstage: OS resume and payload boot. Change-Id: Ie5ee51268e1f473f98fa517710a266e38dc01b6d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/boot/acpi.c | 4 ---- src/include/coverage.h | 21 --------------------- src/lib/gcov-glue.c | 12 ++++++++---- src/lib/hardwaremain.c | 5 ----- src/lib/selfboot.c | 4 ---- 5 files changed, 8 insertions(+), 38 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 1c373ac..a3bf718 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -36,7 +36,6 @@ #if CONFIG_COLLECT_TIMESTAMPS #include <timestamp.h> #endif -#include <coverage.h> /* FIXME: Kconfig doesn't support overridable defaults :-( */ #ifndef CONFIG_HPET_MIN_TICKS @@ -638,9 +637,6 @@ void acpi_resume(void *wake_vec) /* Call mainboard resume handler first, if defined. */ if (mainboard_suspend_resume) mainboard_suspend_resume(); -#if CONFIG_COVERAGE - coverage_exit(); -#endif /* Tear down the caching of the ROM. */ if (disable_cache_rom) disable_cache_rom(); diff --git a/src/include/coverage.h b/src/include/coverage.h deleted file mode 100644 index e1c50c5..0000000 --- a/src/include/coverage.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA - */ - -void coverage_init(void); -void coverage_exit(void); diff --git a/src/lib/gcov-glue.c b/src/lib/gcov-glue.c index 4e2b290..ab9062b 100644 --- a/src/lib/gcov-glue.c +++ b/src/lib/gcov-glue.c @@ -18,8 +18,8 @@ */ #include <stdint.h> +#include <bootstate.h> #include <cbmem.h> -#include <coverage.h> typedef struct file { uint32_t magic; @@ -128,7 +128,7 @@ static void setbuf(FILE *stream, char *buf) gcc_assert(buf == 0); } -void coverage_init(void) +static void coverage_init(void *unused) { extern long __CTOR_LIST__; typedef void (*func_ptr)(void) ; @@ -142,7 +142,7 @@ void coverage_init(void) } void __gcov_flush(void); -void coverage_exit(void) +static void coverage_exit(void *unused) { #if CONFIG_DEBUG_COVERAGE printk(BIOS_DEBUG, "Syncing coverage data.\n"); @@ -150,4 +150,8 @@ void coverage_exit(void) __gcov_flush(); } - +BOOT_STATE_INIT_ENTRIES(gcov_bscb) = { + BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, coverage_init, NULL), + BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, coverage_exit, NULL), + BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, coverage_exit, NULL), +}; diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 47a482e..2c6b726 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -41,7 +41,6 @@ it with the version available from LANL. #include <arch/acpi.h> #endif #include <cbmem.h> -#include <coverage.h> #include <timestamp.h> #define BS_DEBUG_LVL BIOS_NEVER @@ -324,10 +323,6 @@ void hardwaremain(int boot_complete) timestamp_stash(TS_START_RAMSTAGE); post_code(POST_ENTRY_RAMSTAGE); -#if CONFIG_COVERAGE - coverage_init(); -#endif - /* console_init() MUST PRECEDE ALL printk()! */ console_init(); diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index be03b85..934c131 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -33,7 +33,6 @@ #if CONFIG_COLLECT_TIMESTAMPS #include <timestamp.h> #endif -#include <coverage.h> /* Maximum physical address we can use for the coreboot bounce buffer. */ #ifndef MAX_ADDR @@ -537,9 +536,6 @@ int selfboot(struct lb_memory *mem, struct cbfs_payload *payload) #if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_SELFBOOT_JUMP); #endif -#if CONFIG_COVERAGE - coverage_exit(); -#endif /* Tear down the caching of the ROM. */ if (disable_cache_rom)

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New patch to review for coreboot: 9c184c6 cbmem: use boot state machine
by Aaron Durbin 25 Apr '13

25 Apr '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3136 -gerrit commit 9c184c6c8945f70f6c5a9d0981084b504b3ecc04 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 24 16:39:08 2013 -0500 cbmem: use boot state machine There were previously 2 functions, init_cbmem_pre_device() and init_cbmem_post_device(), where the 2 cbmem implementations implemented one or the other. These 2 functions are no longer needed to be called in the boot flow once the boot state callbacks are utilized. Change-Id: Ida71f1187bdcc640ae600705ddb3517e1410a80d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/cbmem.h | 5 ----- src/lib/cbmem.c | 12 +++++++----- src/lib/dynamic_cbmem.c | 8 ++++++-- src/lib/hardwaremain.c | 3 --- 4 files changed, 13 insertions(+), 15 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 219dbfc..ca2c50b 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -161,11 +161,6 @@ void cbmem_list(void); void cbmem_arch_init(void); void __attribute__((weak)) cbmem_post_handling(void); void cbmem_print_entry(int n, u32 id, u64 start, u64 size); -/* The pre|post device cbmem initialization functions are for the - * ramstage main to call. When cbmem is actually initialized depends on - * the cbmem implementation. */ -void init_cbmem_pre_device(void); -void init_cbmem_post_device(void); #else static inline void cbmem_arch_init(void) {} #endif /* __PRE_RAM__ */ diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index ad98082..e8200b6 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -19,6 +19,7 @@ #include <types.h> #include <string.h> +#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) @@ -232,11 +233,7 @@ int cbmem_initialize(void) #endif #ifndef __PRE_RAM__ -/* cbmem cannot be initialized before device drivers, but it can be initialized - * after the drivers have run. */ -void init_cbmem_pre_device(void) {} - -void init_cbmem_post_device(void) +static void init_cbmem_post_device(void *unused) { cbmem_initialize(); #if CONFIG_CONSOLE_CBMEM @@ -244,6 +241,11 @@ void init_cbmem_post_device(void) #endif } +BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { + BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, + init_cbmem_post_device, NULL), +}; + void cbmem_list(void) { struct cbmem_entry *cbmem_toc; diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index ae6c87a..5c269a0 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <bootstate.h> #include <boot/tables.h> #include <console/console.h> #include <cbmem.h> @@ -411,7 +412,7 @@ void *cbmem_entry_start(const struct cbmem_entry *entry) /* selected cbmem can be initialized early in ramstage. Additionally, that * means cbmem console can be reinitialized early as well. The post_device * function is empty since cbmem was initialized early in ramstage. */ -void init_cbmem_pre_device(void) +static void init_cbmem_pre_device(void *unused) { cbmem_initialize(); #if CONFIG_CONSOLE_CBMEM @@ -419,7 +420,10 @@ void init_cbmem_pre_device(void) #endif /* CONFIG_CONSOLE_CBMEM */ } -void init_cbmem_post_device(void) {} +BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { + BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, + init_cbmem_pre_device, NULL), +}; void cbmem_add_lb_mem(struct lb_memory *mem) { diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 2c6b726..7f5d27f 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -96,7 +96,6 @@ static struct boot_state boot_states[] = { static boot_state_t bs_pre_device(void *arg) { - init_cbmem_pre_device(); return BS_DEV_INIT_CHIPS; } @@ -153,8 +152,6 @@ static boot_state_t bs_post_device(void *arg) { timestamp_stash(TS_DEVICE_DONE); - init_cbmem_post_device(); - timestamp_sync(); return BS_OS_RESUME_CHECK;

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New patch to review for coreboot: 5adaf52 boot state: schedule static callbacks
by Aaron Durbin 25 Apr '13

25 Apr '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3133 -gerrit commit 5adaf520dfe4fd904ec0d06ff61b0577b9bf2b75 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 24 16:12:52 2013 -0500 boot state: schedule static callbacks Many of the boot state callbacks can be scheduled at compile time. Therefore, provide a way for a compilation unit to inform the boot state machine when its callbacks should be called. Each C module can export the callbacks and their scheduling requirements without changing the shared boot flow code. Change-Id: Ibc4cea4bd5ad45b2149c2d4aa91cbea652ed93ed Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/armv7/coreboot_ram.ld | 3 +++ src/arch/x86/coreboot_ram.ld | 3 +++ src/include/bootstate.h | 21 +++++++++++++++++++++ src/lib/hardwaremain.c | 20 ++++++++++++++++++++ src/lib/rmodule.ld | 4 ++++ 5 files changed, 51 insertions(+) diff --git a/src/arch/armv7/coreboot_ram.ld b/src/arch/armv7/coreboot_ram.ld index c2ead7a..487f610 100644 --- a/src/arch/armv7/coreboot_ram.ld +++ b/src/arch/armv7/coreboot_ram.ld @@ -61,6 +61,9 @@ SECTIONS cpu_drivers = . ; *(.rodata.cpu_driver) ecpu_drivers = . ; + _bs_init_begin = .; + *(.bs_init) + _bs_init_end = .; *(.rodata) *(.rodata.*) /* kevinh/Ispiri - Added an align, because the objcopy tool diff --git a/src/arch/x86/coreboot_ram.ld b/src/arch/x86/coreboot_ram.ld index 2dd51d5..ea32837 100644 --- a/src/arch/x86/coreboot_ram.ld +++ b/src/arch/x86/coreboot_ram.ld @@ -64,6 +64,9 @@ SECTIONS cpu_drivers = . ; *(.rodata.cpu_driver) ecpu_drivers = . ; + _bs_init_begin = .; + *(.bs_init) + _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 93dd36e..cf1b7a7 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -63,4 +63,25 @@ int boot_state_on_exit(struct boot_state_callback *bscb, boot_state_t state); /* Entry into the boot state machine. */ void hardwaremain(int boot_complete); +/* In order to schedule boot state callbacks at compile-time specify the + * entries in an array using the BOOT_STATE_INIT_ENTRIES and + * BOOT_STATE_INIT_ENTRY macros below. */ +struct boot_state_init_entry { + boot_state_t state; + boot_state_sequence_t when; + struct boot_state_callback bscb; +}; + +#define BOOT_STATE_INIT_ATTR __attribute__ ((section (".bs_init"))) + +#define BOOT_STATE_INIT_ENTRIES(name_) \ + struct boot_state_init_entry name_[] BOOT_STATE_INIT_ATTR + +#define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \ + { \ + .state = state_, \ + .when = when_, \ + .bscb = BOOT_STATE_CALLBACK_INIT(func_, arg_), \ + } + #endif /* BOOTSTATE_H */ diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index f458b23..94eeb89 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -286,6 +286,23 @@ int boot_state_on_exit(struct boot_state_callback *bscb, boot_state_t state_id) return boot_state_sched_callback(state, bscb, BS_ON_EXIT); } +static void boot_state_schedule_static_entries(void) +{ + extern struct boot_state_init_entry _bs_init_begin; + extern struct boot_state_init_entry _bs_init_end; + struct boot_state_init_entry *cur; + + cur = &_bs_init_begin; + + while (cur != &_bs_init_end) { + if (cur->when == BS_ON_ENTRY) + boot_state_on_entry(&cur->bscb, cur->state); + else + boot_state_on_exit(&cur->bscb, cur->state); + cur++; + } +} + void hardwaremain(int boot_complete) { timestamp_stash(TS_START_RAMSTAGE); @@ -311,6 +328,9 @@ void hardwaremain(int boot_complete) hard_reset(); } + /* Schedule the static boot state entries. */ + boot_state_schedule_static_entries(); + /* FIXME: Is there a better way to handle this? */ init_timer(); diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index 41d6357..43c0718 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -61,6 +61,10 @@ SECTIONS cpu_drivers = . ; *(.rodata.cpu_driver) ecpu_drivers = . ; + _bs_init_begin = .; + *(.bs_init) + _bs_init_end = .; + . = ALIGN(4); *(.rodata);

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New patch to review for coreboot: a8f6606 cbfs: make searching for a file less verbose
by Aaron Durbin 25 Apr '13

25 Apr '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3131 -gerrit commit a8f660655a010ecc5ba251e19e91eb47ba76d65b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Apr 25 08:42:23 2013 -0500 cbfs: make searching for a file less verbose The cbfs core code would print out all unmatched file names when searching for a file. This contributes to a lot of unnecessary messages in the boot log. Change this message to a DEBUG one so that it will only be printed when CONFIG_DEBUG_CBFS is enabled. Change-Id: I1e46a4b21d80e5d2f9b511a163def7f5d4e0fb99 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/cbfs_core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 9732b82..1220d48 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -158,7 +158,8 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) media->close(media); return file_ptr; } else { - LOG(" (unmatched file @0x%x: %s)\n", offset, file_name); + DEBUG(" (unmatched file @0x%x: %s)\n", offset, + file_name); media->unmap(media, file_name); }

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New patch to review for coreboot: c860d7b ramstage: introduce boot state machine
by Aaron Durbin 25 Apr '13

25 Apr '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3132 -gerrit commit c860d7b4584dd9989282de1f861eae567c130d66 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 24 15:14:01 2013 -0500 ramstage: introduce boot state machine The boot flow currently has a fixed ordering. The ordering is dictated by the device tree and on x86 the PCI device ordering for when actions are performed. Many of the new machines and configurations have dependencies that do not follow the device ordering. In order to be more flexible the concept of a boot state machine is introduced. At the boundaries (entry and exit) of each state there is opportunity to run callbacks. This ability allows one to schedule actions to be performed without adding board-specific code to the shared boot flow. Change-Id: I757f406c97445f6d9b69c003bb9610b16b132aa6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/bootstate.h | 66 ++++++++++++ src/lib/hardwaremain.c | 259 ++++++++++++++++++++++++++++++++++++++++-------- 2 files changed, 282 insertions(+), 43 deletions(-) diff --git a/src/include/bootstate.h b/src/include/bootstate.h new file mode 100644 index 0000000..93dd36e --- /dev/null +++ b/src/include/bootstate.h @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef BOOTSTATE_H +#define BOOTSTATE_H + +typedef enum { + BS_PRE_DEVICE, + BS_DEV_INIT_CHIPS, + BS_DEV_ENUMERATE, + BS_DEV_RESOURCES, + BS_DEV_ENABLE, + BS_DEV_INIT, + BS_POST_DEVICE, + BS_OS_RESUME, + BS_WRITE_TABLES, + BS_PAYLOAD_LOAD, + BS_PAYLOAD_BOOT, +} boot_state_t; + +typedef enum { + BS_ON_ENTRY, + BS_ON_EXIT +} boot_state_sequence_t; + +struct boot_state_callback { + void *arg; + void (*callback)(void *arg); + /* For use internal to the boot state machine. */ + struct boot_state_callback *next; +}; + +#define BOOT_STATE_CALLBACK_INIT(func_, arg_) \ + { \ + .arg = arg_, \ + .callback = func_, \ + .next = NULL, \ + } +#define BOOT_STATE_CALLBACK(name_, func_, arg_) \ + struct boot_state_callback name_ = BOOT_STATE_CALLBACK_INIT(func_, arg_) + +/* The following 2 functions schedule a callback to be called on entry/exit + * to a given state. Note that thare are no ordering guarantees between the + * individual callbacks. 0 is returned on success < 0 on error. */ +int boot_state_on_entry(struct boot_state_callback *bscb, boot_state_t state); +int boot_state_on_exit(struct boot_state_callback *bscb, boot_state_t state); + +/* Entry into the boot state machine. */ +void hardwaremain(int boot_complete); + +#endif /* BOOTSTATE_H */ diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index a3ee10b..f458b23 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -25,6 +25,7 @@ it with the version available from LANL. * C Bootstrap code for the coreboot */ +#include <bootstate.h> #include <console/console.h> #include <version.h> #include <device/device.h> @@ -43,80 +44,123 @@ it with the version available from LANL. #include <coverage.h> #include <timestamp.h> -/** - * @brief Main function of the RAM part of coreboot. - * - * Coreboot is divided into Pre-RAM part and RAM part. - * - * Device Enumeration: - * In the dev_enumerate() phase, - */ - -void hardwaremain(int boot_complete); - -void hardwaremain(int boot_complete) -{ - struct lb_memory *lb_mem; - void *payload; - - timestamp_stash(TS_START_RAMSTAGE); - post_code(POST_ENTRY_RAMSTAGE); - -#if CONFIG_COVERAGE - coverage_init(); -#endif - - /* console_init() MUST PRECEDE ALL printk()! */ - console_init(); - - post_code(POST_CONSOLE_READY); - - printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n", - coreboot_version, coreboot_extra_version, coreboot_build, - (boot_complete)?"rebooting":"booting"); - - post_code(POST_CONSOLE_BOOT_MSG); - - /* If we have already booted attempt a hard reboot */ - if (boot_complete) { - hard_reset(); +#define BS_DEBUG_LVL BIOS_NEVER + +static boot_state_t bs_pre_device(void *arg); +static boot_state_t bs_dev_init_chips(void *arg); +static boot_state_t bs_dev_enumerate(void *arg); +static boot_state_t bs_dev_resources(void *arg); +static boot_state_t bs_dev_eanble(void *arg); +static boot_state_t bs_dev_init(void *arg); +static boot_state_t bs_post_device(void *arg); +static boot_state_t bs_os_resume(void *arg); +static boot_state_t bs_write_tables(void *arg); +static boot_state_t bs_payload_load(void *arg); +static boot_state_t bs_payload_boot(void *arg); + +struct boot_state { + const char *name; + boot_state_t id; + struct boot_state_callback *seq_callbacks[2]; + boot_state_t (*run_state)(void *arg); + void *arg; + int complete; +}; + +#define BS_INIT(state_, run_func_) \ + { \ + .name = #state_, \ + .id = state_, \ + .seq_callbacks = { NULL, NULL },\ + .run_state = run_func_, \ + .arg = NULL, \ + .complete = 0 \ } - - /* FIXME: Is there a better way to handle this? */ - init_timer(); - +#define BS_INIT_ENTRY(state_, run_func_) \ + [state_] = BS_INIT(state_, run_func_) + +static struct boot_state boot_states[] = { + BS_INIT_ENTRY(BS_PRE_DEVICE, bs_pre_device), + BS_INIT_ENTRY(BS_DEV_INIT_CHIPS, bs_dev_init_chips), + BS_INIT_ENTRY(BS_DEV_ENUMERATE, bs_dev_enumerate), + BS_INIT_ENTRY(BS_DEV_RESOURCES, bs_dev_resources), + BS_INIT_ENTRY(BS_DEV_ENABLE, bs_dev_eanble), + BS_INIT_ENTRY(BS_DEV_INIT, bs_dev_init), + BS_INIT_ENTRY(BS_POST_DEVICE, bs_post_device), + BS_INIT_ENTRY(BS_OS_RESUME, bs_os_resume), + BS_INIT_ENTRY(BS_WRITE_TABLES, bs_write_tables), + BS_INIT_ENTRY(BS_PAYLOAD_LOAD, bs_payload_load), + BS_INIT_ENTRY(BS_PAYLOAD_BOOT, bs_payload_boot), +}; + +static boot_state_t bs_pre_device(void *arg) +{ init_cbmem_pre_device(); + return BS_DEV_INIT_CHIPS; +} +static boot_state_t bs_dev_init_chips(void *arg) +{ timestamp_stash(TS_DEVICE_ENUMERATE); /* Initialize chips early, they might disable unused devices. */ dev_initialize_chips(); + return BS_DEV_ENUMERATE; +} + +static boot_state_t bs_dev_enumerate(void *arg) +{ /* Find the devices we don't have hard coded knowledge about. */ dev_enumerate(); post_code(POST_DEVICE_ENUMERATION_COMPLETE); + return BS_DEV_RESOURCES; +} + +static boot_state_t bs_dev_resources(void *arg) +{ timestamp_stash(TS_DEVICE_CONFIGURE); /* Now compute and assign the bus resources. */ dev_configure(); post_code(POST_DEVICE_CONFIGURATION_COMPLETE); + return BS_DEV_ENABLE; +} + +static boot_state_t bs_dev_eanble(void *arg) +{ timestamp_stash(TS_DEVICE_ENABLE); /* Now actually enable devices on the bus */ dev_enable(); post_code(POST_DEVICES_ENABLED); + return BS_DEV_INIT; +} + +static boot_state_t bs_dev_init(void *arg) +{ timestamp_stash(TS_DEVICE_INITIALIZE); /* And of course initialize devices on the bus */ dev_initialize(); post_code(POST_DEVICES_INITIALIZED); + return BS_POST_DEVICE; +} + +static boot_state_t bs_post_device(void *arg) +{ timestamp_stash(TS_DEVICE_DONE); init_cbmem_post_device(); timestamp_sync(); + return BS_OS_RESUME; +} + +static boot_state_t bs_os_resume(void *arg) +{ #if CONFIG_HAVE_ACPI_RESUME suspend_resume(); post_code(0x8a); @@ -124,6 +168,11 @@ void hardwaremain(int boot_complete) timestamp_add_now(TS_CBMEM_POST); + return BS_WRITE_TABLES; +} + +static boot_state_t bs_write_tables(void *arg) +{ if (cbmem_post_handling) cbmem_post_handling(); @@ -132,7 +181,14 @@ void hardwaremain(int boot_complete) /* Now that we have collected all of our information * write our configuration tables. */ - lb_mem = write_tables(); + write_tables(); + + return BS_PAYLOAD_LOAD; +} + +static boot_state_t bs_payload_load(void *arg) +{ + void *payload; timestamp_add_now(TS_LOAD_PAYLOAD); @@ -141,7 +197,124 @@ void hardwaremain(int boot_complete) if (! payload) die("Could not find a payload\n"); - selfboot(lb_mem, payload); + /* Pass the payload to the next state. */ + boot_states[BS_PAYLOAD_BOOT].arg = payload; + + return BS_PAYLOAD_BOOT; +} + +static boot_state_t bs_payload_boot(void *payload) +{ + selfboot(get_lb_mem(), payload); + printk(BIOS_EMERG, "Boot failed"); + /* Returning from this state will fail because the following signals + * return to a completed state. */ + return BS_PAYLOAD_BOOT; +} + +static void bs_call_callbacks(struct boot_state *state, + boot_state_sequence_t seq) +{ + while (state->seq_callbacks[seq] != NULL) { + struct boot_state_callback *bscb; + + /* Remove the first callback. */ + bscb = state->seq_callbacks[seq]; + state->seq_callbacks[seq] = bscb->next; + bscb->next = NULL; + + bscb->callback(bscb->arg); + } +} + +static void bs_walk_state_machine(boot_state_t current_state_id) +{ + + while (1) { + struct boot_state *state; + + state = &boot_states[current_state_id]; + + if (state->complete) { + printk(BIOS_EMERG, "BS: %s state already executed.\n", + state->name); + break; + } + + printk(BS_DEBUG_LVL, "BS: Entering %s state.\n", state->name); + bs_call_callbacks(state, BS_ON_ENTRY); + + current_state_id = state->run_state(state->arg); + + printk(BS_DEBUG_LVL, "BS: Exiting %s state.\n", state->name); + bs_call_callbacks(state, BS_ON_EXIT); + + state->complete = 1; + } +} + +static int boot_state_sched_callback(struct boot_state *state, + struct boot_state_callback *bscb, + boot_state_sequence_t seq) +{ + if (state->complete) { + printk(BIOS_WARNING, + "Tried to schedule callback on completed state %s.\n", + state->name); + + return -1; + } + + bscb->next = state->seq_callbacks[seq]; + state->seq_callbacks[seq] = bscb; + + return 0; +} + +int boot_state_on_entry(struct boot_state_callback *bscb, boot_state_t state_id) +{ + struct boot_state *state = &boot_states[state_id]; + + return boot_state_sched_callback(state, bscb, BS_ON_ENTRY); +} + +int boot_state_on_exit(struct boot_state_callback *bscb, boot_state_t state_id) +{ + struct boot_state *state = &boot_states[state_id]; + + return boot_state_sched_callback(state, bscb, BS_ON_EXIT); +} + +void hardwaremain(int boot_complete) +{ + timestamp_stash(TS_START_RAMSTAGE); + post_code(POST_ENTRY_RAMSTAGE); + +#if CONFIG_COVERAGE + coverage_init(); +#endif + + /* console_init() MUST PRECEDE ALL printk()! */ + console_init(); + + post_code(POST_CONSOLE_READY); + + printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n", + coreboot_version, coreboot_extra_version, coreboot_build, + (boot_complete)?"rebooting":"booting"); + + post_code(POST_CONSOLE_BOOT_MSG); + + /* If we have already booted attempt a hard reboot */ + if (boot_complete) { + hard_reset(); + } + + /* FIXME: Is there a better way to handle this? */ + init_timer(); + + bs_walk_state_machine(BS_PRE_DEVICE); + die("Boot state machine failure.\n"); }

1 0

Patch set updated for coreboot: e15c7ea Google/Snow: Enable suspend/resume.
by Hung-Te Lin 25 Apr '13

25 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3102 -gerrit commit e15c7ea444609890a84c4c5680b284efbdf504c5 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Apr 25 19:49:40 2013 +0800 Google/Snow: Enable suspend/resume. Add the suspend/resume feature into bootblock and romstage. Note, resuming with X and touchpad driver may be still unstable. Verified by building and booting successfully on Google/Snow, and then executing the "suspend_stress_test" in text mode ("stop ui; suspend_stress_test") in Chromium OS, passed at least 20 iterations. Change-Id: I65681c42eeef2736e55bb906595f42a5b1dfdf11 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/mainboard/google/snow/bootblock.c | 17 ++++++++++++----- src/mainboard/google/snow/romstage.c | 13 ++++++++++--- 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index d2e0b50..d6411b5 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -25,16 +25,23 @@ #include <console/console.h> #include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/pinmux.h> +#include "mainboard.h" void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { - /* kick off the microsecond timer. We want to do this as early - * as we can. - */ - timer_start(); + switch (board_get_wakeup_state()) { + case BOARD_WAKEUP_DIRECT: + board_wakeup(); + break; - exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); + case BOARD_IS_NOT_WAKEUP: + /* kick off the microsecond timer. + * We want to do this as early as we can. + */ + timer_start(); + break; + } #if CONFIG_EARLY_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); console_init(); diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index c067629..3eff129 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -170,15 +170,22 @@ void main(void) { struct mem_timings *mem; void *entry; + int is_resume = (board_get_wakeup_state() != BOARD_IS_NOT_WAKEUP); /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ mem = board_setup_clock(); - console_init(); - board_setup_power(); + if (!is_resume) { + console_init(); + board_setup_power(); + } + + board_setup_memory(mem, is_resume); - board_setup_memory(mem, 0); + if (is_resume) { + board_wakeup(); + } board_setup_storage(); board_setup_gpio();

1 0

Patch set updated for coreboot: d532d5b google/snow: Revise romstage initialization code.
by Hung-Te Lin 25 Apr '13

25 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3130 -gerrit commit d532d5be7a74626c16f3d57be5b89fdc4c761124 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Apr 25 19:30:19 2013 +0800 google/snow: Revise romstage initialization code. Move board setup procedure to board_setup_* functions, with better function names and comments. Verified by successfully building and booting on Google/Snow. Change-Id: I2942d75064135093eeb1c1da188a005fd255111d Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/mainboard/google/snow/romstage.c | 92 ++++++++++++++++++------------------ 1 file changed, 47 insertions(+), 45 deletions(-) diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 6e312fa..c067629 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -46,10 +46,16 @@ #define PMIC_BUS 0 #define MMC0_GPIO_PIN (58) -static int setup_pmic(void) +static void board_setup_power(void) { int error = 0; + power_init(); + + /* Initialize I2C bus to configure PMIC. */ + i2c_init(0, CONFIG_SYS_I2C_SPEED, 0x00); + + printk(BIOS_DEBUG, "%s: Setting up PMIC...\n", __func__); /* * We're using CR1616 coin cell battery that is non-rechargeable * battery. But, BBCHOSTEN bit of the BBAT Charger Register in @@ -81,19 +87,19 @@ static int setup_pmic(void) error |= max77686_enable_32khz_cp(PMIC_BUS); - if (error) - printk(BIOS_CRIT, "%s: Error during PMIC setup\n", __func__); - - return error; + if (error) { + printk(BIOS_CRIT, "%s: PMIC error: %#x\n", __func__, error); + die("Failed to intialize PMIC.\n"); + } } -static void initialize_s5p_mshc(void) +static void board_setup_storage(void) { /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ if (clock_set_mshci(PERIPH_ID_SDMMC0)) - printk(BIOS_CRIT, "Failed to set clock for SDMMC0.\n"); + printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__); if (gpio_direction_output(MMC0_GPIO_PIN, 1)) { - printk(BIOS_CRIT, "Unable to power on SDMMC0.\n"); + printk(BIOS_CRIT, "%s: Unable to power on MMC0.\n", __func__); } gpio_set_pull(MMC0_GPIO_PIN, EXYNOS_GPIO_PULL_NONE); gpio_set_drv(MMC0_GPIO_PIN, EXYNOS_GPIO_DRV_4X); @@ -104,12 +110,12 @@ static void initialize_s5p_mshc(void) exynos_pinmux_config(PERIPH_ID_SDMMC2, 0); } -static void graphics(void) +static void board_setup_graphics(void) { exynos_pinmux_config(PERIPH_ID_DPHPD, 0); } -static void chromeos_gpios(void) +static void board_setup_gpio(void) { struct exynos5_gpio_part1 *gpio_pt1; struct exynos5_gpio_part2 *gpio_pt2; @@ -137,53 +143,49 @@ static void chromeos_gpios(void) s5p_gpio_set_pull(&gpio_pt2->x1, POWER_GPIO, EXYNOS_GPIO_PULL_NONE); } +static void board_setup_memory(struct mem_timings *mem, int is_resume) +{ + printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n", + mem->mem_manuf, + mem->mem_type, + mem->mpll_mdiv, + mem->frequency_mhz); + if (ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, !is_resume)) { + die("Failed to initialize memory controller.\n"); + } +} + +static struct mem_timings *board_setup_clock(void) +{ + struct mem_timings *mem = get_mem_timings(); + struct arm_clk_ratios *arm_ratios = get_arm_clk_ratios(); + if (!mem) { + die("Unable to auto-detect memory timings\n"); + } + system_clock_init(mem, arm_ratios); + return mem; +} + void main(void) { struct mem_timings *mem; - struct arm_clk_ratios *arm_ratios; - int ret; void *entry; - clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ - /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ - mem = get_mem_timings(); - arm_ratios = get_arm_clk_ratios(); - system_clock_init(mem, arm_ratios); + mem = board_setup_clock(); console_init(); + board_setup_power(); - i2c_init(0, CONFIG_SYS_I2C_SPEED, 0x00); - if (power_init()) - power_shutdown(); - printk(BIOS_DEBUG, "%s: setting up pmic...\n", __func__); - if (setup_pmic()) - power_shutdown(); - - if (!mem) { - printk(BIOS_CRIT, "Unable to auto-detect memory timings\n"); - while(1); - } - printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n", - mem->mem_manuf, - mem->mem_type, - mem->mpll_mdiv, - mem->frequency_mhz); - - ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, 1); - if (ret) { - printk(BIOS_ERR, "Memory controller init failed, err: %x\n", - ret); - while(1); - } - - initialize_s5p_mshc(); - - chromeos_gpios(); + board_setup_memory(mem, 0); - graphics(); + board_setup_storage(); + board_setup_gpio(); + board_setup_graphics(); + /* Set SPI (primary CBFS media) clock to 50MHz. */ + clock_set_rate(PERIPH_ID_SPI1, 50000000); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);

1 0

Patch set updated for coreboot: c89d526 google/snow: Add "wakeup" module for suspend/resume.
by Hung-Te Lin 25 Apr '13

25 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3129 -gerrit commit c89d5265659b9a4a1799d38eab864984237a40d2 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Apr 25 17:38:55 2013 +0800 google/snow: Add "wakeup" module for suspend/resume. The "wakeup" procedure will be shared by bootblock and romstage for different types of resume processes. Note, this commit does not include changes in romstage/bootblock to enable suspend/resume feature. Simply adding functions to handle suspend/resume. Verified by successfully building and booting Google/Snow firmware image. Change-Id: I17a256afb99f2f8b5e0eac3393cdf6959b239341 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/cpu/samsung/exynos5250/Makefile.inc | 2 +- src/mainboard/google/snow/Makefile.inc | 3 ++ src/mainboard/google/snow/mainboard.h | 11 ++++++ src/mainboard/google/snow/romstage.c | 13 ------- src/mainboard/google/snow/wakeup.c | 62 +++++++++++++++++++++++++++++++++ 5 files changed, 77 insertions(+), 14 deletions(-) diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 8788a6c..25d1bc5 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -3,7 +3,7 @@ # image outside of CBFS #INTERMEDIATE += exynos5250_add_bl1 -bootblock-y += pinmux.c mct.c +bootblock-y += pinmux.c mct.c power.c # Clock is required for UART bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc index 46e366f..84a8c05 100644 --- a/src/mainboard/google/snow/Makefile.inc +++ b/src/mainboard/google/snow/Makefile.inc @@ -17,9 +17,12 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +bootblock-y += wakeup.c + romstage-y += mainboard.c romstage-y += memory.c romstage-y += romstage.c +romstage-y += wakeup.c # ramstage-y += ec.c ramstage-y += ramstage.c diff --git a/src/mainboard/google/snow/mainboard.h b/src/mainboard/google/snow/mainboard.h index 6fe371f..63a2c18 100644 --- a/src/mainboard/google/snow/mainboard.h +++ b/src/mainboard/google/snow/mainboard.h @@ -35,4 +35,15 @@ enum snow_board_config { int board_get_config(void); +enum { + BOARD_IS_NOT_WAKEUP, // A normal boot (not suspend/resume). + BOARD_WAKEUP_DIRECT, // A wake up event that can be resumed any time. + BOARD_WAKEUP_NEED_CLOCK_RESET, // A wake up event that must be resumed + // only after clock and memory + // controllers are re-initialized. +}; + +int board_get_wakeup_state(void); +void board_wakeup(void); + #endif /* MAINBOARD_H */ diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index edbe009..6e312fa 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -46,19 +46,6 @@ #define PMIC_BUS 0 #define MMC0_GPIO_PIN (58) -#if 0 -static int board_wakeup_permitted(void) -{ - const int gpio = GPIO_Y10; - int is_bad_wake; - - /* We're a bad wakeup if the gpio was defined and was high */ - is_bad_wake = ((gpio != -1) && gpio_get_value(gpio)); - - return !is_bad_wake; -} -#endif - static int setup_pmic(void) { int error = 0; diff --git a/src/mainboard/google/snow/wakeup.c b/src/mainboard/google/snow/wakeup.c new file mode 100644 index 0000000..33ea9d8 --- /dev/null +++ b/src/mainboard/google/snow/wakeup.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/gpio.h> +#include <arch/hlt.h> +#include <console/console.h> +#include <cpu/samsung/exynos5250/gpio.h> +#include <cpu/samsung/exynos5250/power.h> +#include <cpu/samsung/exynos5-common/exynos5-common.h> + +#include "mainboard.h" + +static int wakeup_need_reset(void) +{ + /* The "wake up" event is not reliable (known as "bad wakeup") and needs + * reset if GPIO value is high. */ + return gpio_get_value(GPIO_Y10); +} + +void board_wakeup(void) +{ + if (wakeup_need_reset()) + power_reset(); + + power_init(); /* Ensure ps_hold_setup() for early wakeup. */ + power_exit_wakeup(); + /* Should never return. */ + die("Failed to wake up.\n"); +} + +int board_get_wakeup_state() +{ + uint32_t status = power_read_reset_status(); + + /* DIDLE/LPA can be resumed without clock reset (ex, bootblock), + * and SLEEP requires resetting clock (should be done in ROM stage). + */ + + if (status == S5P_CHECK_DIDLE || status == S5P_CHECK_LPA) + return BOARD_WAKEUP_DIRECT; + + if (status == S5P_CHECK_SLEEP) + return BOARD_WAKEUP_NEED_CLOCK_RESET; + + return BOARD_IS_NOT_WAKEUP; +}

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Patch set updated for coreboot: c121a4a arm/exynos: Allow DRAM controller to be initialized without clearing RAM content.
by Hung-Te Lin 25 Apr '13

25 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3128 -gerrit commit c121a4a316f5690f1b6f4631f0298366bc06ed74 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Apr 25 16:14:19 2013 +0800 arm/exynos: Allow DRAM controller to be initialized without clearing RAM content. To support suspend/resume, PHY control must be reset only on normal boot path. So add a new param "mem_reset" to specify that. Verified to boot successfully on Google/Snow. Change-Id: Id49bc6c6239cf71a67ba091092dd3ebf18e83e33 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/cpu/samsung/exynos5250/dmc_init_ddr3.c | 14 ++++++++++---- src/cpu/samsung/exynos5250/setup.h | 4 +++- src/mainboard/google/snow/romstage.c | 2 +- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c index 5bb8a37..132471d 100644 --- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c @@ -61,7 +61,8 @@ static void reset_phy_ctrl(void) udelay(500); } -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) +int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, + int mem_reset) { unsigned int val; struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl; @@ -71,9 +72,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE; phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE; dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE; - printk(BIOS_SPEW, "ddr3_mem_ctrl_init: reset phy: "); - reset_phy_ctrl(); - printk(BIOS_SPEW, "done\n"); + + if (mem_reset) { + printk(BIOS_SPEW, "%s: reset phy: ", __func__); + reset_phy_ctrl(); + printk(BIOS_SPEW, "done\n"); + } else { + printk(BIOS_SPEW, "%s: skip mem_reset.\n", __func__); + } /* Set Impedance Output Driver */ printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Set Impedance Output Driver\n"); diff --git a/src/cpu/samsung/exynos5250/setup.h b/src/cpu/samsung/exynos5250/setup.h index 4f7f58c..f205b4d 100644 --- a/src/cpu/samsung/exynos5250/setup.h +++ b/src/cpu/samsung/exynos5250/setup.h @@ -702,9 +702,11 @@ void mem_ctrl_init(void); * which the DMC uses to decide how to split a memory * chunk into smaller chunks to support concurrent * accesses; may vary across boards. + * @param mem_reset Reset memory during initialization. * @return 0 if ok, SETUP_ERR_... if there is a problem */ -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size); +int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, + int mem_reset); void tzpc_init(void); /* diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 41b88e1..edbe009 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -184,7 +184,7 @@ void main(void) mem->mpll_mdiv, mem->frequency_mhz); - ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE); + ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, 1); if (ret) { printk(BIOS_ERR, "Memory controller init failed, err: %x\n", ret);

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coreboot-gerrit April 2013