Patch set updated for coreboot: 8605a03 Intel 82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2

[Paul Menzel]

Paul Menzel ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3122

-gerrit

commit 8605a032dfb371952b96380ec94b424170c9917b
Author: Paul Menzel 
Date:   Tue Apr 23 13:00:34 2013 +0200

Intel 82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2

Commit »Support for the Intel ICH7 southbridge.« (debb11fc) [1] used
    `1 << 25` to set the I/O APIC ID of 2. Instead using `2 << 24`, which
    is the same value, makes it clear, that the I/O APIC ID is 2.

Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID
    is 2« (8c937c7e) [2] is used as a template.

[1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=debb11fc1fe5f556...
    [2] http://review.coreboot.org/3100

Change-Id: Ib688500944cd78a1cc1c8082bb138fa9468bdbfb
    Signed-off-by: Paul Menzel 
---
 src/southbridge/intel/i82801gx/lpc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 3a94e84..777a6d7 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -52,12 +52,12 @@ static void i82801gx_enable_apic(struct device *dev)
    pci_write_config8(dev, ACPI_CNTL, ACPI_EN);

*ioapic_index = 0;
-	*ioapic_data = (1 << 25);
+	*ioapic_data = (2 << 24);

*ioapic_index = 0;
    reg32 = *ioapic_data;
    printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
-	if (reg32 != (1 << 25))
+	if (reg32 != (2 << 24))
    	die("APIC Error\n");

printk(BIOS_SPEW, "Dumping IOAPIC registers\n");