Change in coreboot[master]: mb/google/volteer/variants/eldrid: disable Fan Performance Control an...
Nick Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy ......................................................................
mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy
add dptf option and disable fan relate control from overridetree.cb
BUG=b:167931578
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 69 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/1
diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 6e9d743..1aef702 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -58,7 +58,75 @@ }"
device domain 0 on - device pci 04.0 off end + device pci 04.0 on + # Default DPTF Policy for all Volteer boards if not overridden + chip drivers/intel/dptf + ## Active Policy + register "policies.active" = "{ + [0] = {.target = DPTF_CPU, + .thresholds = {TEMP_PCT(85, 90), + TEMP_PCT(80, 69), + TEMP_PCT(75, 56), + TEMP_PCT(70, 46), + TEMP_PCT(65, 36),}}, + [1] = {.target = DPTF_TEMP_SENSOR_0, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [2] = {.target = DPTF_TEMP_SENSOR_1, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [3] = {.target = DPTF_TEMP_SENSOR_2, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [4] = {.target = DPTF_TEMP_SENSOR_3, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}}" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" + + ## Power Limits Control + # 10-15W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is fixed at 64W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 15000, + .max_power = 60000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 }}" + + device generic 0 on end + end + end device pci 15.0 on chip drivers/i2c/generic register "hid" = ""10EC5682""
Nick Chen has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy ......................................................................
mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy
add dptf option and disable fan relate control from overridetree.cb
BUG=b:167931578
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 69 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/2
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#3).
Change subject: mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy ......................................................................
mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy
add dptf option and disable relate fan control from overridetree.cb
BUG=b:167931578
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 69 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/3
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#4).
Change subject: mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy ......................................................................
mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy
Enable dptf feature and remove fan control part from overridetree.cb
BUG=b:167931578
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 69 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/4
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#5).
Change subject: mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy ......................................................................
mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy
Enable dptf feature and remove fan control part from overridetree.cb
BUG=b:167931578
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 69 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/5
Nick Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy ......................................................................
Set Ready For Review
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy ......................................................................
Patch Set 5:
(5 comments)
https://review.coreboot.org/c/coreboot/+/45860/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/eldrid/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45860/5/src/mainboard/google/voltee... PS5, Line 67: TEMP_PCT(85, 90), : TEMP_PCT(80, 69), : TEMP_PCT(75, 56), : TEMP_PCT(70, 46), : TEMP_PCT(65, 36),}}, nit: line these up
https://review.coreboot.org/c/coreboot/+/45860/5/src/mainboard/google/voltee... PS5, Line 73: TEMP_PCT(50, 90), : TEMP_PCT(47, 69), : TEMP_PCT(45, 56), : TEMP_PCT(42, 46), : TEMP_PCT(39, 36),}} same
https://review.coreboot.org/c/coreboot/+/45860/5/src/mainboard/google/voltee... PS5, Line 79: TEMP_PCT(50, 90), : TEMP_PCT(47, 69), : TEMP_PCT(45, 56), : TEMP_PCT(42, 46), : TEMP_PCT(39, 36),}} same
https://review.coreboot.org/c/coreboot/+/45860/5/src/mainboard/google/voltee... PS5, Line 85: TEMP_PCT(50, 90), : TEMP_PCT(47, 69), : TEMP_PCT(45, 56), : TEMP_PCT(42, 46), : TEMP_PCT(39, 36),}}, same
https://review.coreboot.org/c/coreboot/+/45860/5/src/mainboard/google/voltee... PS5, Line 91: TEMP_PCT(50, 90), : TEMP_PCT(47, 69), : TEMP_PCT(45, 56), : TEMP_PCT(42, 46), : TEMP_PCT(39, 36),}}} same
Keith Short has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45860/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/eldrid/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45860/5/src/mainboard/google/voltee... PS5, Line 62: Default DPTF Policy for all Volteer boards if not overridden Should be "DPTF Policy for Eldrid board", or you can remove this comment completely.
Hello build bot (Jenkins), Tim Wawrzynczak, Keith Short, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#6).
Change subject: mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy ......................................................................
mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy
Enable dptf feature and remove fan control part from overridetree.cb
BUG=b:167931578
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 69 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/6
Hello build bot (Jenkins), Tim Wawrzynczak, Keith Short, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#7).
Change subject: mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy ......................................................................
mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy
Enable dptf feature and remove fan control part from overridetree.cb
BUG=b:167931578
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 69 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/7
Nick Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy ......................................................................
Patch Set 7:
(6 comments)
https://review.coreboot.org/c/coreboot/+/45860/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/eldrid/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45860/5/src/mainboard/google/voltee... PS5, Line 62: Default DPTF Policy for all Volteer boards if not overridden
Should be "DPTF Policy for Eldrid board", or you can remove this comment completely.
Done
https://review.coreboot.org/c/coreboot/+/45860/5/src/mainboard/google/voltee... PS5, Line 67: TEMP_PCT(85, 90), : TEMP_PCT(80, 69), : TEMP_PCT(75, 56), : TEMP_PCT(70, 46), : TEMP_PCT(65, 36),}},
nit: line these up
Done
https://review.coreboot.org/c/coreboot/+/45860/5/src/mainboard/google/voltee... PS5, Line 73: TEMP_PCT(50, 90), : TEMP_PCT(47, 69), : TEMP_PCT(45, 56), : TEMP_PCT(42, 46), : TEMP_PCT(39, 36),}}
same
Done
https://review.coreboot.org/c/coreboot/+/45860/5/src/mainboard/google/voltee... PS5, Line 79: TEMP_PCT(50, 90), : TEMP_PCT(47, 69), : TEMP_PCT(45, 56), : TEMP_PCT(42, 46), : TEMP_PCT(39, 36),}}
same
Done
https://review.coreboot.org/c/coreboot/+/45860/5/src/mainboard/google/voltee... PS5, Line 85: TEMP_PCT(50, 90), : TEMP_PCT(47, 69), : TEMP_PCT(45, 56), : TEMP_PCT(42, 46), : TEMP_PCT(39, 36),}},
same
Done
https://review.coreboot.org/c/coreboot/+/45860/5/src/mainboard/google/voltee... PS5, Line 91: TEMP_PCT(50, 90), : TEMP_PCT(47, 69), : TEMP_PCT(45, 56), : TEMP_PCT(42, 46), : TEMP_PCT(39, 36),}}}
same
Done
Keith Short has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy ......................................................................
Patch Set 7: Code-Review+1
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45860/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45860/7//COMMIT_MSG@7 PS7, Line 7: mb/google/volteer/variants/eldrid: disable Fan Performance Control : and Passive Policy Please keep subject line to 72 chars; I suggest: mb/google/volteer: Add a DPTF policy for Eldrid
https://review.coreboot.org/c/coreboot/+/45860/7/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/eldrid/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45860/7/src/mainboard/google/voltee... PS7, Line 61: device pci 04.0 on : # DPTF Policy for Eldrid board : chip drivers/intel/dptf : ## Active Policy : register "policies.active" = "{ : [0] = {.target = DPTF_CPU, : .thresholds = {TEMP_PCT(85, 90), : TEMP_PCT(80, 69), : TEMP_PCT(75, 56), : TEMP_PCT(70, 46), : TEMP_PCT(65, 36),}}, : [1] = {.target = DPTF_TEMP_SENSOR_0, : .thresholds = {TEMP_PCT(50, 90), : TEMP_PCT(47, 69), : TEMP_PCT(45, 56), : TEMP_PCT(42, 46), : TEMP_PCT(39, 36),}}, : [2] = {.target = DPTF_TEMP_SENSOR_1, : .thresholds = {TEMP_PCT(50, 90), : TEMP_PCT(47, 69), : TEMP_PCT(45, 56), : TEMP_PCT(42, 46), : TEMP_PCT(39, 36),}}, : [3] = {.target = DPTF_TEMP_SENSOR_2, : .thresholds = {TEMP_PCT(50, 90), : TEMP_PCT(47, 69), : TEMP_PCT(45, 56), : TEMP_PCT(42, 46), : TEMP_PCT(39, 36),}}, : [4] = {.target = DPTF_TEMP_SENSOR_3, : .thresholds = {TEMP_PCT(50, 90), : TEMP_PCT(47, 69), : TEMP_PCT(45, 56), : TEMP_PCT(42, 46), : TEMP_PCT(39, 36),}}}" : : ## Critical Policy : register "policies.critical" = "{ : [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), : [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), : [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), : [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), : [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" : : ## Power Limits Control : # 10-15W PL1 in 200mW increments, avg over 28-32s interval : # PL2 is fixed at 64W, avg over 28-32s interval : register "controls.power_limits" = "{ : .pl1 = {.min_power = 3000, : .max_power = 15000, : .time_window_min = 28 * MSECS_PER_SEC, : .time_window_max = 32 * MSECS_PER_SEC, : .granularity = 200,}, : .pl2 = {.min_power = 15000, : .max_power = 60000, : .time_window_min = 28 * MSECS_PER_SEC, : .time_window_max = 32 * MSECS_PER_SEC, : .granularity = 1000,}}" : : ## Charger Performance Control (Control, mA) : register "controls.charger_perf" = "{ : [0] = { 255, 1700 }, : [1] = { 24, 1500 }, : [2] = { 16, 1000 }, : [3] = { 8, 500 }}" : : device generic 0 on end : end : end I don't think this isn't doing what you're expecting here.
The variants all "inherit" the settings from the baseboard (on a per-register basis), so if you want to disable fan control & passive policy, you would have to do something like this:
``` device pci 04.0 on # DPTF Policy for Eldrid board chip drivers/intel/dptf # Disable Passive policy inherited from baseboard register "policies.passive" = "{[0] = DPTF_PASSIVE(NONE, NONE, 0, 0)}"
# Disable Active policy inherited from baseboard register "policies.active" = "{[0] = {.target = DPTF_NONE, .thresholds = {TEMP_PCT(0,0)}}}" device generic 0 on end end end
```
That will take all of the settings from the baseboard, but replace the passive and active with what is specified here (null policies basically). Sorry it's ugly, I will add something to make this cleaner.
Hello build bot (Jenkins), Tim Wawrzynczak, Keith Short, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#8).
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
mb/google/volteer: Add a DPTF policy for Eldrid
Enable dptf feature and remove fan control part from overridetree.cb
BUG=b:167931578
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/8
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45860/8/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/eldrid/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45860/8/src/mainboard/google/voltee... PS8, Line 67: trailing whitespace
Nick Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45860/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45860/7//COMMIT_MSG@7 PS7, Line 7: mb/google/volteer/variants/eldrid: disable Fan Performance Control : and Passive Policy
Please keep subject line to 72 chars; I suggest: […]
Done
https://review.coreboot.org/c/coreboot/+/45860/7/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/eldrid/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45860/7/src/mainboard/google/voltee... PS7, Line 61: device pci 04.0 on : # DPTF Policy for Eldrid board : chip drivers/intel/dptf : ## Active Policy : register "policies.active" = "{ : [0] = {.target = DPTF_CPU, : .thresholds = {TEMP_PCT(85, 90), : TEMP_PCT(80, 69), : TEMP_PCT(75, 56), : TEMP_PCT(70, 46), : TEMP_PCT(65, 36),}}, : [1] = {.target = DPTF_TEMP_SENSOR_0, : .thresholds = {TEMP_PCT(50, 90), : TEMP_PCT(47, 69), : TEMP_PCT(45, 56), : TEMP_PCT(42, 46), : TEMP_PCT(39, 36),}}, : [2] = {.target = DPTF_TEMP_SENSOR_1, : .thresholds = {TEMP_PCT(50, 90), : TEMP_PCT(47, 69), : TEMP_PCT(45, 56), : TEMP_PCT(42, 46), : TEMP_PCT(39, 36),}}, : [3] = {.target = DPTF_TEMP_SENSOR_2, : .thresholds = {TEMP_PCT(50, 90), : TEMP_PCT(47, 69), : TEMP_PCT(45, 56), : TEMP_PCT(42, 46), : TEMP_PCT(39, 36),}}, : [4] = {.target = DPTF_TEMP_SENSOR_3, : .thresholds = {TEMP_PCT(50, 90), : TEMP_PCT(47, 69), : TEMP_PCT(45, 56), : TEMP_PCT(42, 46), : TEMP_PCT(39, 36),}}}" : : ## Critical Policy : register "policies.critical" = "{ : [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), : [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), : [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), : [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), : [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" : : ## Power Limits Control : # 10-15W PL1 in 200mW increments, avg over 28-32s interval : # PL2 is fixed at 64W, avg over 28-32s interval : register "controls.power_limits" = "{ : .pl1 = {.min_power = 3000, : .max_power = 15000, : .time_window_min = 28 * MSECS_PER_SEC, : .time_window_max = 32 * MSECS_PER_SEC, : .granularity = 200,}, : .pl2 = {.min_power = 15000, : .max_power = 60000, : .time_window_min = 28 * MSECS_PER_SEC, : .time_window_max = 32 * MSECS_PER_SEC, : .granularity = 1000,}}" : : ## Charger Performance Control (Control, mA) : register "controls.charger_perf" = "{ : [0] = { 255, 1700 }, : [1] = { 24, 1500 }, : [2] = { 16, 1000 }, : [3] = { 8, 500 }}" : : device generic 0 on end : end : end
I don't think this isn't doing what you're expecting here. […]
Done
Hello build bot (Jenkins), Tim Wawrzynczak, Keith Short, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#9).
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
mb/google/volteer: Add a DPTF policy for Eldrid
Enable dptf feature and remove fan control part from overridetree.cb
BUG=b:167931578
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/9
Nick Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45860/8/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/eldrid/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45860/8/src/mainboard/google/voltee... PS8, Line 67:
trailing whitespace
Done
Hello build bot (Jenkins), Tim Wawrzynczak, Keith Short, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#10).
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
mb/google/volteer: Add a DPTF policy for Eldrid
Enable dptf feature and remove fan control part from overridetree.cb
BUG=b:167931578
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/10
Hello build bot (Jenkins), Tim Wawrzynczak, Keith Short, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#11).
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
mb/google/volteer: Add a DPTF policy for Eldrid
Enable dptf feature and remove fan control part from overridetree.cb
BUG=b:167931578
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/11
Hello build bot (Jenkins), Tim Wawrzynczak, Keith Short, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#12).
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
mb/google/volteer: Add a DPTF policy for Eldrid
Enable dptf feature and remove fan control part from overridetree.cb
BUG=b:167931578
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/12
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 12: Code-Review+2
Hello build bot (Jenkins), Tim Wawrzynczak, Keith Short, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#13).
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
mb/google/volteer: Add a DPTF policy for Eldrid
Enable dptf feature and remove fan control part from overridetree.cb
BUG=b:167931578
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/13
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45860/13/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/eldrid/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45860/13/src/mainboard/google/volte... PS13, Line 64: Disable Passive policy Any reason for disabling passive policy ?
Hello build bot (Jenkins), Tim Wawrzynczak, Keith Short, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#14).
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
mb/google/volteer: Add a DPTF policy for Eldrid
Enable dptf feature and remove fan control part from overridetree.cb
BUG=b:167931578
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 26 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/14
Nick Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45860/13/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/eldrid/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45860/13/src/mainboard/google/volte... PS13, Line 64: Disable Passive policy
Any reason for disabling passive policy ?
Eldrid is going to add new "Passive policy" and "Critical policy" after thermal validate.
Let me remove this part and add more policy.
Hello build bot (Jenkins), Tim Wawrzynczak, Keith Short, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#15).
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
mb/google/volteer: Add a DPTF policy for Eldrid
Enable dptf feature and remove fan control part from overridetree.cb
BUG=b:167931578, b:170357248
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 26 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/15
Hello build bot (Jenkins), Tim Wawrzynczak, Keith Short, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#16).
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
mb/google/volteer: Add a DPTF policy for Eldrid
1. Enable dptf feature and remove fan control part from overridetree.cb 2. Update tcc offset to 5
BUG=b:167931578, b:170357248
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 26 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/16
Hello build bot (Jenkins), Tim Wawrzynczak, Keith Short, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#17).
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
mb/google/volteer: Add a DPTF policy for Eldrid
1. Enable dptf feature and remove fan control part from overridetree.cb 2. Update tcc offset to 5
BUG=b:167931578, b:170357248
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 26 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/17
Nick Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 18:
This change is ready for review.
Hello build bot (Jenkins), Tim Wawrzynczak, Keith Short, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#19).
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
mb/google/volteer: Add a DPTF policy for Eldrid
1. Enable dptf feature and remove fan control part from overridetree.cb 2. Update tcc offset to 5 3. Update PL2 max_power to 51
BUG=b:167931578, b:170357248
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 59 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/19
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 19:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45860/19/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/eldrid/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45860/19/src/mainboard/google/volte... PS19, Line 76: trailing whitespace
Hello build bot (Jenkins), Tim Wawrzynczak, Keith Short, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#20).
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
mb/google/volteer: Add a DPTF policy for Eldrid
1. Enable dptf feature and remove fan control part from overridetree.cb 2. Update tcc offset to 5 3. Update PL2 max_power to 51
BUG=b:167931578, b:170357248
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 59 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/20
Nick Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 20:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45860/19/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/eldrid/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45860/19/src/mainboard/google/volte... PS19, Line 76:
trailing whitespace
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 20:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45860/18/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/eldrid/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45860/18/src/mainboard/google/volte... PS18, Line 69: 3 Are you trying to just override the thresholds for CPU and sensor 2? Then you'll need the following: ``` register "policies.passive[0]" = "DPTF_PASSIVE(CPU,CPU,95,5000)" register "policies.passive[3]" = "DPTF_PASSIVE(CPU,TEMP_SENSOR_2,60,6000)" ```
https://review.coreboot.org/c/coreboot/+/45860/18/src/mainboard/google/volte... PS18, Line 74: 3 Same as above, if you're trying to overwrite/override the settings for CPU & temp_sensor_2, you'll need to structure it the same way as above.
https://review.coreboot.org/c/coreboot/+/45860/18/src/mainboard/google/volte... PS18, Line 79: To disable active policy, you'll need the following: ``` register "policies.active" = "{[0] = {.target=DPTF_NONE}}" ``` or similar to disable what's inherited from the baseboard.
Hello build bot (Jenkins), Tim Wawrzynczak, Keith Short, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#21).
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
mb/google/volteer: Add a DPTF policy for Eldrid
1. Enable dptf feature and remove fan control part from overridetree.cb 2. Update tcc offset to 5 3. Update PL2 max_power to 51
BUG=b:167931578, b:170357248
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 53 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/21
Nick Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 21:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45860/18/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/eldrid/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45860/18/src/mainboard/google/volte... PS18, Line 69: 3
Are you trying to just override the thresholds for CPU and sensor 2? Then you'll need the following: […]
Done
https://review.coreboot.org/c/coreboot/+/45860/18/src/mainboard/google/volte... PS18, Line 74: 3
Same as above, if you're trying to overwrite/override the settings for CPU & temp_sensor_2, you'll n […]
Done
https://review.coreboot.org/c/coreboot/+/45860/18/src/mainboard/google/volte... PS18, Line 79:
To disable active policy, you'll need the following: […]
Done
Nick Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 21:
Hi Tim, if the CL is good, can you help to review the CL?
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 21:
(4 comments)
https://review.coreboot.org/c/coreboot/+/45860/21/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/eldrid/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45860/21/src/mainboard/google/volte... PS21, Line 11: 105 Does this mean only PL4 has different values between U2-2 and U4-2 SoC types ? What about PL1 and PL2 values, please confirm.
https://review.coreboot.org/c/coreboot/+/45860/21/src/mainboard/google/volte... PS21, Line 89: 10 Update comment value according to below used value.
https://review.coreboot.org/c/coreboot/+/45860/21/src/mainboard/google/volte... PS21, Line 90: 64 Same comment as above.
https://review.coreboot.org/c/coreboot/+/45860/21/src/mainboard/google/volte... PS21, Line 103: ## Disable Fan Performance Control from baseboard : register "controls.fan_perf" = "{ : [0] = { 0, 0, 0, 0 }}" : : # Disable Fan options from baseboard : register "options.fan.fine_grained_control" = "0" : register "options.fan.step_size" = "0" Active policy already disabled at line 78 above. Do you still need this ?
Hello build bot (Jenkins), Tim Wawrzynczak, Keith Short, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#22).
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
mb/google/volteer: Add a DPTF policy for Eldrid
1. Enable dptf feature and remove fan control part from overridetree.cb 2. Update tcc offset to 5 3. Update PL2 max_power to 51
BUG=b:167931578, b:170357248
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 43 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/22
Nick Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 22:
(4 comments)
https://review.coreboot.org/c/coreboot/+/45860/21/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/eldrid/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45860/21/src/mainboard/google/volte... PS21, Line 11: 105
Does this mean only PL4 has different values between U2-2 and U4-2 SoC types ? What about PL1 and PL […]
Eldrid don't needed to define pl4 after we concern with thermal team. So I removed the part.
https://review.coreboot.org/c/coreboot/+/45860/21/src/mainboard/google/volte... PS21, Line 89: 10
Update comment value according to below used value.
done
https://review.coreboot.org/c/coreboot/+/45860/21/src/mainboard/google/volte... PS21, Line 90: 64
Same comment as above.
done
https://review.coreboot.org/c/coreboot/+/45860/21/src/mainboard/google/volte... PS21, Line 103: ## Disable Fan Performance Control from baseboard : register "controls.fan_perf" = "{ : [0] = { 0, 0, 0, 0 }}" : : # Disable Fan options from baseboard : register "options.fan.fine_grained_control" = "0" : register "options.fan.step_size" = "0"
Active policy already disabled at line 78 above. […]
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 22:
(4 comments)
https://review.coreboot.org/c/coreboot/+/45860/22//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45860/22//COMMIT_MSG@2 PS22, Line 2: nick_xr_chen Please use *Nick Chen*.
https://review.coreboot.org/c/coreboot/+/45860/22//COMMIT_MSG@10 PS22, Line 10: 2. Update tcc offset to 5 Please remove the trailing space.
https://review.coreboot.org/c/coreboot/+/45860/22//COMMIT_MSG@12 PS22, Line 12: Who gave you the number?
https://review.coreboot.org/c/coreboot/+/45860/22//COMMIT_MSG@15 PS22, Line 15: nick_xr_chen Nick Chen
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 22:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45860/22/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/eldrid/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45860/22/src/mainboard/google/volte... PS22, Line 79: register "policies.passive[0]" = "DPTF_PASSIVE(CPU,CPU,95,5000)" : register "policies.passive[3]" = "DPTF_PASSIVE(CPU,TEMP_SENSOR_2,60,6000)" Sorry Nick, I got myself confused the other day 😞
To override just the CPU and TEMP_SENSOR_2, this needs to be: ``` ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 60, 6000), [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}"
```
https://review.coreboot.org/c/coreboot/+/45860/22/src/mainboard/google/volte... PS22, Line 82: ## Critical Policy : register "policies.critical[0]" = "DPTF_CRITICAL(CPU,100,SHUTDOWN)" : register "policies.critical[3]" = "DPTF_CRITICAL(TEMP_SENSOR_2,80,SHUTDOWN)" I apologize, the same thing here: ``` ## Critical Policy register "policies.critical" = "{ [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN), [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" ```
Hello build bot (Jenkins), Tim Wawrzynczak, Keith Short, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#23).
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
mb/google/volteer: Add a DPTF policy for Eldrid
1. Enable dptf feature and remove fan control part from overridetree.cb 2. Update tcc offset to 5 3. Update PL2 max_power to 51
BUG=b:167931578, b:170357248
Signed-off-by: Nick Chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 43 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/23
Hello build bot (Jenkins), Tim Wawrzynczak, Keith Short, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#24).
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
mb/google/volteer: Add a DPTF policy for Eldrid
1. Enable dptf feature and remove fan control part from overridetree.cb 2. Update tcc offset to 5 3. Update PL2 max_power to 51
BUG=b:167931578, b:170357248
Signed-off-by: nick_xr_chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 43 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/24
Hello build bot (Jenkins), Tim Wawrzynczak, Keith Short, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#25).
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
mb/google/volteer: Add a DPTF policy for Eldrid
1. Enable dptf feature and remove fan control part from overridetree.cb 2. Update tcc offset to 5 3. Update PL2 max_power to 51
BUG=b:167931578, b:170357248
Signed-off-by: Nick Chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 45 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/25
Nick Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 25:
(6 comments)
https://review.coreboot.org/c/coreboot/+/45860/22//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45860/22//COMMIT_MSG@2 PS22, Line 2: nick_xr_chen
Please use *Nick Chen*.
Done
https://review.coreboot.org/c/coreboot/+/45860/22//COMMIT_MSG@10 PS22, Line 10: 2. Update tcc offset to 5
Please remove the trailing space.
Done
https://review.coreboot.org/c/coreboot/+/45860/22//COMMIT_MSG@12 PS22, Line 12:
Who gave you the number?
Base on b:/170357248#4, the value is decided by thermal team
https://review.coreboot.org/c/coreboot/+/45860/22//COMMIT_MSG@15 PS22, Line 15: nick_xr_chen
Nick Chen
Done
https://review.coreboot.org/c/coreboot/+/45860/22/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/eldrid/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45860/22/src/mainboard/google/volte... PS22, Line 79: register "policies.passive[0]" = "DPTF_PASSIVE(CPU,CPU,95,5000)" : register "policies.passive[3]" = "DPTF_PASSIVE(CPU,TEMP_SENSOR_2,60,6000)"
Sorry Nick, I got myself confused the other day 😞 […]
Thanks for your support. We just concern cpu and temp_sensor_2 so we only add [0] and [3] on the register. Is the change correct?
https://review.coreboot.org/c/coreboot/+/45860/22/src/mainboard/google/volte... PS22, Line 82: ## Critical Policy : register "policies.critical[0]" = "DPTF_CRITICAL(CPU,100,SHUTDOWN)" : register "policies.critical[3]" = "DPTF_CRITICAL(TEMP_SENSOR_2,80,SHUTDOWN)"
I apologize, the same thing here: […]
Same as above.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 25:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45860/22//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45860/22//COMMIT_MSG@12 PS22, Line 12:
Base on b:/170357248#4, the value is decided by thermal team
Unfortunately, the access to the bug report is restricted, so please add the information to the commit message.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 25:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45860/22/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/eldrid/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45860/22/src/mainboard/google/volte... PS22, Line 79: register "policies.passive[0]" = "DPTF_PASSIVE(CPU,CPU,95,5000)" : register "policies.passive[3]" = "DPTF_PASSIVE(CPU,TEMP_SENSOR_2,60,6000)"
Thanks for your support. […]
If you're not using TSR 0, 1, or 3, then you'll need it to look like: ``` register "policies.passive[0]" = "..." register "policies.passive[1]" = "..." ```
https://review.coreboot.org/c/coreboot/+/45860/22/src/mainboard/google/volte... PS22, Line 82: ## Critical Policy : register "policies.critical[0]" = "DPTF_CRITICAL(CPU,100,SHUTDOWN)" : register "policies.critical[3]" = "DPTF_CRITICAL(TEMP_SENSOR_2,80,SHUTDOWN)"
Same as above.
If you're not using TSR 0, 1, or 3, then you'll need it to look like:
register "policies.critical[0]" = "..." register "policies.critical[1]" = "..."
Hello build bot (Jenkins), Tim Wawrzynczak, Keith Short, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45860
to look at the new patch set (#26).
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
mb/google/volteer: Add a DPTF policy for Eldrid
1. Enable dptf feature and remove fan control part from overridetree.cb 2. Update tcc offset to 5 3. Follow thermal validation and update PL2 max_power to 51
BUG=b:167931578, b:170357248
Signed-off-by: Nick Chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 43 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/26
Nick Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 26:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45860/22//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45860/22//COMMIT_MSG@12 PS22, Line 12:
Unfortunately, the access to the bug report is restricted, so please add the information to the comm […]
Done
https://review.coreboot.org/c/coreboot/+/45860/22/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/eldrid/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45860/22/src/mainboard/google/volte... PS22, Line 79: register "policies.passive[0]" = "DPTF_PASSIVE(CPU,CPU,95,5000)" : register "policies.passive[3]" = "DPTF_PASSIVE(CPU,TEMP_SENSOR_2,60,6000)"
If you're not using TSR 0, 1, or 3, then you'll need it to look like: […]
Done
https://review.coreboot.org/c/coreboot/+/45860/22/src/mainboard/google/volte... PS22, Line 82: ## Critical Policy : register "policies.critical[0]" = "DPTF_CRITICAL(CPU,100,SHUTDOWN)" : register "policies.critical[3]" = "DPTF_CRITICAL(TEMP_SENSOR_2,80,SHUTDOWN)"
If you're not using TSR 0, 1, or 3, then you'll need it to look like: […]
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 26: Code-Review+2
Nick Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
Patch Set 26:
Hi Googler,
The CL has benn +2, could you help to review and merge the CL?
Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45860 )
Change subject: mb/google/volteer: Add a DPTF policy for Eldrid ......................................................................
mb/google/volteer: Add a DPTF policy for Eldrid
1. Enable dptf feature and remove fan control part from overridetree.cb 2. Update tcc offset to 5 3. Follow thermal validation and update PL2 max_power to 51
BUG=b:167931578, b:170357248
Signed-off-by: Nick Chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45860 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 43 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 5fcd456..7fd6576 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -1,5 +1,15 @@ chip soc/intel/tigerlake
+ register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" + + register "tcc_offset" = "5" # TCC of 95 register "TcssAuxOri" = "1" register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" @@ -58,7 +68,39 @@ }"
device domain 0 on - device ref dptf off end + device ref dptf on + # DPTF Policy for Eldrid board + chip drivers/intel/dptf + + ## Disable Active Policy from baseboard + register "policies.active" = "{[0] = {.target=DPTF_NONE}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU,CPU,95,5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU,TEMP_SENSOR_2,60,6000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU,100,SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_2,80,SHUTDOWN)" + + ## Power Limits Control + # 3-15W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is fixed at 51W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 15000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + device generic 0 on end + end + end device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682""
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build bot (Jenkins) (Code Review) -
Keith Short (Code Review)
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Nick Chen (Code Review)
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Paul Menzel (Code Review)
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