Hello Weiyi Lu,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/45402
to review the following change.
Change subject: soc/mediatek: Add function to get clock frequency of MT8192 ......................................................................
soc/mediatek: Add function to get clock frequency of MT8192
Implement mt_fmeter_get_freq() in MT8192 to get frequency of some pre-defined clocks in the frequency meter.
Signed-off-by: Weiyi Lu weiyi.lu@mediatek.com Change-Id: I75df0b040ed7ea73d25724a3c80040f4e731118f --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/pll.c 3 files changed, 80 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/45402/1
diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index 0f8732f..1787c4b 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -60,4 +60,10 @@ void mt_pll_init(void); void mt_pll_raise_little_cpu_freq(u32 freq);
+enum fmeter_type { + FMETER_ABIST = 0, + FMETER_CKGEN +}; +unsigned int mt_fmeter_get_freq(enum fmeter_type type, unsigned int id); + #endif diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index 177bd33..f4a7180 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -299,4 +299,10 @@ DEFINE_BITFIELD(PLLGP1_LVRREF, 18, 17) DEFINE_BITFIELD(PLLGP2_LVRREF, 10, 9)
+DEFINE_BITFIELD(CLK_DBG_CFG_ABIST_CK_SEL, 21, 16) +DEFINE_BITFIELD(CLK_DBG_CFG_CKGEN_CK_SEL, 13, 8) +DEFINE_BITFIELD(CLK_DBG_CFG_METER_CK_SEL, 1, 0) +DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24) +DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) + #endif /* SOC_MEDIATEK_MT8192_PLL_H */ diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index e8849df..94dc469 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -459,3 +459,71 @@ /* disable [4] intermediate clock armpll_divider_pll1_ck */ clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); } + +unsigned int mt_fmeter_get_freq(enum fmeter_type type, unsigned int id) +{ + unsigned int output = 0, i = 0, count, clk_dbg_cfg, clk_misc_cfg_0; + bool timeout = false; + + /* backup */ + clk_dbg_cfg = read32(&mtk_topckgen->clk_dbg_cfg); + clk_misc_cfg_0 = read32(&mtk_topckgen->clk_misc_cfg_0); + + /* set up frequency meter */ + if (type == FMETER_ABIST) { + SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg, + CLK_DBG_CFG_ABIST_CK_SEL, id, + CLK_DBG_CFG_CKGEN_CK_SEL, 0, + CLK_DBG_CFG_METER_CK_SEL, 0); + SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, + CLK_MISC_CFG_0_METER_DIV, 1); + } else if (type == FMETER_CKGEN) { + SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg, + CLK_DBG_CFG_ABIST_CK_SEL, 0, + CLK_DBG_CFG_CKGEN_CK_SEL, id, + CLK_DBG_CFG_METER_CK_SEL, 1); + SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, + CLK_MISC_CFG_0_METER_DIV, 0); + } else + return 0; + + /* enable frequency meter */ + write32(&mtk_topckgen->clk26cali_0, 0x1000); + + /* set load count = 1024-1 */ + SET32_BITFIELDS(&mtk_topckgen->clk26cali_1, + CLK26CALI_1_LOAD_CNT, 0x3ff); + + /* trigger frequency meter */ + setbits32(&mtk_topckgen->clk26cali_0, 0x10); + + /* wait frequency meter until finished */ + while (read32(&mtk_topckgen->clk26cali_0) & 0x10) { + udelay(10); + i++; + if (i > 20) { + timeout = true; + break; + } + } + + count = read32(&mtk_topckgen->clk26cali_1) & 0xffff; + + output = (count * 26000) / 1024; /* KHz */ + + /* disable frequency meter */ + write32(&mtk_topckgen->clk26cali_0, 0x0000); + + /* restore */ + write32(&mtk_topckgen->clk_dbg_cfg, clk_dbg_cfg); + write32(&mtk_topckgen->clk_misc_cfg_0, clk_misc_cfg_0); + + if (!timeout) { + if (type == FMETER_ABIST) + return (output * 2); + else if (type == FMETER_CKGEN) + return output; + } + + return 0; +}
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45402 )
Change subject: soc/mediatek: Add function to get clock frequency of MT8192 ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45402/1/src/soc/mediatek/mt8192/pll... File src/soc/mediatek/mt8192/pll.c:
https://review.coreboot.org/c/coreboot/+/45402/1/src/soc/mediatek/mt8192/pll... PS1, Line 495: CLK26CALI_1_LOAD_CNT align to previous (
https://review.coreboot.org/c/coreboot/+/45402/1/src/soc/mediatek/mt8192/pll... PS1, Line 498: 0x10 give this a name (especially we'll reuse it below)?
https://review.coreboot.org/c/coreboot/+/45402/1/src/soc/mediatek/mt8192/pll... PS1, Line 502: udelay(10); Is udelay(10) needed? can we use stopwatch?
Weiyi Lu has uploaded a new patch set (#2) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/45402 )
Change subject: soc/mediatek: Add function to get clock frequency of MT8192 ......................................................................
soc/mediatek: Add function to get clock frequency of MT8192
Implement mt_fmeter_get_freq() in MT8192 to get frequency of some pre-defined clocks in the frequency meter.
Signed-off-by: Weiyi Lu weiyi.lu@mediatek.com Change-Id: I75df0b040ed7ea73d25724a3c80040f4e731118f --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/pll.c 3 files changed, 74 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/45402/2
Weiyi Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45402 )
Change subject: soc/mediatek: Add function to get clock frequency of MT8192 ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45402/1/src/soc/mediatek/mt8192/pll... File src/soc/mediatek/mt8192/pll.c:
https://review.coreboot.org/c/coreboot/+/45402/1/src/soc/mediatek/mt8192/pll... PS1, Line 495: CLK26CALI_1_LOAD_CNT
align to previous (
Done
https://review.coreboot.org/c/coreboot/+/45402/1/src/soc/mediatek/mt8192/pll... PS1, Line 498: 0x10
give this a name (especially we'll reuse it below)?
Done
https://review.coreboot.org/c/coreboot/+/45402/1/src/soc/mediatek/mt8192/pll... PS1, Line 502: udelay(10);
Is udelay(10) needed? can we use stopwatch?
Done
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45402 )
Change subject: soc/mediatek: Add function to get clock frequency of MT8192 ......................................................................
Patch Set 2:
(7 comments)
https://review.coreboot.org/c/coreboot/+/45402/2/src/soc/mediatek/common/inc... File src/soc/mediatek/common/include/soc/pll_common.h:
https://review.coreboot.org/c/coreboot/+/45402/2/src/soc/mediatek/common/inc... PS2, Line 65: N Please add a trailing "," for consistency.
https://review.coreboot.org/c/coreboot/+/45402/2/src/soc/mediatek/common/inc... PS2, Line 67: unsigned int u32
https://review.coreboot.org/c/coreboot/+/45402/2/src/soc/mediatek/mt8192/pll... File src/soc/mediatek/mt8192/pll.c:
https://review.coreboot.org/c/coreboot/+/45402/2/src/soc/mediatek/mt8192/pll... PS2, Line 488: return 0; Do we want to die() in this case?
https://review.coreboot.org/c/coreboot/+/45402/2/src/soc/mediatek/mt8192/pll... PS2, Line 497: setbits32(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER); Could also we use the SET32_BITFIELDS API for this?
https://review.coreboot.org/c/coreboot/+/45402/2/src/soc/mediatek/mt8192/pll... PS2, Line 503: else Also add {} for the else block.
https://review.coreboot.org/c/coreboot/+/45402/2/src/soc/mediatek/mt8192/pll... PS2, Line 504: output = 0; If this is an error case, perhaps at least print an error message here?
https://review.coreboot.org/c/coreboot/+/45402/2/src/soc/mediatek/mt8192/pll... PS2, Line 514: ( No need for the parentheses.
Weiyi Lu has uploaded a new patch set (#3) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/45402 )
Change subject: soc/mediatek: Add function to get clock frequency of MT8192 ......................................................................
soc/mediatek: Add function to get clock frequency of MT8192
Implement mt_fmeter_get_freq() in MT8192 to get frequency of some pre-defined clocks in the frequency meter.
Signed-off-by: Weiyi Lu weiyi.lu@mediatek.com Change-Id: I75df0b040ed7ea73d25724a3c80040f4e731118f --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/pll.c 3 files changed, 74 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/45402/3
Weiyi Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45402 )
Change subject: soc/mediatek: Add function to get clock frequency of MT8192 ......................................................................
Patch Set 3:
(7 comments)
https://review.coreboot.org/c/coreboot/+/45402/2/src/soc/mediatek/common/inc... File src/soc/mediatek/common/include/soc/pll_common.h:
https://review.coreboot.org/c/coreboot/+/45402/2/src/soc/mediatek/common/inc... PS2, Line 65: N
Please add a trailing "," for consistency.
Done
https://review.coreboot.org/c/coreboot/+/45402/2/src/soc/mediatek/common/inc... PS2, Line 67: unsigned int
u32
Done
https://review.coreboot.org/c/coreboot/+/45402/2/src/soc/mediatek/mt8192/pll... File src/soc/mediatek/mt8192/pll.c:
https://review.coreboot.org/c/coreboot/+/45402/2/src/soc/mediatek/mt8192/pll... PS2, Line 488: return 0;
Do we want to die() in this case?
Done
https://review.coreboot.org/c/coreboot/+/45402/2/src/soc/mediatek/mt8192/pll... PS2, Line 497: setbits32(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER);
Could also we use the SET32_BITFIELDS API for this?
Done
https://review.coreboot.org/c/coreboot/+/45402/2/src/soc/mediatek/mt8192/pll... PS2, Line 503: else
Also add {} for the else block.
Done
https://review.coreboot.org/c/coreboot/+/45402/2/src/soc/mediatek/mt8192/pll... PS2, Line 504: output = 0;
If this is an error case, perhaps at least print an error message here?
Done
https://review.coreboot.org/c/coreboot/+/45402/2/src/soc/mediatek/mt8192/pll... PS2, Line 514: (
No need for the parentheses.
Done
Weiyi Lu has uploaded a new patch set (#4) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/45402 )
Change subject: soc/mediatek: Add function to get clock frequency of MT8192 ......................................................................
soc/mediatek: Add function to get clock frequency of MT8192
Implement mt_fmeter_get_freq() in MT8192 to get frequency of some pre-defined clocks in the frequency meter.
Signed-off-by: Weiyi Lu weiyi.lu@mediatek.com Change-Id: I75df0b040ed7ea73d25724a3c80040f4e731118f --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/pll.c 3 files changed, 75 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/45402/4
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45402 )
Change subject: soc/mediatek: Add function to get clock frequency of MT8192 ......................................................................
Patch Set 4: Code-Review+1
Weiyi Lu has uploaded a new patch set (#5) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/45402 )
Change subject: soc/mediatek: Add function to get clock frequency of MT8192 ......................................................................
soc/mediatek: Add function to get clock frequency of MT8192
Implement mt_fmeter_get_freq() in MT8192 to get frequency of some pre-defined clocks in the frequency meter.
Signed-off-by: Weiyi Lu weiyi.lu@mediatek.com Change-Id: I75df0b040ed7ea73d25724a3c80040f4e731118f --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/pll.c 3 files changed, 75 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/45402/5
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45402 )
Change subject: soc/mediatek: Add function to get clock frequency of MT8192 ......................................................................
Patch Set 5: Code-Review+1
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45402 )
Change subject: soc/mediatek: Add function to get clock frequency of MT8192 ......................................................................
Patch Set 5:
merge conflict and build failure - please fix the chain, or move this to a separate chain.
CK HU has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45402 )
Change subject: soc/mediatek: Add function to get clock frequency of MT8192 ......................................................................
Patch Set 5:
Patch Set 5:
merge conflict and build failure - please fix the chain, or move this to a separate chain.
@Yidi, please help on this.
Yidi Lin has uploaded a new patch set (#6) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/45402 )
Change subject: soc/mediatek: Add function to get clock frequency of MT8192 ......................................................................
soc/mediatek: Add function to get clock frequency of MT8192
Implement mt_fmeter_get_freq() in MT8192 to get frequency of some pre-defined clocks in the frequency meter.
Signed-off-by: Weiyi Lu weiyi.lu@mediatek.com Change-Id: I75df0b040ed7ea73d25724a3c80040f4e731118f --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/pll.c 3 files changed, 80 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/45402/6
Yidi Lin has uploaded a new patch set (#7) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/45402 )
Change subject: soc/mediatek: Add function to get clock frequency of MT8192 ......................................................................
soc/mediatek: Add function to get clock frequency of MT8192
Implement mt_fmeter_get_freq() in MT8192 to get frequency of some pre-defined clocks in the frequency meter.
Signed-off-by: Weiyi Lu weiyi.lu@mediatek.com Change-Id: I75df0b040ed7ea73d25724a3c80040f4e731118f --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/pll.c 3 files changed, 75 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/45402/7
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45402 )
Change subject: soc/mediatek: Add function to get clock frequency of MT8192 ......................................................................
Patch Set 7: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/45402/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45402/7//COMMIT_MSG@9 PS7, Line 9: mt_fmeter_get_freq mt_fmeter_get_freq_khz
Weiyi Lu has uploaded a new patch set (#8) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/45402 )
Change subject: soc/mediatek: Add function to measure clock frequency of MT8192 ......................................................................
soc/mediatek: Add function to measure clock frequency of MT8192
Implement mt_fmeter_get_freq_khz() in MT8192 to measure frequency of some pre-defined clocks by frequency meter.
Signed-off-by: Weiyi Lu weiyi.lu@mediatek.com Change-Id: I75df0b040ed7ea73d25724a3c80040f4e731118f --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/pll.c 3 files changed, 75 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/45402/8
Weiyi Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45402 )
Change subject: soc/mediatek: Add function to measure clock frequency of MT8192 ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45402/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45402/7//COMMIT_MSG@9 PS7, Line 9: mt_fmeter_get_freq
mt_fmeter_get_freq_khz
Done
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45402 )
Change subject: soc/mediatek: Add function to measure clock frequency of MT8192 ......................................................................
Patch Set 9: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45402 )
Change subject: soc/mediatek: Add function to measure clock frequency of MT8192 ......................................................................
soc/mediatek: Add function to measure clock frequency of MT8192
Implement mt_fmeter_get_freq_khz() in MT8192 to measure frequency of some pre-defined clocks by frequency meter.
Signed-off-by: Weiyi Lu weiyi.lu@mediatek.com Change-Id: I75df0b040ed7ea73d25724a3c80040f4e731118f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45402 Reviewed-by: Hung-Te Lin hungte@chromium.org Reviewed-by: Yu-Ping Wu yupingso@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/pll.c 3 files changed, 75 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, but someone else must approve
diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index 0f8732f..d9ba230 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -60,4 +60,10 @@ void mt_pll_init(void); void mt_pll_raise_little_cpu_freq(u32 freq);
+enum fmeter_type { + FMETER_ABIST = 0, + FMETER_CKGEN, +}; +u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id); + #endif diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index 43c2528..d5a9cf9 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -295,4 +295,11 @@ DEFINE_BITFIELD(PLLGP1_LVRREF, 18, 17) DEFINE_BITFIELD(PLLGP2_LVRREF, 10, 9)
+DEFINE_BITFIELD(CLK_DBG_CFG_ABIST_CK_SEL, 21, 16) +DEFINE_BITFIELD(CLK_DBG_CFG_CKGEN_CK_SEL, 13, 8) +DEFINE_BITFIELD(CLK_DBG_CFG_METER_CK_SEL, 1, 0) +DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24) +DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) +DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) + #endif /* SOC_MEDIATEK_MT8192_PLL_H */ diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index e8849df..11750d2 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <console/console.h> #include <device/mmio.h> #include <delay.h> #include <stddef.h> +#include <timer.h>
#include <soc/addressmap.h> #include <soc/infracfg.h> @@ -459,3 +461,63 @@ /* disable [4] intermediate clock armpll_divider_pll1_ck */ clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); } + +u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id) +{ + u32 output, count, clk_dbg_cfg, clk_misc_cfg_0; + + /* backup */ + clk_dbg_cfg = read32(&mtk_topckgen->clk_dbg_cfg); + clk_misc_cfg_0 = read32(&mtk_topckgen->clk_misc_cfg_0); + + /* set up frequency meter */ + if (type == FMETER_ABIST) { + SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg, + CLK_DBG_CFG_ABIST_CK_SEL, id, + CLK_DBG_CFG_CKGEN_CK_SEL, 0, + CLK_DBG_CFG_METER_CK_SEL, 0); + SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, + CLK_MISC_CFG_0_METER_DIV, 1); + } else if (type == FMETER_CKGEN) { + SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg, + CLK_DBG_CFG_ABIST_CK_SEL, 0, + CLK_DBG_CFG_CKGEN_CK_SEL, id, + CLK_DBG_CFG_METER_CK_SEL, 1); + SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, + CLK_MISC_CFG_0_METER_DIV, 0); + } else { + die("unsupport fmeter type\n"); + } + + /* enable frequency meter */ + write32(&mtk_topckgen->clk26cali_0, 0x1000); + + /* set load count = 1024-1 */ + SET32_BITFIELDS(&mtk_topckgen->clk26cali_1, CLK26CALI_1_LOAD_CNT, 0x3ff); + + /* trigger frequency meter */ + SET32_BITFIELDS(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER, 1); + + /* wait frequency meter until finished */ + if (wait_us(200, !READ32_BITFIELD(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER))) { + count = read32(&mtk_topckgen->clk26cali_1) & 0xffff; + output = (count * 26000) / 1024; /* KHz */ + } else { + printk(BIOS_WARNING, "fmeter timeout\n"); + output = 0; + } + + /* disable frequency meter */ + write32(&mtk_topckgen->clk26cali_0, 0x0000); + + /* restore */ + write32(&mtk_topckgen->clk_dbg_cfg, clk_dbg_cfg); + write32(&mtk_topckgen->clk_misc_cfg_0, clk_misc_cfg_0); + + if (type == FMETER_ABIST) + return output * 2; + else if (type == FMETER_CKGEN) + return output; + + return 0; +}
-
CK HU (Code Review) -
Hung-Te Lin (Code Review)
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Weiyi Lu (Code Review)
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Yidi Lin (Code Review)
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Yu-Ping Wu (Code Review)