CK HU would like Weiyi Lu to review this change.

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soc/mediatek: Add function to get clock frequency of MT8192

Implement mt_fmeter_get_freq() in MT8192 to get frequency of
some pre-defined clocks in the frequency meter.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: I75df0b040ed7ea73d25724a3c80040f4e731118f
---
M src/soc/mediatek/common/include/soc/pll_common.h
M src/soc/mediatek/mt8192/include/soc/pll.h
M src/soc/mediatek/mt8192/pll.c
3 files changed, 80 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/45402/1

diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h
index 0f8732f..1787c4b 100644
--- a/src/soc/mediatek/common/include/soc/pll_common.h
+++ b/src/soc/mediatek/common/include/soc/pll_common.h
@@ -60,4 +60,10 @@
 void mt_pll_init(void);
 void mt_pll_raise_little_cpu_freq(u32 freq);
 
+enum fmeter_type {
+	FMETER_ABIST = 0,
+	FMETER_CKGEN
+};
+unsigned int mt_fmeter_get_freq(enum fmeter_type type, unsigned int id);
+
 #endif
diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h
index 177bd33..f4a7180 100644
--- a/src/soc/mediatek/mt8192/include/soc/pll.h
+++ b/src/soc/mediatek/mt8192/include/soc/pll.h
@@ -299,4 +299,10 @@
 DEFINE_BITFIELD(PLLGP1_LVRREF, 18, 17)
 DEFINE_BITFIELD(PLLGP2_LVRREF, 10, 9)
 
+DEFINE_BITFIELD(CLK_DBG_CFG_ABIST_CK_SEL, 21, 16)
+DEFINE_BITFIELD(CLK_DBG_CFG_CKGEN_CK_SEL, 13, 8)
+DEFINE_BITFIELD(CLK_DBG_CFG_METER_CK_SEL, 1, 0)
+DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24)
+DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16)
+
 #endif /* SOC_MEDIATEK_MT8192_PLL_H */
diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c
index e8849df..94dc469 100644
--- a/src/soc/mediatek/mt8192/pll.c
+++ b/src/soc/mediatek/mt8192/pll.c
@@ -459,3 +459,71 @@
 	/* disable [4] intermediate clock armpll_divider_pll1_ck */
 	clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
 }
+
+unsigned int mt_fmeter_get_freq(enum fmeter_type type, unsigned int id)
+{
+	unsigned int output = 0, i = 0, count, clk_dbg_cfg, clk_misc_cfg_0;
+	bool timeout = false;
+
+	/* backup */
+	clk_dbg_cfg = read32(&mtk_topckgen->clk_dbg_cfg);
+	clk_misc_cfg_0 = read32(&mtk_topckgen->clk_misc_cfg_0);
+
+	/* set up frequency meter */
+	if (type == FMETER_ABIST) {
+		SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg,
+			CLK_DBG_CFG_ABIST_CK_SEL, id,
+			CLK_DBG_CFG_CKGEN_CK_SEL, 0,
+			CLK_DBG_CFG_METER_CK_SEL, 0);
+		SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0,
+			CLK_MISC_CFG_0_METER_DIV, 1);
+	} else if (type == FMETER_CKGEN) {
+		SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg,
+			CLK_DBG_CFG_ABIST_CK_SEL, 0,
+			CLK_DBG_CFG_CKGEN_CK_SEL, id,
+			CLK_DBG_CFG_METER_CK_SEL, 1);
+		SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0,
+			CLK_MISC_CFG_0_METER_DIV, 0);
+	} else
+		return 0;
+
+	/* enable frequency meter */
+	write32(&mtk_topckgen->clk26cali_0, 0x1000);
+
+	/* set load count = 1024-1 */
+	SET32_BITFIELDS(&mtk_topckgen->clk26cali_1,
+		CLK26CALI_1_LOAD_CNT, 0x3ff);
+
+	/* trigger frequency meter */
+	setbits32(&mtk_topckgen->clk26cali_0, 0x10);
+
+	/* wait frequency meter until finished */
+	while (read32(&mtk_topckgen->clk26cali_0) & 0x10) {
+		udelay(10);
+		i++;
+		if (i > 20) {
+			timeout = true;
+			break;
+		}
+	}
+
+	count = read32(&mtk_topckgen->clk26cali_1) & 0xffff;
+
+	output = (count * 26000) / 1024; /* KHz */
+
+	/* disable frequency meter */
+	write32(&mtk_topckgen->clk26cali_0, 0x0000);
+
+	/* restore */
+	write32(&mtk_topckgen->clk_dbg_cfg, clk_dbg_cfg);
+	write32(&mtk_topckgen->clk_misc_cfg_0, clk_misc_cfg_0);
+
+	if (!timeout) {
+		if (type == FMETER_ABIST)
+			return (output * 2);
+		else if (type == FMETER_CKGEN)
+			return output;
+	}
+
+	return 0;
+}

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