Marvin Drees has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48648 )
Change subject: mb/asus: Add ASUS H110T mainboard ......................................................................
mb/asus: Add ASUS H110T mainboard
This initial commit isn't yet fully working but in order to get it sorted it is pushed already.
As the IGD and serial line aren't fully working yet, it is hard to tell what parts of the hardware already work and which don't.
Tested payloads so far: coreinfo and tianocore.
Signed-off-by: Marvin Drees marvin@ceres-sys.de Change-Id: Iab30596f2a12931679687c9f56427712b65f9363 --- A src/mainboard/asus/h110t/Kconfig A src/mainboard/asus/h110t/Kconfig.name A src/mainboard/asus/h110t/Makefile.inc A src/mainboard/asus/h110t/acpi/dptf.asl A src/mainboard/asus/h110t/acpi/ec.asl A src/mainboard/asus/h110t/acpi/mainboard.asl A src/mainboard/asus/h110t/acpi/superio.asl A src/mainboard/asus/h110t/board_info.txt A src/mainboard/asus/h110t/bootblock.c A src/mainboard/asus/h110t/cmos.default A src/mainboard/asus/h110t/cmos.layout A src/mainboard/asus/h110t/data.vbt A src/mainboard/asus/h110t/devicetree.cb A src/mainboard/asus/h110t/dsdt.asl A src/mainboard/asus/h110t/gma-mainboard.ads A src/mainboard/asus/h110t/hda_verb.c A src/mainboard/asus/h110t/include/gpio.h A src/mainboard/asus/h110t/mainboard.c A src/mainboard/asus/h110t/ramstage.c A src/mainboard/asus/h110t/romstage.c 20 files changed, 1,218 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/48648/1
diff --git a/src/mainboard/asus/h110t/Kconfig b/src/mainboard/asus/h110t/Kconfig new file mode 100644 index 0000000..676ecad --- /dev/null +++ b/src/mainboard/asus/h110t/Kconfig @@ -0,0 +1,51 @@ +if BOARD_ASUS_H110T + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select SOC_INTEL_KABYLAKE + select SKYLAKE_SOC_PCH_H + select SUPERIO_NUVOTON_COMMON_COM_A + select SUPERIO_NUVOTON_NCT5539D + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + select MAINBOARD_USES_IFD_GBE_REGION + select DRIVER_INTEL_I210 + select MAINBOARD_HAS_LPC_TPM + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "asus/h110t" + +config MAINBOARD_PART_NUMBER + string + default "H110T" + +config MAX_CPUS + int + default 8 + +config DEVICETREE + string + default "devicetree.cb" + +config DIMM_SPD_SIZE + int + default 512 # DDR4 + +# This is overridden if CMOS is used for configuration values. +config MAINBOARD_POWER_ON_AFTER_POWER_FAIL + bool + default n + +endif diff --git a/src/mainboard/asus/h110t/Kconfig.name b/src/mainboard/asus/h110t/Kconfig.name new file mode 100644 index 0000000..f9d5c9c --- /dev/null +++ b/src/mainboard/asus/h110t/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_H110T + bool "H110T" diff --git a/src/mainboard/asus/h110t/Makefile.inc b/src/mainboard/asus/h110t/Makefile.inc new file mode 100644 index 0000000..ef44a4c --- /dev/null +++ b/src/mainboard/asus/h110t/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/h110t/acpi/dptf.asl b/src/mainboard/asus/h110t/acpi/dptf.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/h110t/acpi/dptf.asl diff --git a/src/mainboard/asus/h110t/acpi/ec.asl b/src/mainboard/asus/h110t/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/h110t/acpi/ec.asl diff --git a/src/mainboard/asus/h110t/acpi/mainboard.asl b/src/mainboard/asus/h110t/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/h110t/acpi/mainboard.asl diff --git a/src/mainboard/asus/h110t/acpi/superio.asl b/src/mainboard/asus/h110t/acpi/superio.asl new file mode 100644 index 0000000..800e80a --- /dev/null +++ b/src/mainboard/asus/h110t/acpi/superio.asl @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define NCT5539D_SHOW_SP1 +#define NCT5539D_SHOW_KBC +#define NCT5539D_SHOW_HWM + +#undef NCT5539D_SHOW_GPIO diff --git a/src/mainboard/asus/h110t/board_info.txt b/src/mainboard/asus/h110t/board_info.txt new file mode 100644 index 0000000..37aa41c --- /dev/null +++ b/src/mainboard/asus/h110t/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/H110T/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2016 diff --git a/src/mainboard/asus/h110t/bootblock.c b/src/mainboard/asus/h110t/bootblock.c new file mode 100644 index 0000000..d3f9ef3 --- /dev/null +++ b/src/mainboard/asus/h110t/bootblock.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/gpio.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5539d/nct5539d.h> +#include "include/gpio.h" + +static void early_config_superio(void) +{ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT5539D_SP1); + nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} + +void bootblock_mainboard_early_init(void) +{ + early_config_superio(); +} diff --git a/src/mainboard/asus/h110t/cmos.default b/src/mainboard/asus/h110t/cmos.default new file mode 100644 index 0000000..f4dbc7e --- /dev/null +++ b/src/mainboard/asus/h110t/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +hyper_threading=Enable diff --git a/src/mainboard/asus/h110t/cmos.layout b/src/mainboard/asus/h110t/cmos.layout new file mode 100644 index 0000000..81dd48b --- /dev/null +++ b/src/mainboard/asus/h110t/cmos.layout @@ -0,0 +1,111 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +#416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +#896 32 r 0 mrc_scrambler_seed +#928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/asus/h110t/data.vbt b/src/mainboard/asus/h110t/data.vbt new file mode 100644 index 0000000..0061c69 --- /dev/null +++ b/src/mainboard/asus/h110t/data.vbt Binary files differ diff --git a/src/mainboard/asus/h110t/devicetree.cb b/src/mainboard/asus/h110t/devicetree.cb new file mode 100644 index 0000000..82f8968 --- /dev/null +++ b/src/mainboard/asus/h110t/devicetree.cb @@ -0,0 +1,196 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # FSP Configuration + register "PrimaryDisplay" = "Display_iGFX" + register "SaGv" = "SaGv_Enabled" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + subsystemid 0x1043 0x8694 inherit # Asus specific + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on # USB xHCI + # TODO get these values right + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off end # Thermal Subsystem + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on # SATA + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + }" + end + device pci 19.0 off end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1c.0 on # PCI Express Port 5 + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + end + device pci 1d.0 on # PCI Express Port 9 + register "PcieRpEnable[8]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + end + device pci 1d.1 on # PCI Express Port 10 - Realtek onboard LAN + register "PcieRpEnable[9]" = "1" + register "PcieRpAdvancedErrorReporting[9]" = "1" + register "PcieRpLtrEnable[9]" = "1" + # Disable CLKREQ#, since onboard LAN is always present + register "PcieRpClkReqSupport[9]" = "0" + end + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on # LPC bridge # TODO the superio config probably needs improvement + + # Set LPC Serial IRQ mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + chip superio/common + device pnp 2e.ff on # passes SIO base addr to SSDT gen + chip superio/nuvoton/nct5539d + device pnp 2e.1 on + irq 0x13 = 0xff + irq 0x14 = 0xff + irq 0x1a = 0x00 + irq 0x24 = 0x00 + irq 0x26 = 0x00 + irq 0x27 = 0x01 + irq 0x28 = 0x10 + irq 0x2a = 0x00 + irq 0x2c = 0x00 + irq 0x2d = 0x02 + irq 0x2f = 0x00 + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO7 + device pnp 2e.107 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.308 off end # GPIO BASE + device pnp 2e.408 off end # WDTMEM + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.a on # ACPI + irq 0xe6 = 0x0a + irq 0xe7 = 0x11 + irq 0xec = 0x80 + irq 0xf2 = 0x5d + end + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + irq 0xf0 = 0x7e + end + device pnp 2e.d off end # BCLK/WDT2/WDT_MEM + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID/PORT 80 + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 off end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end # superio/nuvoton/nct5539d + end # SSDT gen + end # superio/common + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on # Intel HDA + register "PchHdaVcType" = "Vc1" + end + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/asus/h110t/dsdt.asl b/src/mainboard/asus/h110t/dsdt.asl new file mode 100644 index 0000000..32e22b3 --- /dev/null +++ b/src/mainboard/asus/h110t/dsdt.asl @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + #include <soc/intel/common/acpi/platform.asl> + #include <soc/intel/skylake/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + /* Image processing unit */ + #include <soc/intel/skylake/acpi/ipu.asl> + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + // Dynamic Platform Thermal Framework + #include "acpi/dptf.asl" + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/asus/h110t/gma-mainboard.ads b/src/mainboard/asus/h110t/gma-mainboard.ads new file mode 100644 index 0000000..7bf6d97 --- /dev/null +++ b/src/mainboard/asus/h110t/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + DP1, + LVDS, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/h110t/hda_verb.c b/src/mainboard/asus/h110t/hda_verb.c new file mode 100644 index 0000000..136c60a --- /dev/null +++ b/src/mainboard/asus/h110t/hda_verb.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek ALC887 */ + 0x10438445, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x10438445), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014020), + AZALIA_PIN_CFG(0, 0x15, 0x90170110), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214030), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4026c629), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[] = {}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/h110t/include/gpio.h b/src/mainboard/asus/h110t/include/gpio.h new file mode 100644 index 0000000..ee33999 --- /dev/null +++ b/src/mainboard/asus/h110t/include/gpio.h @@ -0,0 +1,637 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <gpio.h> + +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + _PAD_CFG_STRUCT(GPP_A0, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* RCIN# */ + _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), + PAD_PULL(UP_20K)), /* LAD0 */ + _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), + PAD_PULL(UP_20K)), /* LAD1 */ + _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), + PAD_PULL(UP_20K)), /* LAD2 */ + _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), + PAD_PULL(UP_20K)), /* LAD3 */ + _PAD_CFG_STRUCT(GPP_A5, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* LFRAME# */ + _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), + 0), /* SERIRQ */ + _PAD_CFG_STRUCT(GPP_A7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A8, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A9, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_PULL(DN_20K)), /* CLKOUT_LPC0 */ + _PAD_CFG_STRUCT(GPP_A10, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_PULL(DN_20K)), /* CLKOUT_LPC1 */ + _PAD_CFG_STRUCT(GPP_A11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + PAD_PULL(UP_20K)), /* PME# */ + _PAD_CFG_STRUCT(GPP_A12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* SUSWARN#/SUSPWRDNACK */ + _PAD_CFG_STRUCT(GPP_A14, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A15, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_PULL(UP_20K)), /* SUS_ACK# */ + _PAD_CFG_STRUCT(GPP_A16, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A17, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A18, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A19, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPO(GPP_A20, 0, PLTRST), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A21, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A22, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, PLTRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_B ------- */ + _PAD_CFG_STRUCT(GPP_B0, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B1, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B2, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B3, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B4, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B8, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B10, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B11, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* PLTRST# */ + _PAD_CFG_STRUCT(GPP_B14, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_PULL(DN_20K)), /* SPKR */ + _PAD_CFG_STRUCT(GPP_B15, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPO(GPP_B16, 0, PLTRST), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B17, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B18, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B19, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B20, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B21, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B22, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + _PAD_CFG_STRUCT(GPP_C0, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) + | (1 << 1), + 0), /* SMBCLK */ + _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), + 0), /* SMBDATA */ + _PAD_CFG_STRUCT(GPP_C2, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C3, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) + | (1 << 1), + 0), /* SML0CLK */ + _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), + 0), /* SML0DATA */ + _PAD_CFG_STRUCT(GPP_C5, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C10, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C11, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C13, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C15, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C16, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C17, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C20, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C21, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C22, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) + | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) + | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), + 0), /* GPIO */ + + /* ------- GPIO Group GPP_D ------- */ + _PAD_CFG_STRUCT(GPP_D0, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D2, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D3, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D4, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) + | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D9, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D10, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D11, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D12, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + PAD_PULL(DN_20K)), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D15, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D16, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D18, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D19, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, PLTRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_E0, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E8, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* SATA_LED# */ + _PAD_CFG_STRUCT(GPP_E9, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* USB_OC0# */ + _PAD_CFG_STRUCT(GPP_E10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* USB_OC1# */ + _PAD_CFG_STRUCT(GPP_E11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* USB_OC2# */ + _PAD_CFG_STRUCT(GPP_E12, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* USB_OC3# */ + + /* ------- GPIO Group GPP_F ------- */ + _PAD_CFG_STRUCT(GPP_F0, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F1, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + PAD_PULL(UP_20K)), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F2, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + PAD_PULL(UP_20K)), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F5, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F15, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* USB_OC4# */ + _PAD_CFG_STRUCT(GPP_F16, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F17, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F18, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F19, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* eDP_VDDEN */ + _PAD_CFG_STRUCT(GPP_F20, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* eDP_BKLTEN */ + _PAD_CFG_STRUCT(GPP_F21, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* eDP_BKLTCTL */ + PAD_CFG_GPI_TRIG_OWN(GPP_F22, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + + /* ------- GPIO Group GPP_G ------- */ + _PAD_CFG_STRUCT(GPP_G0, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G2, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G3, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G4, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G5, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G9, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G10, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G15, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G17, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G18, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G19, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G20, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G22, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H1, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) + | (1 << 1), + 0), /* SRCCLKREQ7# */ + PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H3, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H4, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H5, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H9, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H10, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H11, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H13, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H16, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H17, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H20, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H21, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + + /* ------- GPIO Community 2 ------- */ + + /* -------- GPIO Group GPD -------- */ + _PAD_CFG_STRUCT(GPD0, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD1, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), + 0), /* LAN_WAKE# */ + _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), + PAD_PULL(UP_20K)), /* PWRBTN# */ + _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* SLP_S3# */ + _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* SLP_S4# */ + _PAD_CFG_STRUCT(GPD6, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1) | 1, + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD8, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD10, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD11, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* LANPHYPC */ + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + _PAD_CFG_STRUCT(GPP_I0, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* DDPB_HPD0 */ + _PAD_CFG_STRUCT(GPP_I1, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* DDPC_HPD1 */ + _PAD_CFG_STRUCT(GPP_I2, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* DDPD_HPD2 */ + _PAD_CFG_STRUCT(GPP_I3, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* DDPE_HPD3 */ + _PAD_CFG_STRUCT(GPP_I4, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* EDP_HPD */ + _PAD_CFG_STRUCT(GPP_I5, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* DDPB_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I6, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_PULL(DN_20K)), /* DDPB_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I7, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* DDPC_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I8, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_PULL(DN_20K)), /* DDPC_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I9, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* DDPD_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I10, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + PAD_PULL(DN_20K)), /* DDPD_CTRLDATA */ +}; + +static const struct pad_config early_gpio_table[] = { + + /* ------- GPIO Group GPP_A ------- */ + _PAD_CFG_STRUCT(GPP_A0, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* RCIN# */ + _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), + PAD_PULL(UP_20K)), /* LAD0 */ + _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), + PAD_PULL(UP_20K)), /* LAD1 */ + _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), + PAD_PULL(UP_20K)), /* LAD2 */ + _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), + PAD_PULL(UP_20K)), /* LAD3 */ + _PAD_CFG_STRUCT(GPP_A5, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* LFRAME# */ + _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), + 0), /* SERIRQ */ + _PAD_CFG_STRUCT(GPP_A7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A8, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A9, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_PULL(DN_20K)), /* CLKOUT_LPC0 */ + _PAD_CFG_STRUCT(GPP_A10, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_PULL(DN_20K)), /* CLKOUT_LPC1 */ + _PAD_CFG_STRUCT(GPP_A11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + PAD_PULL(UP_20K)), /* PME# */ + _PAD_CFG_STRUCT(GPP_A12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* SUSWARN#/SUSPWRDNACK */ + _PAD_CFG_STRUCT(GPP_A14, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A15, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_PULL(UP_20K)), /* SUS_ACK# */ +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/asus/h110t/mainboard.c b/src/mainboard/asus/h110t/mainboard.c new file mode 100644 index 0000000..203c5e3 --- /dev/null +++ b/src/mainboard/asus/h110t/mainboard.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <drivers/intel/i210/i210.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + +enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6]) +{ + /* TODO */ + mac[0] = 0xFF; + mac[1] = 0xFF; + mac[2] = 0xFF; + mac[3] = 0xFF; + mac[4] = 0xFF; + mac[5] = 0xFF; + return CB_SUCCESS; +} diff --git a/src/mainboard/asus/h110t/ramstage.c b/src/mainboard/asus/h110t/ramstage.c new file mode 100644 index 0000000..9d3933c --- /dev/null +++ b/src/mainboard/asus/h110t/ramstage.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> +#include "include/gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/asus/h110t/romstage.c b/src/mainboard/asus/h110t/romstage.c new file mode 100644 index 0000000..7c532e4 --- /dev/null +++ b/src/mainboard/asus/h110t/romstage.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <soc/romstage.h> +#include <stdint.h> +#include <string.h> +#include <spd_bin.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const u16 rcomp_resistors[3] = {121, 75, 100}; + + const u16 rcomp_targets[5] = {50, 26, 20, 20, 26}; + + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + + struct spd_block blk = { + .addr_map = {0x50, 0x52}, + }; + + assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors)); + assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets)); + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; + dump_spd_info(&blk); + + memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget)); + + /* use virtual channel 1 for the dmi interface of the PCH */ + mupd->FspmTestConfig.DmiVc1 = 1; + + /* desktop type */ + mem_cfg->UserBd = BOARD_TYPE_DESKTOP; +}
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48648 )
Change subject: mb/asus: Add ASUS H110T mainboard ......................................................................
Patch Set 1: Code-Review+1
(10 comments)
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/Kc... File src/mainboard/asus/h110t/Kconfig:
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/Kc... PS1, Line 4: : select BOARD_ROMSIZE_KB_16384 : select HAVE_ACPI_RESUME : select HAVE_ACPI_TABLES : select HAVE_OPTION_TABLE : select HAVE_CMOS_DEFAULT : select INTEL_GMA_HAVE_VBT : select INTEL_INT15 : select SOC_INTEL_KABYLAKE : select SKYLAKE_SOC_PCH_H : select SUPERIO_NUVOTON_COMMON_COM_A : select SUPERIO_NUVOTON_NCT5539D : select REALTEK_8168_RESET : select RT8168_SET_LED_MODE : select MAINBOARD_USES_IFD_GBE_REGION : select DRIVER_INTEL_I210 : select MAINBOARD_HAS_LPC_TPM Please order alphabetically
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/Kc... PS1, Line 38: config DEVICETREE : string : default "devicetree.cb" Remove, devicetree.cb is the default
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/bo... File src/mainboard/asus/h110t/board_info.txt:
PS1: Board name and Vendor name missing
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/de... File src/mainboard/asus/h110t/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/de... PS1, Line 5: register "deep_s3_enable_ac" = "0" : register "deep_s3_enable_dc" = "0" : register "deep_s5_enable_ac" = "0" : register "deep_s5_enable_dc" = "0" Remove, 0 is the default
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/ds... File src/mainboard/asus/h110t/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/ds... PS1, Line 7: 0x02, // DSDT revision: ACPI v2.0 and up Usually, we use the defines here.
ACPI_DSDT_REV_2
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/ds... PS1, Line 8: "COREv4", // OEM id OEM_ID
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/ds... PS1, Line 9: "COREBOOT", // OEM table id ACPI_TABLE_CREATOR
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/ma... File src/mainboard/asus/h110t/mainboard.c:
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/ma... PS1, Line 14: mainboard_enable enable_mainboard
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/ra... File src/mainboard/asus/h110t/ramstage.c:
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/ra... PS1, Line 10: gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); Add the following hook to mainboard_ops and do the GPIO configuration there:
.init = init_mainboard
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/ro... File src/mainboard/asus/h110t/romstage.c:
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/ro... PS1, Line 6: include <string.h> Is this used?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48648 )
Change subject: mb/asus: Add ASUS H110T mainboard ......................................................................
Patch Set 1:
(15 comments)
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/Kc... File src/mainboard/asus/h110t/Kconfig:
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/Kc... PS1, Line 19: select DRIVER_INTEL_I210 This board has two NICs, right? I see two Ethernet ports. I find it weird that they are different, though.
If one of them shows up as PCI bus:dev.fun 00:1f.6 with vendor firmware, it's not i210 but the in-PCH GbE NIC, and you would want to enable the corresponding device in devicetree.cb
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/cm... File src/mainboard/asus/h110t/cmos.layout:
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/cm... PS1, Line 6: #start-bit length config config-ID name : #0 8 r 0 seconds : #8 8 r 0 alarm_seconds : #16 8 r 0 minutes : #24 8 r 0 alarm_minutes : #32 8 r 0 hours : #40 8 r 0 alarm_hours : #48 8 r 0 day_of_week : #56 8 r 0 day_of_month : #64 8 r 0 month : #72 8 r 0 year : # ----------------------------------------------------------------- : # Status Register A : #80 4 r 0 rate_select : #84 3 r 0 REF_Clock : #87 1 r 0 UIP : # ----------------------------------------------------------------- : # Status Register B : #88 1 r 0 auto_switch_DST : #89 1 r 0 24_hour_mode : #90 1 r 0 binary_values_enable : #91 1 r 0 square-wave_out_enable : #92 1 r 0 update_finished_enable : #93 1 r 0 alarm_interrupt_enable : #94 1 r 0 periodic_interrupt_enable : #95 1 r 0 disable_clock_updates : # ----------------------------------------------------------------- : # Status Register C : #96 4 r 0 status_c_rsvd : #100 1 r 0 uf_flag : #101 1 r 0 af_flag : #102 1 r 0 pf_flag : #103 1 r 0 irqf_flag : # ----------------------------------------------------------------- : # Status Register D : #104 7 r 0 status_d_rsvd : #111 1 r 0 valid_cmos_ram : # ----------------------------------------------------------------- : # Diagnostic Status Register : #112 8 r 0 diag_rsvd1 Please drop this
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/cm... PS1, Line 48: For consistency, align columns with tabs
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/cm... PS1, Line 49: #120 264 r 0 unused Drop unused and commented-out lines too
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/cm... PS1, Line 77: # SandyBridge MRC Scrambler Seed values : #896 32 r 0 mrc_scrambler_seed : #928 32 r 0 mrc_scrambler_seed_s3 Not Sandy Bridge, please drop
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/cm... PS1, Line 83: #1000 24 r 0 amd_reserved Meaningless on Intel, can drop too
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/de... File src/mainboard/asus/h110t/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/de... PS1, Line 46: # Asus specific Yeah, subsystem IDs are OEM-specific. No need to add this comment
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/de... PS1, Line 64: register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" nit: add a blank line to separate USB2 from USB3
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/de... PS1, Line 82: on nit: To preserve alignment, I would add an extra space after `on`
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/de... PS1, Line 87: # SATA nit: same here, I'd align the comment with the previous lines
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/de... PS1, Line 99: register "PcieRpClkReqSupport[0]" = "1" You'd want to specify which ClkReq pin is to be used for this root port.
WARNING: Root ports are numbered starting from 1, but device functions and array indices start at zero. It's easy to get the numbers mixed up.
NOTE: if root ports aren't working as expected, check if root port functions have been swapped. With vendor firmware, if the device ID for 1c.0 is that of root port #5, functions have definitely been swapped.
FSP does its own function swapping, then coreboot updates the devicetree accounting for what FSP did. In my example, one would use `device pci 1c.4 on` and `4` for the array index.
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/de... PS1, Line 126: 2e.ff 2e.0 ?
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/ds... File src/mainboard/asus/h110t/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/ds... PS1, Line 20: /* Image processing unit */ : #include <soc/intel/skylake/acpi/ipu.asl> IPU isn't used on this board (it's for camera stuff)
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/gm... File src/mainboard/asus/h110t/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/gm... PS1, Line 11: ports : constant Port_List := : (HDMI1, : DP1, : LVDS, : others => Disabled); For Ada, we use three spaces for indentation
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/ro... File src/mainboard/asus/h110t/romstage.c:
https://review.coreboot.org/c/coreboot/+/48648/1/src/mainboard/asus/h110t/ro... PS1, Line 6: include <string.h>
Is this used?
memcpy prototype is in string.h
https://man7.org/linux/man-pages/man3/memcpy.3.html
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/asus: Add ASUS H110T mainboard ......................................................................
mb/asus: Add ASUS H110T mainboard
Work in Progress.
This initial commit isn't yet fully working but in order to get it sorted it is pushed already.
As the IGD and serial line aren't fully working yet, it is hard to tell what parts of the hardware already work and which don't.
Tested payloads so far: coreinfo and tianocore.
Signed-off-by: Marvin Drees marvin@ceres-sys.de Change-Id: Iab30596f2a12931679687c9f56427712b65f9363 --- A src/mainboard/asus/h110t/Kconfig A src/mainboard/asus/h110t/Kconfig.name A src/mainboard/asus/h110t/Makefile.inc A src/mainboard/asus/h110t/acpi/dptf.asl A src/mainboard/asus/h110t/acpi/ec.asl A src/mainboard/asus/h110t/acpi/mainboard.asl A src/mainboard/asus/h110t/acpi/superio.asl A src/mainboard/asus/h110t/board_info.txt A src/mainboard/asus/h110t/bootblock.c A src/mainboard/asus/h110t/cmos.default A src/mainboard/asus/h110t/cmos.layout A src/mainboard/asus/h110t/data.vbt A src/mainboard/asus/h110t/devicetree.cb A src/mainboard/asus/h110t/dsdt.asl A src/mainboard/asus/h110t/gma-mainboard.ads A src/mainboard/asus/h110t/hda_verb.c A src/mainboard/asus/h110t/include/gpio.h A src/mainboard/asus/h110t/mainboard.c A src/mainboard/asus/h110t/ramstage.c A src/mainboard/asus/h110t/romstage.c 20 files changed, 1,218 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/48648/2
Attention is currently required from: Felix Singer. Marvin Drees has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48648 )
Change subject: mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
Patch Set 6:
(5 comments)
This change is ready for review.
File src/mainboard/asus/sklkbl_h/include/mainboard/gpio.h:
PS4:
Rename this file to variant/gpio.h to make clear that these methods are called from variants.
Done
https://review.coreboot.org/c/coreboot/+/48648/comment/dfb7c2ff_61c1f459 PS4, Line 6: mainboard_early_config_gpios
variant
Done
https://review.coreboot.org/c/coreboot/+/48648/comment/d706967a_8038b4e8 PS4, Line 6: void mainboard_early_config_gpios(void);
We already use variant_configure_early_gpios for other boards. […]
Might be a good idea to move these into common code. I'm not sure if the gpio_early function is actually needed on this one as UART is handled by the superio. Currently trying to figure that out and so far it seems to boot even without specifying gpios early.
https://review.coreboot.org/c/coreboot/+/48648/comment/9d0c9b0b_3d73ca29 PS4, Line 7: void mainboard_config_gpios(void);
variant
Done
File src/mainboard/asus/sklkbl_h/variants/h110t/board_info.txt:
https://review.coreboot.org/c/coreboot/+/48648/comment/0f404716_ae174c6d PS4, Line 1: Category: desktop : Vendor name: Asus
Remove
Done
Attention is currently required from: Felix Singer, Maxim Polyakov, Angel Pons. Marvin Drees has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48648 )
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
Patch Set 9:
(1 comment)
This change is ready for review.
File src/mainboard/asus/h110t/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48648/comment/048a58a3_9e5b7220 PS1, Line 99: register "PcieRpClkReqSupport[0]" = "1"
You'd want to specify which ClkReq pin is to be used for this root port. […]
Ack
Attention is currently required from: Felix Singer, Maxim Polyakov, Angel Pons. Marvin Drees has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48648 )
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
Patch Set 9:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48648/comment/848f3eda_ae8b8648 PS4, Line 16: Finish the overridetree
There's no way to tell what should go into devicetree.cb and what should go into overridetree. […]
Would it make sense to rather not define a global devicetree and overridetrees for the variants but rather define an independant devicetree for each variant?
Commit Message:
https://review.coreboot.org/c/coreboot/+/48648/comment/c4f16a24_279f84ff PS9, Line 13: - Correct UART Output (Output seems to have wrong BAUD, Would it be helpful to provide the garbled output via a pastebin? Otherwise I could also provide the console output via the SPI flash dump. I'm also working with the datasheet of a slightly different chip as the NCT5539D one isn't available to me.
Attention is currently required from: Felix Singer, Maxim Polyakov, Angel Pons. Marvin Drees has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48648 )
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48648/comment/f79da14b_298134dc PS9, Line 13: - Correct UART Output (Output seems to have wrong BAUD,
Would it be helpful to provide the garbled output via a pastebin? Otherwise I could also provide the […]
EDIT: Just received insight to the correct datasheet
Attention is currently required from: Felix Singer, Maxim Polyakov, Angel Pons. Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, Maxim Polyakov, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48648
to look at the new patch set (#10).
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
[WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards
Currently WIP: H110T Next: Q170T (Same issues currently)
Not working yet: - Correct UART Output (Output seems to have wrong BAUD, correct values couldn't be determined yet) - IGD Output (No signal on both DP and HDMI)
TODO: - Fill devicetree more (Most notably USB OC pins and superio) - Figure out UART (done by superio NCT5539D which seems rarely used on other boards) - See if gpio_early can be removed (probably not, as superio depends on some straps according to datasheet) - Figure out why system_reset() gets called during FSP MemoryInit on cold boot once - DPTF and other miscellaneous features
Latest log: https://pastebin.com/raw/Ku9M9d6G
Change-Id: Iab30596f2a12931679687c9f56427712b65f9363 Signed-off-by: Marvin Drees marvin@ceres-sys.de --- A src/mainboard/asus/sklkbl_h/Kconfig A src/mainboard/asus/sklkbl_h/Kconfig.name A src/mainboard/asus/sklkbl_h/Makefile.inc A src/mainboard/asus/sklkbl_h/acpi/dptf.asl A src/mainboard/asus/sklkbl_h/acpi/ec.asl A src/mainboard/asus/sklkbl_h/acpi/superio.asl A src/mainboard/asus/sklkbl_h/board_info.txt A src/mainboard/asus/sklkbl_h/bootblock.c A src/mainboard/asus/sklkbl_h/cmos.default A src/mainboard/asus/sklkbl_h/cmos.layout A src/mainboard/asus/sklkbl_h/devicetree.cb A src/mainboard/asus/sklkbl_h/dsdt.asl A src/mainboard/asus/sklkbl_h/fadt.c A src/mainboard/asus/sklkbl_h/include/variant/gpio.h A src/mainboard/asus/sklkbl_h/include/variant/superio.h A src/mainboard/asus/sklkbl_h/ramstage.c A src/mainboard/asus/sklkbl_h/romstage.c A src/mainboard/asus/sklkbl_h/variants/h110t/board_info.txt A src/mainboard/asus/sklkbl_h/variants/h110t/data.vbt A src/mainboard/asus/sklkbl_h/variants/h110t/gma-mainboard.ads A src/mainboard/asus/sklkbl_h/variants/h110t/gpio.c A src/mainboard/asus/sklkbl_h/variants/h110t/gpio_early.c A src/mainboard/asus/sklkbl_h/variants/h110t/hda_verb.c A src/mainboard/asus/sklkbl_h/variants/h110t/overridetree.cb A src/mainboard/asus/sklkbl_h/variants/h110t/superio.c 25 files changed, 1,880 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/48648/10
Attention is currently required from: Felix Singer, Maxim Polyakov, Angel Pons. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48648 )
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
Patch Set 10:
(4 comments)
File src/mainboard/asus/sklkbl_h/fadt.c:
https://review.coreboot.org/c/coreboot/+/48648/comment/0beb9a36_f5eb0b44 PS10, Line 8: fadt->preferred_pm_profile = PM_DESKTOP; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/48648/comment/6ed9a716_72259f05 PS10, Line 8: fadt->preferred_pm_profile = PM_DESKTOP; please, no spaces at the start of a line
File src/mainboard/asus/sklkbl_h/variants/h110t/gpio_early.c:
https://review.coreboot.org/c/coreboot/+/48648/comment/4b560c2b_d7452c6c PS10, Line 106: gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/48648/comment/86a878f0_2da2f1fa PS10, Line 106: gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); please, no spaces at the start of a line
Attention is currently required from: Felix Singer, Maxim Polyakov, Sumeet R Pawnikar, Marvin Drees. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48648 )
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
Patch Set 12:
(5 comments)
File src/mainboard/asus/sklkbl_h/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48648/comment/7a01db99_f8b13063 PS12, Line 7: register "SaGv" = "SaGv_Enabled" Only matters for ULT, remove.
https://review.coreboot.org/c/coreboot/+/48648/comment/deef2fc8_c53a9694 PS12, Line 13: register "s0ix_enable" = "1" Remove, S0ix can cause issues and only makes sense on mobile platforms anyway
File src/mainboard/asus/sklkbl_h/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/48648/comment/b0dc770b_dce82e31 PS12, Line 25: #include "acpi/dptf.asl" // TODO Is DPTF meant for desktop boards as well? I don't think so. I'd remove this and the empty file
File src/mainboard/asus/sklkbl_h/fadt.c:
https://review.coreboot.org/c/coreboot/+/48648/comment/04b4b5e0_de74bd4c PS12, Line 8: fadt->preferred_pm_profile = PM_DESKTOP; Shouldn't be needed
File src/mainboard/asus/sklkbl_h/variants/h110t/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/48648/comment/4b6f9920_3652c31c PS12, Line 20: register "SendVrMbxCmd" = "2" If you copied this from another board, try without. I really doubt this applies to your board.
Attention is currently required from: Angel Pons. Marvin Drees has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48648 )
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
Patch Set 15:
(8 comments)
This change is ready for review.
Commit Message:
https://review.coreboot.org/c/coreboot/+/48648/comment/3afcfae8_9da41f34 PS4, Line 16: Finish the overridetree
Would it make sense to rather not define a global devicetree and overridetrees for the variants but […]
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/48648/comment/8ea51acf_e6adcfc4 PS9, Line 13: - Correct UART Output (Output seems to have wrong BAUD,
EDIT: Just received insight to the correct datasheet
Done
File src/mainboard/asus/h110t/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48648/comment/7e0eaf1f_a92025c1 PS1, Line 99: register "PcieRpClkReqSupport[0]" = "1"
Ack
Done
File src/mainboard/asus/sklkbl_h/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48648/comment/bcadece1_1d7c3af6 PS12, Line 7: register "SaGv" = "SaGv_Enabled"
Only matters for ULT, remove.
Done
https://review.coreboot.org/c/coreboot/+/48648/comment/2feaf304_b8802017 PS12, Line 13: register "s0ix_enable" = "1"
Remove, S0ix can cause issues and only makes sense on mobile platforms anyway
Done
File src/mainboard/asus/sklkbl_h/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/48648/comment/7fbd0827_df1210ec PS12, Line 25: #include "acpi/dptf.asl" // TODO Is DPTF meant for desktop boards as well?
I don't think so. […]
Done
File src/mainboard/asus/sklkbl_h/fadt.c:
https://review.coreboot.org/c/coreboot/+/48648/comment/33bb7cd3_54fcdd51 PS12, Line 8: fadt->preferred_pm_profile = PM_DESKTOP;
Shouldn't be needed
Done
File src/mainboard/asus/sklkbl_h/variants/h110t/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/48648/comment/7b26302d_b94de375 PS12, Line 20: register "SendVrMbxCmd" = "2"
If you copied this from another board, try without. I really doubt this applies to your board.
Done
Attention is currently required from: Angel Pons. Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48648
to look at the new patch set (#16).
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
[WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards
Currently WIP: H110T Next: Q170T (Same issues currently)
Working: - Booting into SeaBIOS - Booting into TianoCore - UART (uses 12V RS232 levels!)
Not working yet: - IGD Output (No signal on both DP and HDMI)
TODO: - Fill devicetree more (Most notably USB OC pins and superio) - See if gpio_early can be removed (probably not, as superio depends on some straps according to datasheet) - Figure out why system_reset() gets called during FSP MemoryInit on cold boot once
Notes: - EM100 usage flakey
Change-Id: Iab30596f2a12931679687c9f56427712b65f9363 Signed-off-by: Marvin Drees marvin@ceres-sys.de --- A src/mainboard/asus/sklkbl_h/Kconfig A src/mainboard/asus/sklkbl_h/Kconfig.name A src/mainboard/asus/sklkbl_h/Makefile.inc A src/mainboard/asus/sklkbl_h/acpi/ec.asl A src/mainboard/asus/sklkbl_h/acpi/superio.asl A src/mainboard/asus/sklkbl_h/board_info.txt A src/mainboard/asus/sklkbl_h/bootblock.c A src/mainboard/asus/sklkbl_h/cmos.default A src/mainboard/asus/sklkbl_h/cmos.layout A src/mainboard/asus/sklkbl_h/dsdt.asl A src/mainboard/asus/sklkbl_h/include/variant/gpio.h A src/mainboard/asus/sklkbl_h/include/variant/superio.h A src/mainboard/asus/sklkbl_h/ramstage.c A src/mainboard/asus/sklkbl_h/romstage.c A src/mainboard/asus/sklkbl_h/variants/h110t/board_info.txt A src/mainboard/asus/sklkbl_h/variants/h110t/data.vbt A src/mainboard/asus/sklkbl_h/variants/h110t/devicetree.cb A src/mainboard/asus/sklkbl_h/variants/h110t/gma-mainboard.ads A src/mainboard/asus/sklkbl_h/variants/h110t/gpio.c A src/mainboard/asus/sklkbl_h/variants/h110t/gpio_early.c A src/mainboard/asus/sklkbl_h/variants/h110t/hda_verb.c A src/mainboard/asus/sklkbl_h/variants/h110t/superio.c 22 files changed, 1,783 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/48648/16
Attention is currently required from: Felix Singer, Angel Pons. Marvin Drees has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48648 )
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
Patch Set 16:
(1 comment)
File src/mainboard/asus/h110t/Kconfig:
https://review.coreboot.org/c/coreboot/+/48648/comment/2e4b4100_6727bd8b PS1, Line 4: : select BOARD_ROMSIZE_KB_16384 : select HAVE_ACPI_RESUME : select HAVE_ACPI_TABLES : select HAVE_OPTION_TABLE : select HAVE_CMOS_DEFAULT : select INTEL_GMA_HAVE_VBT : select INTEL_INT15 : select SOC_INTEL_KABYLAKE : select SKYLAKE_SOC_PCH_H : select SUPERIO_NUVOTON_COMMON_COM_A : select SUPERIO_NUVOTON_NCT5539D : select REALTEK_8168_RESET : select RT8168_SET_LED_MODE : select MAINBOARD_USES_IFD_GBE_REGION : select DRIVER_INTEL_I210 : select MAINBOARD_HAS_LPC_TPM
Please order alphabetically
Done
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Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
Patch Set 16:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48648/comment/2fdb3564_d0635d68 PS16, Line 24: - Figure out why system_reset() gets called during : FSP MemoryInit on cold boot once If by "cold boot" you mean after the power supply was unplugged, it's completely normal.
I'm pretty sure it's the same as on Haswell, where the ME needs a `system_reset()` to perform "dynamic fusing". I don't know what exactly this "dynamic fusing" does, but it updates the CAPID0 register in the host bridge's PCI config space, most likely according to the capabilities of the processor and PCH. I think this is how Intel restricts memory overclocking to mainboards with a Z-series PCH, among other things.
Attention is currently required from: Felix Singer, Angel Pons. Marvin Drees has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48648 )
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
Patch Set 16:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48648/comment/edd7a8c9_209a868a PS16, Line 24: - Figure out why system_reset() gets called during : FSP MemoryInit on cold boot once
If by "cold boot" you mean after the power supply was unplugged, it's completely normal. […]
Ack
Attention is currently required from: Felix Singer, Angel Pons, Marvin Drees. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48648 )
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
Patch Set 16:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48648/comment/53dabd73_d3857829 PS16, Line 28: - EM100 usage flakey It’d be great if you elaborated a little.
Attention is currently required from: Felix Singer, Paul Menzel, Angel Pons. Marvin Drees has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48648 )
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
Patch Set 16:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48648/comment/1a870294_bf291142 PS16, Line 28: - EM100 usage flakey
It’d be great if you elaborated a little.
First I need to run "make" twice so the ifdtool actually modifies the values, second even if the image is modified to run at lower speeds sometimes it wouldn't start and the trace output of the em100 shows "unknown instruction" several times followed by "chip erase" several times. These issues can't reliably be reproduced though, they only happen every 1 out of 5 tries roughly, that's why I just called it flakey.
Attention is currently required from: Felix Singer, Paul Menzel, Angel Pons. Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48648
to look at the new patch set (#17).
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
[WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards
Currently WIP: H110T Next: Q170T (Same issues currently)
Working: - Booting into SeaBIOS - Booting into TianoCore - Booting into LinuxBoot - UART (uses 12V RS232 levels!)
Not working yet: - IGD Output (No signal on both DP and HDMI)
TODO: - Fill devicetree more (Most notably USB OC pins and superio) - See if gpio_early can be removed (probably not, as superio depends on some straps according to datasheet)
Notes: - EM100 usage flakey
Change-Id: Iab30596f2a12931679687c9f56427712b65f9363 Signed-off-by: Marvin Drees marvin@ceres-sys.de --- A src/mainboard/asus/sklkbl_h/Kconfig A src/mainboard/asus/sklkbl_h/Kconfig.name A src/mainboard/asus/sklkbl_h/Makefile.inc A src/mainboard/asus/sklkbl_h/acpi/ec.asl A src/mainboard/asus/sklkbl_h/acpi/superio.asl A src/mainboard/asus/sklkbl_h/board_info.txt A src/mainboard/asus/sklkbl_h/bootblock.c A src/mainboard/asus/sklkbl_h/cmos.default A src/mainboard/asus/sklkbl_h/cmos.layout A src/mainboard/asus/sklkbl_h/dsdt.asl A src/mainboard/asus/sklkbl_h/include/variant/gpio.h A src/mainboard/asus/sklkbl_h/include/variant/superio.h A src/mainboard/asus/sklkbl_h/ramstage.c A src/mainboard/asus/sklkbl_h/romstage.c A src/mainboard/asus/sklkbl_h/variants/h110t/board_info.txt A src/mainboard/asus/sklkbl_h/variants/h110t/data.vbt A src/mainboard/asus/sklkbl_h/variants/h110t/devicetree.cb A src/mainboard/asus/sklkbl_h/variants/h110t/gma-mainboard.ads A src/mainboard/asus/sklkbl_h/variants/h110t/gpio.c A src/mainboard/asus/sklkbl_h/variants/h110t/gpio_early.c A src/mainboard/asus/sklkbl_h/variants/h110t/hda_verb.c A src/mainboard/asus/sklkbl_h/variants/h110t/superio.c 22 files changed, 1,783 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/48648/17
Attention is currently required from: Felix Singer, Paul Menzel, Angel Pons. Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48648
to look at the new patch set (#18).
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
[WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards
Currently WIP: H110T Next: Q170T (Same issues currently)
Working: - Booting into SeaBIOS - Booting into TianoCore - Booting into LinuxBoot - UART (uses 12V RS232 levels!)
Not working yet: - IGD Output (No signal on both DP and HDMI)
TODO: - Fill devicetree more (Most notably USB OC pins and superio) - See if gpio_early can be removed (probably not, as superio depends on some straps according to datasheet)
Notes: - EM100 usage flakey - Stripping ME causes the board to not boot at all (no UART output after modifying ME)
Change-Id: Iab30596f2a12931679687c9f56427712b65f9363 Signed-off-by: Marvin Drees marvin@ceres-sys.de --- A src/mainboard/asus/sklkbl_h/Kconfig A src/mainboard/asus/sklkbl_h/Kconfig.name A src/mainboard/asus/sklkbl_h/Makefile.inc A src/mainboard/asus/sklkbl_h/acpi/ec.asl A src/mainboard/asus/sklkbl_h/acpi/superio.asl A src/mainboard/asus/sklkbl_h/board_info.txt A src/mainboard/asus/sklkbl_h/bootblock.c A src/mainboard/asus/sklkbl_h/cmos.default A src/mainboard/asus/sklkbl_h/cmos.layout A src/mainboard/asus/sklkbl_h/dsdt.asl A src/mainboard/asus/sklkbl_h/include/variant/gpio.h A src/mainboard/asus/sklkbl_h/include/variant/superio.h A src/mainboard/asus/sklkbl_h/ramstage.c A src/mainboard/asus/sklkbl_h/romstage.c A src/mainboard/asus/sklkbl_h/variants/h110t/board_info.txt A src/mainboard/asus/sklkbl_h/variants/h110t/data.vbt A src/mainboard/asus/sklkbl_h/variants/h110t/devicetree.cb A src/mainboard/asus/sklkbl_h/variants/h110t/gma-mainboard.ads A src/mainboard/asus/sklkbl_h/variants/h110t/gpio.c A src/mainboard/asus/sklkbl_h/variants/h110t/gpio_early.c A src/mainboard/asus/sklkbl_h/variants/h110t/hda_verb.c A src/mainboard/asus/sklkbl_h/variants/h110t/superio.c 22 files changed, 1,783 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/48648/18
Attention is currently required from: Felix Singer, Angel Pons, Marvin Drees. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48648 )
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
Patch Set 18:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48648/comment/fd2e2a99_15fb380a PS18, Line 29: (no UART output after modifying ME) Does a “stripped ME” work with the vendor firmware?
Attention is currently required from: Felix Singer, Paul Menzel, Angel Pons. Marvin Drees has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48648 )
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
Patch Set 18:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48648/comment/fe1923f6_05f676a4 PS18, Line 29: (no UART output after modifying ME)
Does a “stripped ME” work with the vendor firmware?
It does not, the fan spins but that's about all that happens. No UART, no picture etc.
Attention is currently required from: Felix Singer, Paul Menzel, Angel Pons. Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48648
to look at the new patch set (#19).
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
[WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards
Currently WIP: H110T Next: Q170T (Same issues currently)
Working: - Booting into SeaBIOS - Booting into TianoCore - UART (uses 12V RS232 levels!) - HDMI and DP in Tianocore via libgfxinit
Not working: - Video in Linux
Untested: - USB - Ethernet - LVDS - Sound
TODO: - Fill devicetree more (Most notably USB OC pins and superio) - See if gpio_early can be removed (probably not, as superio depends on some straps according to datasheet)
Notes: - EM100 usage flakey - Stripping ME causes the board to not boot at all The same behaviour occurs with me_cleaned vendor firmware
Change-Id: Iab30596f2a12931679687c9f56427712b65f9363 Signed-off-by: Marvin Drees marvin@ceres-sys.de --- A src/mainboard/asus/sklkbl_h/Kconfig A src/mainboard/asus/sklkbl_h/Kconfig.name A src/mainboard/asus/sklkbl_h/Makefile.inc A src/mainboard/asus/sklkbl_h/acpi/ec.asl A src/mainboard/asus/sklkbl_h/acpi/superio.asl A src/mainboard/asus/sklkbl_h/board_info.txt A src/mainboard/asus/sklkbl_h/bootblock.c A src/mainboard/asus/sklkbl_h/cmos.default A src/mainboard/asus/sklkbl_h/cmos.layout A src/mainboard/asus/sklkbl_h/dsdt.asl A src/mainboard/asus/sklkbl_h/include/variant/gpio.h A src/mainboard/asus/sklkbl_h/include/variant/superio.h A src/mainboard/asus/sklkbl_h/ramstage.c A src/mainboard/asus/sklkbl_h/romstage.c A src/mainboard/asus/sklkbl_h/variants/h110t/board_info.txt A src/mainboard/asus/sklkbl_h/variants/h110t/data.vbt A src/mainboard/asus/sklkbl_h/variants/h110t/devicetree.cb A src/mainboard/asus/sklkbl_h/variants/h110t/gma-mainboard.ads A src/mainboard/asus/sklkbl_h/variants/h110t/gpio.c A src/mainboard/asus/sklkbl_h/variants/h110t/gpio_early.c A src/mainboard/asus/sklkbl_h/variants/h110t/hda_verb.c A src/mainboard/asus/sklkbl_h/variants/h110t/superio.c 22 files changed, 1,765 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/48648/19
Attention is currently required from: Felix Singer, Paul Menzel, Angel Pons. Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48648
to look at the new patch set (#20).
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
[WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards
Currently WIP: H110T Next: Q170T (Same issues currently)
Working: - Booting into SeaBIOS - Booting into TianoCore - UART (uses 12V RS232 levels!) - HDMI and DP in Tianocore via libgfxinit
Not working: - Booting Linux, resets at DMAR - Video in Linux
Untested: - USB - Ethernet - LVDS - Sound
TODO: - Fill devicetree more (Most notably USB OC pins) - Fix bootloop
Notes: - EM100 usage flakey - Stripping ME causes the board to not boot at all The same behaviour occurs with me_cleaned vendor firmware
Change-Id: Iab30596f2a12931679687c9f56427712b65f9363 Signed-off-by: Marvin Drees marvin@ceres-sys.de --- A src/mainboard/asus/sklkbl_h/Kconfig A src/mainboard/asus/sklkbl_h/Kconfig.name A src/mainboard/asus/sklkbl_h/Makefile.inc A src/mainboard/asus/sklkbl_h/acpi/ec.asl A src/mainboard/asus/sklkbl_h/acpi/superio.asl A src/mainboard/asus/sklkbl_h/board_info.txt A src/mainboard/asus/sklkbl_h/bootblock.c A src/mainboard/asus/sklkbl_h/cmos.default A src/mainboard/asus/sklkbl_h/cmos.layout A src/mainboard/asus/sklkbl_h/dsdt.asl A src/mainboard/asus/sklkbl_h/include/variant/gpio.h A src/mainboard/asus/sklkbl_h/include/variant/superio.h A src/mainboard/asus/sklkbl_h/ramstage.c A src/mainboard/asus/sklkbl_h/romstage.c A src/mainboard/asus/sklkbl_h/variants/h110t/board_info.txt A src/mainboard/asus/sklkbl_h/variants/h110t/data.vbt A src/mainboard/asus/sklkbl_h/variants/h110t/devicetree.cb A src/mainboard/asus/sklkbl_h/variants/h110t/gma-mainboard.ads A src/mainboard/asus/sklkbl_h/variants/h110t/gpio.c A src/mainboard/asus/sklkbl_h/variants/h110t/gpio_early.c A src/mainboard/asus/sklkbl_h/variants/h110t/hda_verb.c A src/mainboard/asus/sklkbl_h/variants/h110t/superio.c 22 files changed, 1,778 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/48648/20
Attention is currently required from: Felix Singer, Paul Menzel, Angel Pons. Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48648
to look at the new patch set (#21).
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
[WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards
Currently WIP: H110T Next: Q170T (Same issues currently)
Working: - Booting into SeaBIOS - Booting into TianoCore - UART (uses 12V RS232 levels!) - HDMI and DP in Tianocore via libgfxinit
Not working: - Booting Linux, resets at DMAR - Video in Linux
Untested: - USB - Ethernet - LVDS - Sound
TODO: - Fill devicetree more (Most notably USB OC pins) - Fix bootloop
Notes: - EM100 usage flakey - Stripping ME causes the board to not boot at all The same behaviour occurs with me_cleaned vendor firmware
Change-Id: Iab30596f2a12931679687c9f56427712b65f9363 Signed-off-by: Marvin Drees marvin@ceres-sys.de --- A src/mainboard/asus/sklkbl_h/Kconfig A src/mainboard/asus/sklkbl_h/Kconfig.name A src/mainboard/asus/sklkbl_h/Makefile.inc A src/mainboard/asus/sklkbl_h/acpi/ec.asl A src/mainboard/asus/sklkbl_h/acpi/superio.asl A src/mainboard/asus/sklkbl_h/board_info.txt A src/mainboard/asus/sklkbl_h/bootblock.c A src/mainboard/asus/sklkbl_h/cmos.default A src/mainboard/asus/sklkbl_h/cmos.layout A src/mainboard/asus/sklkbl_h/dsdt.asl A src/mainboard/asus/sklkbl_h/include/variant/gpio.h A src/mainboard/asus/sklkbl_h/include/variant/superio.h A src/mainboard/asus/sklkbl_h/ramstage.c A src/mainboard/asus/sklkbl_h/romstage.c A src/mainboard/asus/sklkbl_h/variants/h110t/board_info.txt A src/mainboard/asus/sklkbl_h/variants/h110t/data.vbt A src/mainboard/asus/sklkbl_h/variants/h110t/devicetree.cb A src/mainboard/asus/sklkbl_h/variants/h110t/gma-mainboard.ads A src/mainboard/asus/sklkbl_h/variants/h110t/gpio.c A src/mainboard/asus/sklkbl_h/variants/h110t/gpio_early.c A src/mainboard/asus/sklkbl_h/variants/h110t/hda_verb.c A src/mainboard/asus/sklkbl_h/variants/h110t/superio.c 22 files changed, 1,778 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/48648/21
Attention is currently required from: Felix Singer, Paul Menzel, Angel Pons. Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, Maxim Polyakov, Sumeet R Pawnikar, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48648
to look at the new patch set (#22).
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
[WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards
Currently WIP: H110T Next: Q170T (Same issues currently)
Working: - Booting into SeaBIOS - Booting into TianoCore - UART (uses 12V RS232 levels!) - HDMI and DP in Tianocore via libgfxinit - TPM 2.0 - NVMe M.2
Not working: - Booting Linux, resets at DMAR - Video in Linux - USB (Needs devicetree entries)
Untested: - Ethernet (Needs working OS) - LVDS (No hardware to test) - Sound (Needs working OS) - M.2 E key slot (Needs working OS) - SATA (Needs working OS) - S3 sleep (Needs working OS)
TODO: - Fill devicetree more (Most notably USB OC pins) - Fix bootloop - Booting Memtest86 as the primary payload reveals that CPU0 is receiving an unexpected interrupt, causing it to reset.
Notes: - EM100 usage flakey (does quad IO even though IFD is modified not to) - Stripping ME causes the board to not boot at all. The same behaviour occurs with me_cleaned vendor firmware. But setting the HAP bit works and disables the ME.
Change-Id: Iab30596f2a12931679687c9f56427712b65f9363 Signed-off-by: Marvin Drees marvin@ceres-sys.de --- A src/mainboard/asus/sklkbl_h/Kconfig A src/mainboard/asus/sklkbl_h/Kconfig.name A src/mainboard/asus/sklkbl_h/Makefile.inc A src/mainboard/asus/sklkbl_h/acpi/ec.asl A src/mainboard/asus/sklkbl_h/acpi/superio.asl A src/mainboard/asus/sklkbl_h/board_info.txt A src/mainboard/asus/sklkbl_h/bootblock.c A src/mainboard/asus/sklkbl_h/cmos.default A src/mainboard/asus/sklkbl_h/cmos.layout A src/mainboard/asus/sklkbl_h/dsdt.asl A src/mainboard/asus/sklkbl_h/include/variant/gpio.h A src/mainboard/asus/sklkbl_h/include/variant/superio.h A src/mainboard/asus/sklkbl_h/ramstage.c A src/mainboard/asus/sklkbl_h/romstage.c A src/mainboard/asus/sklkbl_h/variants/h110t/board_info.txt A src/mainboard/asus/sklkbl_h/variants/h110t/data.vbt A src/mainboard/asus/sklkbl_h/variants/h110t/devicetree.cb A src/mainboard/asus/sklkbl_h/variants/h110t/gma-mainboard.ads A src/mainboard/asus/sklkbl_h/variants/h110t/gpio.c A src/mainboard/asus/sklkbl_h/variants/h110t/gpio_early.c A src/mainboard/asus/sklkbl_h/variants/h110t/hda_verb.c A src/mainboard/asus/sklkbl_h/variants/h110t/superio.c 22 files changed, 1,780 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/48648/22
Attention is currently required from: Felix Singer, Paul Menzel, Angel Pons. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48648 )
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
Patch Set 23: Verified+1
(18 comments)
File src/mainboard/asus/sklkbl_h/Kconfig:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-138348): https://review.coreboot.org/c/coreboot/+/48648/comment/34e38e10_aff0d200 PS23, Line 18: select SUPERIO_NUVOTON_COMMON_COM_A 'SUPERIO' may be misspelled - perhaps ''?
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-138348): https://review.coreboot.org/c/coreboot/+/48648/comment/76498d98_afea3aa2 PS23, Line 19: select SUPERIO_NUVOTON_NCT5539D 'SUPERIO' may be misspelled - perhaps ''?
File src/mainboard/asus/sklkbl_h/Makefile.inc:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-138348): https://review.coreboot.org/c/coreboot/+/48648/comment/0ccbc705_489d8268 PS23, Line 7: bootblock-y += variants/$(VARIANT_DIR)/superio.c 'superio' may be misspelled - perhaps ''?
File src/mainboard/asus/sklkbl_h/acpi/superio.asl:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-138348): https://review.coreboot.org/c/coreboot/+/48648/comment/6f3daaf2_9d2240e0 PS23, Line 3: #define SUPERIO_DEV SIO0 'SUPERIO' may be misspelled - perhaps ''?
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-138348): https://review.coreboot.org/c/coreboot/+/48648/comment/8c3347a3_95cdc199 PS23, Line 4: #define SUPERIO_PNP_BASE 0x2e 'SUPERIO' may be misspelled - perhaps ''?
File src/mainboard/asus/sklkbl_h/bootblock.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-138348): https://review.coreboot.org/c/coreboot/+/48648/comment/e3d19a9b_e6bccedd PS23, Line 5: #include <variant/superio.h> 'superio' may be misspelled - perhaps ''?
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-138348): https://review.coreboot.org/c/coreboot/+/48648/comment/3840b3c3_27eb319b PS23, Line 10: variant_early_configure_superio(); 'superio' may be misspelled - perhaps ''?
File src/mainboard/asus/sklkbl_h/include/variant/superio.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-138348): https://review.coreboot.org/c/coreboot/+/48648/comment/6c8a6a89_1d137f2d PS23, Line 3: #ifndef MAINBOARD_SUPERIO_H 'SUPERIO' may be misspelled - perhaps ''?
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-138348): https://review.coreboot.org/c/coreboot/+/48648/comment/0284ec8d_032123bc PS23, Line 4: #define MAINBOARD_SUPERIO_H 'SUPERIO' may be misspelled - perhaps ''?
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-138348): https://review.coreboot.org/c/coreboot/+/48648/comment/cc975eea_816b6382 PS23, Line 6: void variant_early_configure_superio(void); 'superio' may be misspelled - perhaps ''?
File src/mainboard/asus/sklkbl_h/variants/h110t/devicetree.cb:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-138348): https://review.coreboot.org/c/coreboot/+/48648/comment/e440cc5a_834ef901 PS23, Line 83: chip superio/common 'superio' may be misspelled - perhaps ''?
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-138348): https://review.coreboot.org/c/coreboot/+/48648/comment/11e4bff0_d62e1c2d PS23, Line 85: chip superio/nuvoton/nct5539d 'superio' may be misspelled - perhaps ''?
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-138348): https://review.coreboot.org/c/coreboot/+/48648/comment/918f8378_7f2fb4cc PS23, Line 152: end # superio/nuvoton/nct5539d 'superio' may be misspelled - perhaps ''?
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-138348): https://review.coreboot.org/c/coreboot/+/48648/comment/ff063b1d_f6b2d7e2 PS23, Line 154: end # superio/common 'superio' may be misspelled - perhaps ''?
File src/mainboard/asus/sklkbl_h/variants/h110t/superio.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-138348): https://review.coreboot.org/c/coreboot/+/48648/comment/b42fc56c_8f0b29ab PS23, Line 3: #include <superio/nuvoton/common/nuvoton.h> 'superio' may be misspelled - perhaps ''?
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-138348): https://review.coreboot.org/c/coreboot/+/48648/comment/3b924332_2407ac3c PS23, Line 4: #include <superio/nuvoton/nct5539d/nct5539d.h> 'superio' may be misspelled - perhaps ''?
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-138348): https://review.coreboot.org/c/coreboot/+/48648/comment/9c671df5_d8b093f1 PS23, Line 5: #include <variant/superio.h> 'superio' may be misspelled - perhaps ''?
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-138348): https://review.coreboot.org/c/coreboot/+/48648/comment/1808736a_576ec9ba PS23, Line 7: void variant_early_configure_superio(void) 'superio' may be misspelled - perhaps ''?
Attention is currently required from: Angel Pons, Felix Singer, Marvin Drees, Paul Menzel.
Felix Singer has uploaded a new patch set (#29) to the change originally created by Marvin Drees. ( https://review.coreboot.org/c/coreboot/+/48648?usp=email )
The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins)
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
[WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards
Currently WIP: H110T Next: Q170T (Same issues currently)
Working: - Booting into SeaBIOS - Booting into TianoCore - UART (uses 12V RS232 levels!) - HDMI and DP in Tianocore via libgfxinit - TPM 2.0 - NVMe M.2
Not working: - Booting Linux, resets at DMAR - Video in Linux - USB (Needs devicetree entries)
Untested: - Ethernet (Needs working OS) - LVDS (No hardware to test) - Sound (Needs working OS) - M.2 E key slot (Needs working OS) - SATA (Needs working OS) - S3 sleep (Needs working OS)
TODO: - Fill devicetree more (Most notably USB OC pins) - Fix bootloop - Booting Memtest86 as the primary payload reveals that CPU0 is receiving an unexpected interrupt, causing it to reset.
Notes: - EM100 usage flakey (does quad IO even though IFD is modified not to) - Stripping ME causes the board to not boot at all. The same behaviour occurs with me_cleaned vendor firmware. But setting the HAP bit works and disables the ME.
Change-Id: Iab30596f2a12931679687c9f56427712b65f9363 Signed-off-by: Marvin Drees marvin@ceres-sys.de --- A src/mainboard/asus/sklkbl_h/Kconfig A src/mainboard/asus/sklkbl_h/Kconfig.name A src/mainboard/asus/sklkbl_h/Makefile.inc A src/mainboard/asus/sklkbl_h/acpi/ec.asl A src/mainboard/asus/sklkbl_h/acpi/superio.asl A src/mainboard/asus/sklkbl_h/board_info.txt A src/mainboard/asus/sklkbl_h/bootblock.c A src/mainboard/asus/sklkbl_h/cmos.default A src/mainboard/asus/sklkbl_h/cmos.layout A src/mainboard/asus/sklkbl_h/dsdt.asl A src/mainboard/asus/sklkbl_h/include/variant/gpio.h A src/mainboard/asus/sklkbl_h/include/variant/superio.h A src/mainboard/asus/sklkbl_h/ramstage.c A src/mainboard/asus/sklkbl_h/romstage.c A src/mainboard/asus/sklkbl_h/variants/h110t/board_info.txt A src/mainboard/asus/sklkbl_h/variants/h110t/data.vbt A src/mainboard/asus/sklkbl_h/variants/h110t/devicetree.cb A src/mainboard/asus/sklkbl_h/variants/h110t/gma-mainboard.ads A src/mainboard/asus/sklkbl_h/variants/h110t/gpio.c A src/mainboard/asus/sklkbl_h/variants/h110t/gpio_early.c A src/mainboard/asus/sklkbl_h/variants/h110t/hda_verb.c A src/mainboard/asus/sklkbl_h/variants/h110t/superio.c 22 files changed, 1,766 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/48648/29
Attention is currently required from: Angel Pons, Felix Singer, Marvin Drees, Paul Menzel.
Felix Singer has uploaded a new patch set (#30) to the change originally created by Marvin Drees. ( https://review.coreboot.org/c/coreboot/+/48648?usp=email )
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
[WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards
Currently WIP: H110T Next: Q170T (Same issues currently)
Working: - Booting into SeaBIOS - Booting into TianoCore - UART (uses 12V RS232 levels!) - HDMI and DP in Tianocore via libgfxinit - TPM 2.0 - NVMe M.2
Not working: - Booting Linux, resets at DMAR - Video in Linux - USB (Needs devicetree entries)
Untested: - Ethernet (Needs working OS) - LVDS (No hardware to test) - Sound (Needs working OS) - M.2 E key slot (Needs working OS) - SATA (Needs working OS) - S3 sleep (Needs working OS)
TODO: - Fill devicetree more (Most notably USB OC pins) - Fix bootloop - Booting Memtest86 as the primary payload reveals that CPU0 is receiving an unexpected interrupt, causing it to reset.
Notes: - EM100 usage flakey (does quad IO even though IFD is modified not to) - Stripping ME causes the board to not boot at all. The same behaviour occurs with me_cleaned vendor firmware. But setting the HAP bit works and disables the ME.
Change-Id: Iab30596f2a12931679687c9f56427712b65f9363 Signed-off-by: Marvin Drees marvin@ceres-sys.de --- A src/mainboard/asus/sklkbl_h/Kconfig A src/mainboard/asus/sklkbl_h/Kconfig.name A src/mainboard/asus/sklkbl_h/Makefile.inc A src/mainboard/asus/sklkbl_h/acpi/ec.asl A src/mainboard/asus/sklkbl_h/acpi/superio.asl A src/mainboard/asus/sklkbl_h/board_info.txt A src/mainboard/asus/sklkbl_h/bootblock.c A src/mainboard/asus/sklkbl_h/cmos.default A src/mainboard/asus/sklkbl_h/cmos.layout A src/mainboard/asus/sklkbl_h/dsdt.asl A src/mainboard/asus/sklkbl_h/include/variant/gpio.h A src/mainboard/asus/sklkbl_h/include/variant/superio.h A src/mainboard/asus/sklkbl_h/ramstage.c A src/mainboard/asus/sklkbl_h/romstage.c A src/mainboard/asus/sklkbl_h/variants/h110t/board_info.txt A src/mainboard/asus/sklkbl_h/variants/h110t/data.vbt A src/mainboard/asus/sklkbl_h/variants/h110t/devicetree.cb A src/mainboard/asus/sklkbl_h/variants/h110t/gma-mainboard.ads A src/mainboard/asus/sklkbl_h/variants/h110t/gpio.c A src/mainboard/asus/sklkbl_h/variants/h110t/gpio_early.c A src/mainboard/asus/sklkbl_h/variants/h110t/hda_verb.c A src/mainboard/asus/sklkbl_h/variants/h110t/superio.c 22 files changed, 1,762 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/48648/30
Attention is currently required from: Angel Pons, Felix Singer, Marvin Drees, Paul Menzel.
Felix Singer has uploaded a new patch set (#31) to the change originally created by Marvin Drees. ( https://review.coreboot.org/c/coreboot/+/48648?usp=email )
Change subject: [WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards ......................................................................
[WIP] mb/asus/sklkbl_h: Add base for Asus Skylake Boards
Currently WIP: H110T Next: Q170T (Same issues currently)
Working: - Booting into SeaBIOS - Booting into TianoCore - UART (uses 12V RS232 levels!) - HDMI and DP in Tianocore via libgfxinit - TPM 2.0 - NVMe M.2
Not working: - Booting Linux, resets at DMAR - Video in Linux - USB (Needs devicetree entries)
Untested: - Ethernet (Needs working OS) - LVDS (No hardware to test) - Sound (Needs working OS) - M.2 E key slot (Needs working OS) - SATA (Needs working OS) - S3 sleep (Needs working OS)
TODO: - Fill devicetree more (Most notably USB OC pins) - Fix bootloop - Booting Memtest86 as the primary payload reveals that CPU0 is receiving an unexpected interrupt, causing it to reset.
Notes: - EM100 usage flakey (does quad IO even though IFD is modified not to) - Stripping ME causes the board to not boot at all. The same behaviour occurs with me_cleaned vendor firmware. But setting the HAP bit works and disables the ME.
Change-Id: Iab30596f2a12931679687c9f56427712b65f9363 Signed-off-by: Marvin Drees marvin@ceres-sys.de --- A src/mainboard/asus/sklkbl_h/Kconfig A src/mainboard/asus/sklkbl_h/Kconfig.name A src/mainboard/asus/sklkbl_h/Makefile.inc A src/mainboard/asus/sklkbl_h/acpi/ec.asl A src/mainboard/asus/sklkbl_h/acpi/superio.asl A src/mainboard/asus/sklkbl_h/board_info.txt A src/mainboard/asus/sklkbl_h/bootblock.c A src/mainboard/asus/sklkbl_h/cmos.default A src/mainboard/asus/sklkbl_h/cmos.layout A src/mainboard/asus/sklkbl_h/dsdt.asl A src/mainboard/asus/sklkbl_h/include/variant/gpio.h A src/mainboard/asus/sklkbl_h/include/variant/superio.h A src/mainboard/asus/sklkbl_h/ramstage.c A src/mainboard/asus/sklkbl_h/romstage.c A src/mainboard/asus/sklkbl_h/variants/h110t/board_info.txt A src/mainboard/asus/sklkbl_h/variants/h110t/data.vbt A src/mainboard/asus/sklkbl_h/variants/h110t/devicetree.cb A src/mainboard/asus/sklkbl_h/variants/h110t/gma-mainboard.ads A src/mainboard/asus/sklkbl_h/variants/h110t/gpio.c A src/mainboard/asus/sklkbl_h/variants/h110t/gpio_early.c A src/mainboard/asus/sklkbl_h/variants/h110t/hda_verb.c A src/mainboard/asus/sklkbl_h/variants/h110t/superio.c 22 files changed, 1,764 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/48648/31
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Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
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Felix Singer (Code Review)
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Marvin D (Code Review)
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Marvin Drees (Code Review)
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Paul Menzel (Code Review)