Marvin Drees has uploaded this change for review.
mb/asus: Add ASUS H110T mainboard
This initial commit isn't yet fully working but in order to get
it sorted it is pushed already.
As the IGD and serial line aren't fully working yet, it is hard to
tell what parts of the hardware already work and which don't.
Tested payloads so far: coreinfo and tianocore.
Signed-off-by: Marvin Drees <marvin@ceres-sys.de>
Change-Id: Iab30596f2a12931679687c9f56427712b65f9363
---
A src/mainboard/asus/h110t/Kconfig
A src/mainboard/asus/h110t/Kconfig.name
A src/mainboard/asus/h110t/Makefile.inc
A src/mainboard/asus/h110t/acpi/dptf.asl
A src/mainboard/asus/h110t/acpi/ec.asl
A src/mainboard/asus/h110t/acpi/mainboard.asl
A src/mainboard/asus/h110t/acpi/superio.asl
A src/mainboard/asus/h110t/board_info.txt
A src/mainboard/asus/h110t/bootblock.c
A src/mainboard/asus/h110t/cmos.default
A src/mainboard/asus/h110t/cmos.layout
A src/mainboard/asus/h110t/data.vbt
A src/mainboard/asus/h110t/devicetree.cb
A src/mainboard/asus/h110t/dsdt.asl
A src/mainboard/asus/h110t/gma-mainboard.ads
A src/mainboard/asus/h110t/hda_verb.c
A src/mainboard/asus/h110t/include/gpio.h
A src/mainboard/asus/h110t/mainboard.c
A src/mainboard/asus/h110t/ramstage.c
A src/mainboard/asus/h110t/romstage.c
20 files changed, 1,218 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/48648/1
diff --git a/src/mainboard/asus/h110t/Kconfig b/src/mainboard/asus/h110t/Kconfig
new file mode 100644
index 0000000..676ecad
--- /dev/null
+++ b/src/mainboard/asus/h110t/Kconfig
@@ -0,0 +1,51 @@
+if BOARD_ASUS_H110T
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_16384
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select SOC_INTEL_KABYLAKE
+ select SKYLAKE_SOC_PCH_H
+ select SUPERIO_NUVOTON_COMMON_COM_A
+ select SUPERIO_NUVOTON_NCT5539D
+ select REALTEK_8168_RESET
+ select RT8168_SET_LED_MODE
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select DRIVER_INTEL_I210
+ select MAINBOARD_HAS_LPC_TPM
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAINBOARD_DIR
+ string
+ default "asus/h110t"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "H110T"
+
+config MAX_CPUS
+ int
+ default 8
+
+config DEVICETREE
+ string
+ default "devicetree.cb"
+
+config DIMM_SPD_SIZE
+ int
+ default 512 # DDR4
+
+# This is overridden if CMOS is used for configuration values.
+config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+ bool
+ default n
+
+endif
diff --git a/src/mainboard/asus/h110t/Kconfig.name b/src/mainboard/asus/h110t/Kconfig.name
new file mode 100644
index 0000000..f9d5c9c
--- /dev/null
+++ b/src/mainboard/asus/h110t/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASUS_H110T
+ bool "H110T"
diff --git a/src/mainboard/asus/h110t/Makefile.inc b/src/mainboard/asus/h110t/Makefile.inc
new file mode 100644
index 0000000..ef44a4c
--- /dev/null
+++ b/src/mainboard/asus/h110t/Makefile.inc
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+
+ramstage-y += ramstage.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/asus/h110t/acpi/dptf.asl b/src/mainboard/asus/h110t/acpi/dptf.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/h110t/acpi/dptf.asl
diff --git a/src/mainboard/asus/h110t/acpi/ec.asl b/src/mainboard/asus/h110t/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/h110t/acpi/ec.asl
diff --git a/src/mainboard/asus/h110t/acpi/mainboard.asl b/src/mainboard/asus/h110t/acpi/mainboard.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/h110t/acpi/mainboard.asl
diff --git a/src/mainboard/asus/h110t/acpi/superio.asl b/src/mainboard/asus/h110t/acpi/superio.asl
new file mode 100644
index 0000000..800e80a
--- /dev/null
+++ b/src/mainboard/asus/h110t/acpi/superio.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define SUPERIO_DEV SIO0
+#define SUPERIO_PNP_BASE 0x2e
+#define NCT5539D_SHOW_SP1
+#define NCT5539D_SHOW_KBC
+#define NCT5539D_SHOW_HWM
+
+#undef NCT5539D_SHOW_GPIO
diff --git a/src/mainboard/asus/h110t/board_info.txt b/src/mainboard/asus/h110t/board_info.txt
new file mode 100644
index 0000000..37aa41c
--- /dev/null
+++ b/src/mainboard/asus/h110t/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asus.com/Motherboards/H110T/
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
+Release year: 2016
diff --git a/src/mainboard/asus/h110t/bootblock.c b/src/mainboard/asus/h110t/bootblock.c
new file mode 100644
index 0000000..d3f9ef3
--- /dev/null
+++ b/src/mainboard/asus/h110t/bootblock.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <soc/gpio.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct5539d/nct5539d.h>
+#include "include/gpio.h"
+
+static void early_config_superio(void)
+{
+ const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT5539D_SP1);
+ nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
+}
+
+static void early_config_gpio(void)
+{
+ /* This is a hack for FSP because it does things in MemoryInit()
+ * which it shouldn't do. We have to prepare certain gpios here
+ * because of the brokenness in FSP. */
+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
+
+void bootblock_mainboard_init(void)
+{
+ early_config_gpio();
+}
+
+void bootblock_mainboard_early_init(void)
+{
+ early_config_superio();
+}
diff --git a/src/mainboard/asus/h110t/cmos.default b/src/mainboard/asus/h110t/cmos.default
new file mode 100644
index 0000000..f4dbc7e
--- /dev/null
+++ b/src/mainboard/asus/h110t/cmos.default
@@ -0,0 +1,5 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+hyper_threading=Enable
diff --git a/src/mainboard/asus/h110t/cmos.layout b/src/mainboard/asus/h110t/cmos.layout
new file mode 100644
index 0000000..81dd48b
--- /dev/null
+++ b/src/mainboard/asus/h110t/cmos.layout
@@ -0,0 +1,111 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392 3 r 0 unused
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+#416 128 r 0 vbnv
+#544 440 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+#896 32 r 0 mrc_scrambler_seed
+#928 32 r 0 mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/asus/h110t/data.vbt b/src/mainboard/asus/h110t/data.vbt
new file mode 100644
index 0000000..0061c69
--- /dev/null
+++ b/src/mainboard/asus/h110t/data.vbt
Binary files differ
diff --git a/src/mainboard/asus/h110t/devicetree.cb b/src/mainboard/asus/h110t/devicetree.cb
new file mode 100644
index 0000000..82f8968
--- /dev/null
+++ b/src/mainboard/asus/h110t/devicetree.cb
@@ -0,0 +1,196 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "0"
+ register "deep_s5_enable_ac" = "0"
+ register "deep_s5_enable_dc" = "0"
+ register "deep_sx_config" = "DSX_EN_WAKE_PIN"
+
+ register "eist_enable" = "1"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_B"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ # FSP Configuration
+ register "PrimaryDisplay" = "Display_iGFX"
+ register "SaGv" = "SaGv_Enabled"
+
+ # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
+ # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
+ register "PmConfigSlpS3MinAssert" = "0x02"
+
+ # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
+ register "PmConfigSlpS4MinAssert" = "0x04"
+
+ # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
+ register "PmConfigSlpSusMinAssert" = "0x03"
+
+ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
+ register "PmConfigSlpAMinAssert" = "0x03"
+
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ device domain 0 on
+ subsystemid 0x1043 0x8694 inherit # Asus specific
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 14.0 on # USB xHCI
+ # TODO get these values right
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC4)"
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC4)"
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[10]" = "USB2_PORT_MID(OC1)"
+ register "usb2_ports[11]" = "USB2_PORT_MID(OC1)"
+ register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)"
+ register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)"
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)"
+ register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+ register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+ register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+ register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+ end
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 off end # Thermal Subsystem
+ device pci 15.0 off end # I2C #0
+ device pci 15.1 off end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 on # SATA
+ register "SataSalpSupport" = "1"
+ register "SataPortsEnable" = "{
+ [0] = 1,
+ [1] = 1,
+ }"
+ end
+ device pci 19.0 off end # UART #2
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 off end # I2C #4
+ device pci 1c.0 on # PCI Express Port 5
+ register "PcieRpEnable[0]" = "1"
+ register "PcieRpClkReqSupport[0]" = "1"
+ end
+ device pci 1d.0 on # PCI Express Port 9
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpAdvancedErrorReporting[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ end
+ device pci 1d.1 on # PCI Express Port 10 - Realtek onboard LAN
+ register "PcieRpEnable[9]" = "1"
+ register "PcieRpAdvancedErrorReporting[9]" = "1"
+ register "PcieRpLtrEnable[9]" = "1"
+ # Disable CLKREQ#, since onboard LAN is always present
+ register "PcieRpClkReqSupport[9]" = "0"
+ end
+ device pci 1e.0 off end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1e.4 off end # eMMC
+ device pci 1e.5 off end # SDIO
+ device pci 1e.6 off end # SDCard
+ device pci 1f.0 on # LPC bridge # TODO the superio config probably needs improvement
+
+ # Set LPC Serial IRQ mode
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+ chip superio/common
+ device pnp 2e.ff on # passes SIO base addr to SSDT gen
+ chip superio/nuvoton/nct5539d
+ device pnp 2e.1 on
+ irq 0x13 = 0xff
+ irq 0x14 = 0xff
+ irq 0x1a = 0x00
+ irq 0x24 = 0x00
+ irq 0x26 = 0x00
+ irq 0x27 = 0x01
+ irq 0x28 = 0x10
+ irq 0x2a = 0x00
+ irq 0x2c = 0x00
+ irq 0x2d = 0x02
+ irq 0x2f = 0x00
+ end
+ device pnp 2e.2 on # UART A
+ io 0x60 = 0x03f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.5 on # PS/2 KBC
+ io 0x60 = 0x0060
+ io 0x62 = 0x0064
+ irq 0x70 = 1 # Keyboard
+ irq 0x72 = 12 # Mouse
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GPIO7
+ device pnp 2e.107 off end # GPIO8
+ device pnp 2e.8 off end # WDT
+ device pnp 2e.108 off end # GPIO0
+ device pnp 2e.308 off end # GPIO BASE
+ device pnp 2e.408 off end # WDTMEM
+ device pnp 2e.9 off end # GPIO2
+ device pnp 2e.109 off end # GPIO3
+ device pnp 2e.209 off end # GPIO4
+ device pnp 2e.309 off end # GPIO5
+ device pnp 2e.a on # ACPI
+ irq 0xe6 = 0x0a
+ irq 0xe7 = 0x11
+ irq 0xec = 0x80
+ irq 0xf2 = 0x5d
+ end
+ device pnp 2e.b on # HWM, LED
+ io 0x60 = 0x0290
+ irq 0xf0 = 0x7e
+ end
+ device pnp 2e.d off end # BCLK/WDT2/WDT_MEM
+ device pnp 2e.e off end # CIR WAKE-UP
+ device pnp 2e.f off end # GPIO PP/OD
+ device pnp 2e.14 off end # SVID/PORT 80
+ device pnp 2e.16 off end # DS5
+ device pnp 2e.116 off end # DS3
+ device pnp 2e.316 off end # PCHDSW
+ device pnp 2e.416 off end # DSWWOPT
+ device pnp 2e.516 off end # DS3OPT
+ device pnp 2e.616 off end # DSDSS
+ device pnp 2e.716 off end # DSPU
+ end # superio/nuvoton/nct5539d
+ end # SSDT gen
+ end # superio/common
+ end # LPC Interface
+ device pci 1f.1 off end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on # Intel HDA
+ register "PchHdaVcType" = "Vc1"
+ end
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 off end # PCH SPI
+ device pci 1f.6 on end # GbE
+ end
+end
diff --git a/src/mainboard/asus/h110t/dsdt.asl b/src/mainboard/asus/h110t/dsdt.asl
new file mode 100644
index 0000000..32e22b3
--- /dev/null
+++ b/src/mainboard/asus/h110t/dsdt.asl
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ #include <soc/intel/common/acpi/platform.asl>
+ #include <soc/intel/skylake/acpi/globalnvs.asl>
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ /* Image processing unit */
+ #include <soc/intel/skylake/acpi/ipu.asl>
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ }
+
+ // Dynamic Platform Thermal Framework
+ #include "acpi/dptf.asl"
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ // Mainboard specific
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/asus/h110t/gma-mainboard.ads b/src/mainboard/asus/h110t/gma-mainboard.ads
new file mode 100644
index 0000000..7bf6d97
--- /dev/null
+++ b/src/mainboard/asus/h110t/gma-mainboard.ads
@@ -0,0 +1,17 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (HDMI1,
+ DP1,
+ LVDS,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asus/h110t/hda_verb.c b/src/mainboard/asus/h110t/hda_verb.c
new file mode 100644
index 0000000..136c60a
--- /dev/null
+++ b/src/mainboard/asus/h110t/hda_verb.c
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0887, /* Codec Vendor / Device ID: Realtek ALC887 */
+ 0x10438445, /* Subsystem ID */
+ 15, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x10438445),
+ AZALIA_PIN_CFG(0, 0x11, 0x40000000),
+ AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x14, 0x01014020),
+ AZALIA_PIN_CFG(0, 0x15, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19040),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a19050),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02214030),
+ AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4026c629),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+ 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(2, 0x80860101),
+ AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(2, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[] = {};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/h110t/include/gpio.h b/src/mainboard/asus/h110t/include/gpio.h
new file mode 100644
index 0000000..ee33999
--- /dev/null
+++ b/src/mainboard/asus/h110t/include/gpio.h
@@ -0,0 +1,637 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef CFG_GPIO_H
+#define CFG_GPIO_H
+
+#include <gpio.h>
+
+static const struct pad_config gpio_table[] = {
+
+ /* ------- GPIO Community 0 ------- */
+
+ /* ------- GPIO Group GPP_A ------- */
+ _PAD_CFG_STRUCT(GPP_A0,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* RCIN# */
+ _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1),
+ PAD_PULL(UP_20K)), /* LAD0 */
+ _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1),
+ PAD_PULL(UP_20K)), /* LAD1 */
+ _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1),
+ PAD_PULL(UP_20K)), /* LAD2 */
+ _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1),
+ PAD_PULL(UP_20K)), /* LAD3 */
+ _PAD_CFG_STRUCT(GPP_A5,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ 0), /* LFRAME# */
+ _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF),
+ 0), /* SERIRQ */
+ _PAD_CFG_STRUCT(GPP_A7,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_A8,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ 0), /* CLKRUN# */
+ _PAD_CFG_STRUCT(GPP_A9,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ PAD_PULL(DN_20K)), /* CLKOUT_LPC0 */
+ _PAD_CFG_STRUCT(GPP_A10,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ PAD_PULL(DN_20K)), /* CLKOUT_LPC1 */
+ _PAD_CFG_STRUCT(GPP_A11,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ PAD_PULL(UP_20K)), /* PME# */
+ _PAD_CFG_STRUCT(GPP_A12,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_A13,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ 0), /* SUSWARN#/SUSPWRDNACK */
+ _PAD_CFG_STRUCT(GPP_A14,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_A15,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ PAD_PULL(UP_20K)), /* SUS_ACK# */
+ _PAD_CFG_STRUCT(GPP_A16,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_A17,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_A18,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_A19,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPO(GPP_A20, 0, PLTRST), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_A21,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_A22,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, PLTRST, OFF, ACPI), /* GPIO */
+
+ /* ------- GPIO Group GPP_B ------- */
+ _PAD_CFG_STRUCT(GPP_B0,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B2,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B3,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B4,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B8,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B9,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B10,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B11,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B12,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B13,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ 0), /* PLTRST# */
+ _PAD_CFG_STRUCT(GPP_B14,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ PAD_PULL(DN_20K)), /* SPKR */
+ _PAD_CFG_STRUCT(GPP_B15,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPO(GPP_B16, 0, PLTRST), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B17,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B18,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B19,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B20,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B21,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B22,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B23,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+
+ /* ------- GPIO Community 1 ------- */
+
+ /* ------- GPIO Group GPP_C ------- */
+ _PAD_CFG_STRUCT(GPP_C0,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE)
+ | (1 << 1),
+ 0), /* SMBCLK */
+ _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1),
+ 0), /* SMBDATA */
+ _PAD_CFG_STRUCT(GPP_C2,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C3,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE)
+ | (1 << 1),
+ 0), /* SML0CLK */
+ _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1),
+ 0), /* SML0DATA */
+ _PAD_CFG_STRUCT(GPP_C5,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C6,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C7,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C9,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C10,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C11,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C13,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C14,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C15,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C16,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_C17, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C20,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_C21, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C22,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI)
+ | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C23,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI)
+ | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1),
+ 0), /* GPIO */
+
+ /* ------- GPIO Group GPP_D ------- */
+ _PAD_CFG_STRUCT(GPP_D0,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D2,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D3,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D4,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI)
+ | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_D9, DN_20K, RSMRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_D10, DN_20K, RSMRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_D11, DN_20K, RSMRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D12,
+ PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ PAD_PULL(DN_20K)), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D14,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_D15, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_D16, DN_20K, RSMRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D18,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_D19,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, PLTRST, OFF, ACPI), /* GPIO */
+
+ /* ------- GPIO Group GPP_E ------- */
+ PAD_CFG_GPI_TRIG_OWN(GPP_E0, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, DEEP, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_E8,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ 0), /* SATA_LED# */
+ _PAD_CFG_STRUCT(GPP_E9,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* USB_OC0# */
+ _PAD_CFG_STRUCT(GPP_E10,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* USB_OC1# */
+ _PAD_CFG_STRUCT(GPP_E11,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* USB_OC2# */
+ _PAD_CFG_STRUCT(GPP_E12,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* USB_OC3# */
+
+ /* ------- GPIO Group GPP_F ------- */
+ _PAD_CFG_STRUCT(GPP_F0,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ PAD_PULL(UP_20K)), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F2,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ PAD_PULL(UP_20K)), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F5,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F6, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F7, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F9,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F14,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F15,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* USB_OC4# */
+ _PAD_CFG_STRUCT(GPP_F16,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F17,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F18,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F19,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ 0), /* eDP_VDDEN */
+ _PAD_CFG_STRUCT(GPP_F20,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ 0), /* eDP_BKLTEN */
+ _PAD_CFG_STRUCT(GPP_F21,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ 0), /* eDP_BKLTCTL */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F22, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_F23,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+
+ /* ------- GPIO Group GPP_G ------- */
+ _PAD_CFG_STRUCT(GPP_G0,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_G2, DN_20K, RSMRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_G3, DN_20K, RSMRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_G4, DN_20K, RSMRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G5,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G7,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_G9, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G10,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G15,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_G17, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_G18, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_G19, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_G20, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G22,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_G23,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+
+ /* ------- GPIO Group GPP_H ------- */
+ PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H1,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE)
+ | (1 << 1),
+ 0), /* SRCCLKREQ7# */
+ PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H3,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H4,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H5,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H6,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_H7, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_H8, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_H9, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H10,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_H11, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H12,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H13,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H14,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_H16, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_H17, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H20,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H21,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, PLTRST, OFF, ACPI), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H23,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+
+ /* ------- GPIO Community 2 ------- */
+
+ /* -------- GPIO Group GPD -------- */
+ _PAD_CFG_STRUCT(GPD0,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPD1,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1),
+ 0), /* LAN_WAKE# */
+ _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1),
+ PAD_PULL(UP_20K)), /* PWRBTN# */
+ _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ 0), /* SLP_S3# */
+ _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ 0), /* SLP_S4# */
+ _PAD_CFG_STRUCT(GPD6, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPD7,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1) | 1,
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPD8,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPD9,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPD10, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPD11, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ 0), /* LANPHYPC */
+
+ /* ------- GPIO Community 3 ------- */
+
+ /* ------- GPIO Group GPP_I ------- */
+ _PAD_CFG_STRUCT(GPP_I0,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ 0), /* DDPB_HPD0 */
+ _PAD_CFG_STRUCT(GPP_I1,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* DDPC_HPD1 */
+ _PAD_CFG_STRUCT(GPP_I2,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ 0), /* DDPD_HPD2 */
+ _PAD_CFG_STRUCT(GPP_I3,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* DDPE_HPD3 */
+ _PAD_CFG_STRUCT(GPP_I4,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* EDP_HPD */
+ _PAD_CFG_STRUCT(GPP_I5,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ 0), /* DDPB_CTRLCLK */
+ _PAD_CFG_STRUCT(GPP_I6,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ PAD_PULL(DN_20K)), /* DDPB_CTRLDATA */
+ _PAD_CFG_STRUCT(GPP_I7,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ 0), /* DDPC_CTRLCLK */
+ _PAD_CFG_STRUCT(GPP_I8,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ PAD_PULL(DN_20K)), /* DDPC_CTRLDATA */
+ _PAD_CFG_STRUCT(GPP_I9,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* DDPD_CTRLCLK */
+ _PAD_CFG_STRUCT(GPP_I10,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ PAD_PULL(DN_20K)), /* DDPD_CTRLDATA */
+};
+
+static const struct pad_config early_gpio_table[] = {
+
+ /* ------- GPIO Group GPP_A ------- */
+ _PAD_CFG_STRUCT(GPP_A0,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* RCIN# */
+ _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1),
+ PAD_PULL(UP_20K)), /* LAD0 */
+ _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1),
+ PAD_PULL(UP_20K)), /* LAD1 */
+ _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1),
+ PAD_PULL(UP_20K)), /* LAD2 */
+ _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1),
+ PAD_PULL(UP_20K)), /* LAD3 */
+ _PAD_CFG_STRUCT(GPP_A5,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ 0), /* LFRAME# */
+ _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF),
+ 0), /* SERIRQ */
+ _PAD_CFG_STRUCT(GPP_A7,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_A8,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ 0), /* CLKRUN# */
+ _PAD_CFG_STRUCT(GPP_A9,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ PAD_PULL(DN_20K)), /* CLKOUT_LPC0 */
+ _PAD_CFG_STRUCT(GPP_A10,
+ PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ PAD_PULL(DN_20K)), /* CLKOUT_LPC1 */
+ _PAD_CFG_STRUCT(GPP_A11,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ PAD_PULL(UP_20K)), /* PME# */
+ _PAD_CFG_STRUCT(GPP_A12,
+ PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_A13,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE),
+ 0), /* SUSWARN#/SUSPWRDNACK */
+ _PAD_CFG_STRUCT(GPP_A14,
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE)
+ | (1 << 1),
+ 0), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_A15,
+ PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE),
+ PAD_PULL(UP_20K)), /* SUS_ACK# */
+};
+
+#endif /* CFG_GPIO_H */
diff --git a/src/mainboard/asus/h110t/mainboard.c b/src/mainboard/asus/h110t/mainboard.c
new file mode 100644
index 0000000..203c5e3
--- /dev/null
+++ b/src/mainboard/asus/h110t/mainboard.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <drivers/intel/i210/i210.h>
+
+static void mainboard_enable(struct device *dev)
+{
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
+
+enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6])
+{
+ /* TODO */
+ mac[0] = 0xFF;
+ mac[1] = 0xFF;
+ mac[2] = 0xFF;
+ mac[3] = 0xFF;
+ mac[4] = 0xFF;
+ mac[5] = 0xFF;
+ return CB_SUCCESS;
+}
diff --git a/src/mainboard/asus/h110t/ramstage.c b/src/mainboard/asus/h110t/ramstage.c
new file mode 100644
index 0000000..9d3933c
--- /dev/null
+++ b/src/mainboard/asus/h110t/ramstage.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+#include "include/gpio.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+ /* Configure pads prior to SiliconInit() in case there's any
+ * dependencies during hardware initialization. */
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/asus/h110t/romstage.c b/src/mainboard/asus/h110t/romstage.c
new file mode 100644
index 0000000..7c532e4
--- /dev/null
+++ b/src/mainboard/asus/h110t/romstage.c
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <soc/romstage.h>
+#include <stdint.h>
+#include <string.h>
+#include <spd_bin.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ const u16 rcomp_resistors[3] = {121, 75, 100};
+
+ const u16 rcomp_targets[5] = {50, 26, 20, 20, 26};
+
+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+
+ struct spd_block blk = {
+ .addr_map = {0x50, 0x52},
+ };
+
+ assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors));
+ assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets));
+
+ mem_cfg->DqPinsInterleaved = 1;
+ get_spd_smbus(&blk);
+ mem_cfg->MemorySpdDataLen = blk.len;
+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
+ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
+ dump_spd_info(&blk);
+
+ memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor));
+ memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget));
+
+ /* use virtual channel 1 for the dmi interface of the PCH */
+ mupd->FspmTestConfig.DmiVc1 = 1;
+
+ /* desktop type */
+ mem_cfg->UserBd = BOARD_TYPE_DESKTOP;
+}
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