Change in coreboot[master]: mb/google/zork: de-assert eMMC RST for Morphius

[Kevin Chiu (Code Review)]

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: de-assert eMMC RST for Morphius
......................................................................

mb/google/zork: de-assert eMMC RST for Morphius

de-assert eMMC RST (GPIO68) to prevent eMMC abnormal.

BUG=b:169211959
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. check GPIO86 state is PU

Change-Id: I9feb826eec8a8cdad5e2bd7efcbb1dcf96185dfd
Signed-off-by: Kevin Chiu 
---
M src/mainboard/google/zork/variants/morphius/gpio.c
1 file changed, 9 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/45756/1

diff --git a/src/mainboard/google/zork/variants/morphius/gpio.c b/src/mainboard/google/zork/variants/morphius/gpio.c
index 8da0de4..c1655fa 100644
--- a/src/mainboard/google/zork/variants/morphius/gpio.c
+++ b/src/mainboard/google/zork/variants/morphius/gpio.c
@@ -52,6 +52,8 @@
 };

static const struct soc_amd_gpio morphius_bid3_gpio_set_stage_ram[] = {
+	/* EMMC_RESET */
+	PAD_GPO(GPIO_68, HIGH),
    /* EN_DEV_BEEP_L */
    PAD_GPO(GPIO_89, HIGH),
    /* TP */
@@ -60,6 +62,11 @@
    PAD_GPO(GPIO_140, HIGH),
 };

+static const struct soc_amd_gpio morphius_gpio_set_stage_ram[] = {
+	/* EMMC_RESET */
+	PAD_GPO(GPIO_68, HIGH),
+};
+
 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
 {
    uint32_t board_version;
@@ -83,6 +90,6 @@
    	return morphius_bid3_gpio_set_stage_ram;
    }

-	*size = 0;
-	return NULL;
+	*size = ARRAY_SIZE(morphius_gpio_set_stage_ram);
+	return morphius_gpio_set_stage_ram;
 }

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: de-assert eMMC RST for Morphius
......................................................................

Patch Set 1:

(3 comments)

https://review.coreboot.org/c/coreboot/+/45756/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/45756/1//COMMIT_MSG@9 
PS1, Line 9: de-assert eMMC RST (GPIO68) to prevent eMMC abnormal.
We don't really use this signal. Probably configure it as PAD_NC in baseboard/gpio_baseboard_trembyle.c?

https://review.coreboot.org/c/coreboot/+/45756/1//COMMIT_MSG@11 
PS1, Line 11: 169211959
Did you mean: 169222156?

https://review.coreboot.org/c/coreboot/+/45756/1//COMMIT_MSG@14 
PS1, Line 14: check GPIO86 state is PU
What is the difference from a functional standpoint? Are you seeing some error go away because of this change?

[Keith Tzeng (Code Review)]

Keith Tzeng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: de-assert eMMC RST for Morphius
......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/c/coreboot/+/45756/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/45756/1//COMMIT_MSG@11 
PS1, Line 11: 169211959
> Did you mean: 169222156?

Should be b:169222156

https://review.coreboot.org/c/coreboot/+/45756/1//COMMIT_MSG@14 
PS1, Line 14: check GPIO86 state is PU
> What is the difference from a functional standpoint? Are you seeing some error go away because of th […]

as on tracker: https://partnerissuetracker.corp.google.com/issues/169222156#comment7
the reset pin keep low on your measurement, eMMC vendor feedback that it need to be high.

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: de-assert eMMC RST for Morphius
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45756/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/45756/1//COMMIT_MSG@14 
PS1, Line 14: check GPIO86 state is PU
> as on tracker: https://partnerissuetracker.corp.google.com/issues/169222156#comment7 […]

Understood. I was just curious if configuring the pad to drive high helps fix any observed issue.

Change in coreboot[master]: mb/google/zork: config eMMC RST GPIO to NC

[Kevin Chiu (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Martin Roth, Bhanu Prakash Maiya, Keith Tzeng, Aaron Durbin,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45756

to look at the new patch set (#2).

Change subject: mb/google/zork: config eMMC RST GPIO to NC
......................................................................

mb/google/zork: config eMMC RST GPIO to NC

Config eMMC RST (GPIO68) to NC to prevent eMMC abnormal.

BUG=b:169222156
BRANCH=zork
TEST=emerge-zork coreboot

Change-Id: I9feb826eec8a8cdad5e2bd7efcbb1dcf96185dfd
Signed-off-by: Kevin Chiu 
---
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/45756/2

Change in coreboot[master]: mb/google/zork: config eMMC RST GPIO to NC

[Kevin Chiu (Code Review)]

Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: config eMMC RST GPIO to NC
......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/45756/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/45756/1//COMMIT_MSG@9 
PS1, Line 9: de-assert eMMC RST (GPIO68) to prevent eMMC abnormal.
> We don't really use this signal. […]

Done

https://review.coreboot.org/c/coreboot/+/45756/1//COMMIT_MSG@11 
PS1, Line 11: 169211959
> Should be b:169222156

Done

Change in coreboot[master]: mb/google/zork: config eMMC RST GPIO to NC

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: config eMMC RST GPIO to NC
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45756/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/45756/2//COMMIT_MSG@13 
PS2, Line 13: TEST
Did you run reboot and suspend stress tests with this?

Change in coreboot[master]: mb/google/zork: config eMMC RST GPIO to NC

[Kevin Chiu (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Martin Roth, Bhanu Prakash Maiya, Keith Tzeng, Aaron Durbin,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45756

to look at the new patch set (#3).

Change subject: mb/google/zork: config eMMC RST GPIO to NC
......................................................................

mb/google/zork: config eMMC RST GPIO to NC

Config eMMC RST (GPIO68) to NC to prevent eMMC abnormal.

BUG=b:169222156
BRANCH=zork
TEST=emerge-zork coreboot
     eMMC DUT reboot/suspend x100 iterations pass

Change-Id: I9feb826eec8a8cdad5e2bd7efcbb1dcf96185dfd
Signed-off-by: Kevin Chiu 
---
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/45756/3

Change in coreboot[master]: mb/google/zork: config eMMC RST GPIO to NC

[Kevin Chiu (Code Review)]

Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: config eMMC RST GPIO to NC
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45756/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/45756/2//COMMIT_MSG@13 
PS2, Line 13: TEST
> Did you run reboot and suspend stress tests with this?

yes, reboot/suspend pass 100 iterations, thanks.

Change in coreboot[master]: mb/google/zork: config eMMC RST GPIO to NC

[Kevin Chiu (Code Review)]

Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: config eMMC RST GPIO to NC
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45756/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/45756/2//COMMIT_MSG@13 
PS2, Line 13: TEST
> yes, reboot/suspend pass 100 iterations, thanks.

Done

Change in coreboot[master]: mb/google/zork: config eMMC RST GPIO to NC

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: config eMMC RST GPIO to NC
......................................................................

Patch Set 3: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/45756/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/45756/2//COMMIT_MSG@13 
PS2, Line 13: TEST
> Done

Thanks Kevin!

Change in coreboot[master]: mb/google/zork: config eMMC RST GPIO to NC

[Kevin Chiu (Code Review)]

Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: config eMMC RST GPIO to NC
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45756/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/45756/1//COMMIT_MSG@14 
PS1, Line 14: check GPIO86 state is PU
> Understood. I was just curious if configuring the pad to drive high helps fix any observed issue.

hi Furquan, I think config this eMMC RST to PU or NC from default PD would help to prevent any concern/confusion even it's not really used . thank you!

Change in coreboot[master]: mb/google/zork: config eMMC RST GPIO to NC

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: config eMMC RST GPIO to NC
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45756/3/src/mainboard/google/zork/v... 
File src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c:

https://review.coreboot.org/c/coreboot/+/45756/3/src/mainboard/google/zork/v... 
PS3, Line 88: *
It would be helpful to have a comment here indicating why this pad is being configured as NC (in case someone comes here looking for the pad).

Change in coreboot[master]: mb/google/zork: config eMMC RST GPIO to NC

[Kevin Chiu (Code Review)]

Hello Kevin Chiu, build bot (Jenkins), Furquan Shaikh, Martin Roth, Bhanu Prakash Maiya, Keith Tzeng, Aaron Durbin,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45756

to look at the new patch set (#4).

Change subject: mb/google/zork: config eMMC RST GPIO to NC
......................................................................

mb/google/zork: config eMMC RST GPIO to NC

Config eMMC RST (GPIO68) to NC to prevent eMMC abnormal.

BUG=b:169222156
BRANCH=zork
TEST=emerge-zork coreboot
     eMMC DUT reboot/suspend x100 iterations pass

Change-Id: I9feb826eec8a8cdad5e2bd7efcbb1dcf96185dfd
Signed-off-by: Kevin Chiu 
---
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
1 file changed, 6 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/45756/4

Change in coreboot[master]: mb/google/zork: config eMMC RST GPIO to NC

[Kevin Chiu (Code Review)]

Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: config eMMC RST GPIO to NC
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45756/3/src/mainboard/google/zork/v... 
File src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c:

https://review.coreboot.org/c/coreboot/+/45756/3/src/mainboard/google/zork/v... 
PS3, Line 88: *
> It would be helpful to have a comment here indicating why this pad is being configured as NC (in cas […]

Done

Change in coreboot[master]: mb/google/zork: config eMMC RST GPIO to NC

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: config eMMC RST GPIO to NC
......................................................................

Patch Set 4: Code-Review+2

Change in coreboot[master]: mb/google/zork: Configure eMMC RST GPIO to NC

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded a new patch set (#5) to the change originally created by Kevin Chiu. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: Configure eMMC RST GPIO to NC
......................................................................

mb/google/zork: Configure eMMC RST GPIO to NC

Configure eMMC RST (GPIO68) to NC because this signal is unused
on the platform.

BUG=b:169222156
BRANCH=zork
TEST=emerge-zork coreboot
     eMMC DUT reboot/suspend x100 iterations pass

Change-Id: I9feb826eec8a8cdad5e2bd7efcbb1dcf96185dfd
Signed-off-by: Kevin Chiu 
---
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
1 file changed, 6 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/45756/5

Change in coreboot[master]: mb/google/zork: Configure eMMC RST GPIO to NC

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded a new patch set (#6) to the change originally created by Kevin Chiu. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: Configure eMMC RST GPIO to NC
......................................................................

mb/google/zork: Configure eMMC RST GPIO to NC

Configure eMMC RST (GPIO68) to NC because this signal is unused
on Chrome OS.

BUG=b:169222156
BRANCH=zork
TEST=emerge-zork coreboot
     eMMC DUT reboot/suspend x100 iterations pass

Change-Id: I9feb826eec8a8cdad5e2bd7efcbb1dcf96185dfd
Signed-off-by: Kevin Chiu 
Signed-off-by: Furquan Shaikh 
---
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
2 files changed, 10 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/45756/6

Change in coreboot[master]: mb/google/zork: Configure eMMC RST GPIO to NC

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: Configure eMMC RST GPIO to NC
......................................................................

Patch Set 6:

I made some minor changes to comments and also added the same change for dalboz reference. But that also means my +2 doesn't count. So, waiting for other reviewers to provide a +2.

Change in coreboot[master]: mb/google/zork: Configure eMMC RST GPIO to NC

[Raul Rangel (Code Review)]

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: Configure eMMC RST GPIO to NC
......................................................................

Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45756/6/src/mainboard/google/zork/v... 
File src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c:

https://review.coreboot.org/c/coreboot/+/45756/6/src/mainboard/google/zork/v... 
PS6, Line 82: EMMC_RESET
Can you rename this to EMMC_RESET_L. Then update the comment to additionally say that the pull up keeps this high.

Change in coreboot[master]: mb/google/zork: Configure eMMC RST GPIO to NC

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: Configure eMMC RST GPIO to NC
......................................................................

Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45756/6/src/mainboard/google/zork/v... 
File src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c:

https://review.coreboot.org/c/coreboot/+/45756/6/src/mainboard/google/zork/v... 
PS6, Line 82: EMMC_RESET
> Can you rename this to EMMC_RESET_L. […]

There is no pull up on this, right?

Change in coreboot[master]: mb/google/zork: Configure eMMC RST GPIO to NC

[Raul Rangel (Code Review)]

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: Configure eMMC RST GPIO to NC
......................................................................

Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45756/6/src/mainboard/google/zork/v... 
File src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c:

https://review.coreboot.org/c/coreboot/+/45756/6/src/mainboard/google/zork/v... 
PS6, Line 82: EMMC_RESET
> There is no pull up on this, right?

There is a pull-up on the schematic.

Change in coreboot[master]: mb/google/zork: Configure eMMC RST GPIO to NC

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: Configure eMMC RST GPIO to NC
......................................................................

Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45756/6/src/mainboard/google/zork/v... 
File src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c:

https://review.coreboot.org/c/coreboot/+/45756/6/src/mainboard/google/zork/v... 
PS6, Line 82: EMMC_RESET
> There is a pull-up on the schematic.

Are you referring to R580? That would take effect only when EMMC_RESET_L is driven high.

Change in coreboot[master]: mb/google/zork: Configure EMMC_RESET_L to drive high

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded a new patch set (#7) to the change originally created by Kevin Chiu. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: Configure EMMC_RESET_L to drive high
......................................................................

mb/google/zork: Configure EMMC_RESET_L to drive high

Configure EMMC_RESET_L (GPIO68) to drive high by default. As per JEDEC
specification for eMMC, RST_n_FUNCTION defaults to temporarily disable
reset using RST_n signal (which is connected to EMMC_RESET_L on
zork). Chrome OS platforms do not configure RST_n_FUNCTION thus making
the reset signal unused. The spec also says that there are no internal
pulls on the card and hence the RST_n signal should be driven
appropriately to prevent the input circuits from flowing unnecessary
leakage current.

Thus, even though the line remains unused, since it is connected in
hardware, this change drives EMMC_RESET_L to high.

BUG=b:169222156
BRANCH=zork
TEST=emerge-zork coreboot
     eMMC DUT reboot/suspend x100 iterations pass

Change-Id: I9feb826eec8a8cdad5e2bd7efcbb1dcf96185dfd
Signed-off-by: Kevin Chiu 
Signed-off-by: Furquan Shaikh 
---
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
2 files changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/45756/7

Change in coreboot[master]: mb/google/zork: Configure EMMC_RESET_L to drive high

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: Configure EMMC_RESET_L to drive high
......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45756/6/src/mainboard/google/zork/v... 
File src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c:

https://review.coreboot.org/c/coreboot/+/45756/6/src/mainboard/google/zork/v... 
PS6, Line 82: EMMC_RESET
> Are you referring to R580? That would take effect only when EMMC_RESET_L is driven high.

Fixed the comment. Also updated commit message.

Change in coreboot[master]: mb/google/zork: Configure EMMC_RESET_L to drive high

[Raul Rangel (Code Review)]

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: Configure EMMC_RESET_L to drive high
......................................................................

Patch Set 7: Code-Review+2

Change in coreboot[master]: mb/google/zork: Configure EMMC_RESET_L to drive high

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45756 )

Change subject: mb/google/zork: Configure EMMC_RESET_L to drive high
......................................................................

mb/google/zork: Configure EMMC_RESET_L to drive high

Configure EMMC_RESET_L (GPIO68) to drive high by default. As per JEDEC
specification for eMMC, RST_n_FUNCTION defaults to temporarily disable
reset using RST_n signal (which is connected to EMMC_RESET_L on
zork). Chrome OS platforms do not configure RST_n_FUNCTION thus making
the reset signal unused. The spec also says that there are no internal
pulls on the card and hence the RST_n signal should be driven
appropriately to prevent the input circuits from flowing unnecessary
leakage current.

Thus, even though the line remains unused, since it is connected in
hardware, this change drives EMMC_RESET_L to high.

BUG=b:169222156
BRANCH=zork
TEST=emerge-zork coreboot
     eMMC DUT reboot/suspend x100 iterations pass

Change-Id: I9feb826eec8a8cdad5e2bd7efcbb1dcf96185dfd
Signed-off-by: Kevin Chiu 
Signed-off-by: Furquan Shaikh 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45756
Tested-by: build bot (Jenkins) 
Reviewed-by: Raul Rangel 
---
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
2 files changed, 4 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Raul Rangel: Looks good to me, approved

diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
index e69b47f..696c733 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
@@ -79,8 +79,8 @@
     * access will be very slow.
     */
    PAD_GPO(GPIO_67, LOW),  // Select Camera 1 Dmic
-	/* EMMC_RESET */
-	PAD_GPO(GPIO_68, LOW),
+	/* EMMC_RESET_L */
+	PAD_GPO(GPIO_68, HIGH),
    /* RAM ID 3 */
    PAD_GPI(GPIO_69, PULL_NONE),
    /* EMMC_CLK */
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
index db1c84d..549cc58 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
@@ -85,8 +85,8 @@
     * access will be very slow.
     */
    PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic
-	/* EMMC_RESET */
-	PAD_GPO(GPIO_68, LOW),
+	/* EMMC_RESET_L */
+	PAD_GPO(GPIO_68, HIGH),
    /* FPMCU_BOOT0 - TODO: Check this */
    PAD_GPO(GPIO_69, LOW),
    /* EMMC_CLK */