Kevin Chiu has uploaded this change for review.

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mb/google/zork: de-assert eMMC RST for Morphius

de-assert eMMC RST (GPIO68) to prevent eMMC abnormal.

BUG=b:169211959
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. check GPIO86 state is PU

Change-Id: I9feb826eec8a8cdad5e2bd7efcbb1dcf96185dfd
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
---
M src/mainboard/google/zork/variants/morphius/gpio.c
1 file changed, 9 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/45756/1

diff --git a/src/mainboard/google/zork/variants/morphius/gpio.c b/src/mainboard/google/zork/variants/morphius/gpio.c
index 8da0de4..c1655fa 100644
--- a/src/mainboard/google/zork/variants/morphius/gpio.c
+++ b/src/mainboard/google/zork/variants/morphius/gpio.c
@@ -52,6 +52,8 @@
 };
 
 static const struct soc_amd_gpio morphius_bid3_gpio_set_stage_ram[] = {
+	/* EMMC_RESET */
+	PAD_GPO(GPIO_68, HIGH),
 	/* EN_DEV_BEEP_L */
 	PAD_GPO(GPIO_89, HIGH),
 	/* TP */
@@ -60,6 +62,11 @@
 	PAD_GPO(GPIO_140, HIGH),
 };
 
+static const struct soc_amd_gpio morphius_gpio_set_stage_ram[] = {
+	/* EMMC_RESET */
+	PAD_GPO(GPIO_68, HIGH),
+};
+
 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
 {
 	uint32_t board_version;
@@ -83,6 +90,6 @@
 		return morphius_bid3_gpio_set_stage_ram;
 	}
 
-	*size = 0;
-	return NULL;
+	*size = ARRAY_SIZE(morphius_gpio_set_stage_ram);
+	return morphius_gpio_set_stage_ram;
 }

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