Change in coreboot[master]: nb/intel/sandybridge: Cache cbmem and stage cache in romstage
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37200 )
Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage ......................................................................
nb/intel/sandybridge: Cache cbmem and stage cache in romstage
The compress postcar option will default to 'y' with this.
Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c 3 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37200/1
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 0502b50..1745b98 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -20,6 +20,7 @@ select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI + select ROMSTAGE_CACHED_CBMEM
if NORTHBRIDGE_INTEL_SANDYBRIDGE
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index c13ae37..441844e 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -19,6 +19,7 @@ #include <commonlib/region.h> #include <bootmode.h> #include <cf9_reset.h> +#include <cpu/x86/mtrr.h> #include <string.h> #include <arch/cpu.h> #include <device/mmio.h> @@ -422,6 +423,7 @@
report_memory_config();
+ setup_romstage_wb_cbmem_cache(); cbmem_was_inited = !cbmem_recovery(s3resume); if (!fast_boot) save_timings(&ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 29c766a..9e70fc1 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -17,6 +17,7 @@ #include <console/usb.h> #include <bootmode.h> #include <cf9_reset.h> +#include <cpu/x86/mtrr.h> #include <string.h> #include <device/device.h> #include <device/pci_ops.h> @@ -451,6 +452,7 @@ hexdump32(BIOS_ERR, mrc_var, sizeof(*mrc_var)/sizeof(u32)); }
+ setup_romstage_wb_cbmem_cache(); cbmem_was_initted = !cbmem_recovery(s3resume); if (!s3resume) save_mrc_data(&pei_data);
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37200
to look at the new patch set (#3).
Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage ......................................................................
nb/intel/sandybridge: Cache cbmem and stage cache in romstage
The compress postcar option will default to 'y' with this.
Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c 3 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37200/3
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37200
to look at the new patch set (#8).
Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage ......................................................................
nb/intel/sandybridge: Cache cbmem and stage cache in romstage
The compress postcar option will default to 'y' with this.
Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c 3 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37200/8
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37200
to look at the new patch set (#9).
Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage ......................................................................
nb/intel/sandybridge: Cache cbmem and stage cache in romstage
The compress postcar option will default to 'y' with this.
Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/model_206ax/Kconfig M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c 4 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37200/9
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37200 )
Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage ......................................................................
Patch Set 9: Code-Review+1
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37200 )
Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage ......................................................................
Patch Set 14:
Why isn't cbmem_recovery() calling the mtrr code directly on supported platforms in romstage?
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37200
to look at the new patch set (#15).
Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage ......................................................................
nb/intel/sandybridge: Cache cbmem and stage cache in romstage
The compress postcar option will default to 'y' with this.
Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/model_206ax/Kconfig M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c 4 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37200/15
Attention is currently required from: Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37200 )
Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage ......................................................................
Patch Set 15:
(1 comment)
File src/northbridge/intel/sandybridge/raminit.c:
https://review.coreboot.org/c/coreboot/+/37200/comment/e9452ba4_567266f8 PS15, Line 466: setup_romstage_wb_cbmem_cache(8 * MiB); Is this related to memmap.c function `fill_postcar_frame`?
Also, this call is only effective on the native raminit codepath.
Attention is currently required from: Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37200 )
Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage ......................................................................
Patch Set 15:
(1 comment)
File src/northbridge/intel/sandybridge/raminit.c:
https://review.coreboot.org/c/coreboot/+/37200/comment/5553599b_95b67a69 PS15, Line 466: setup_romstage_wb_cbmem_cache(8 * MiB);
Is this related to memmap.c function `fill_postcar_frame`?
Yes. The function is less smart and only uses one MTRR however.
Also, this call is only effective on the native raminit codepath.
The idea is to set it up before cbmem is up (to speed things up). It's probably a good idea to move that cbmem init + extras to a common place or provide a post cbmem_init callback for things happening after cbmem init here.
Attention is currently required from: Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37200 )
Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage ......................................................................
Patch Set 15:
(1 comment)
File src/northbridge/intel/sandybridge/raminit.c:
https://review.coreboot.org/c/coreboot/+/37200/comment/ece3d6bc_70d47958 PS15, Line 466: setup_romstage_wb_cbmem_cache(8 * MiB);
Is this related to memmap.c function `fill_postcar_frame`? […]
Ah, then I'd look into providing a x86-specific helper function. I'd also encapsulate the cbmem_was_inited thing, while at it. Note that CB:50967 touches related stuff.
Attention is currently required from: Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37200 )
Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage ......................................................................
Patch Set 15:
(1 comment)
File src/northbridge/intel/sandybridge/raminit.c:
https://review.coreboot.org/c/coreboot/+/37200/comment/dacdd8a5_d5a78b78 PS15, Line 466: setup_romstage_wb_cbmem_cache(8 * MiB);
Ah, then I'd look into providing a x86-specific helper function. I'd also encapsulate the cbmem_was_inited thing, while at it. Note that CB:50967 touches related stuff.
So ideally you'd reuse some of the postcar MTRR setup to speed up operation on cbmem. One difference is however that romstage already has some MTRR in use so that might not always works. Maybe adding a helper to return an MTRR config array to cover a certain range just like how things are done with the postcar frame could come in handy here.
Attention is currently required from: Angel Pons. Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37200
to look at the new patch set (#16).
Change subject: nb/intel/sandybridge: Cache cbmem in romstage ......................................................................
nb/intel/sandybridge: Cache cbmem in romstage
The compress postcar option will default to 'y' with this.
Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/model_206ax/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37200/16
Attention is currently required from: Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37200 )
Change subject: nb/intel/sandybridge: Cache cbmem in romstage ......................................................................
Patch Set 17:
(1 comment)
File src/northbridge/intel/sandybridge/raminit.c:
https://review.coreboot.org/c/coreboot/+/37200/comment/26a8989d_b767aed0 PS15, Line 466: setup_romstage_wb_cbmem_cache(8 * MiB);
Ah, then I'd look into providing a x86-specific helper function. […]
Done differently using a CBMEM_INIT_HOOK.
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37200?usp=email )
Change subject: nb/intel/sandybridge: Cache cbmem in romstage ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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Martin L Roth (Code Review)
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Patrick Rudolph (Code Review)