Arthur Heymans uploaded patch set #8 to this change.

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nb/intel/sandybridge: Cache cbmem and stage cache in romstage

The compress postcar option will default to 'y' with this.

Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/northbridge/intel/sandybridge/Kconfig
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
3 files changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37200/8

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9
Gerrit-Change-Number: 37200
Gerrit-PatchSet: 8
Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-MessageType: newpatchset