Attention is currently required from: Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37200 ) Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage ...................................................................... Patch Set 15: (1 comment) File src/northbridge/intel/sandybridge/raminit.c: https://review.coreboot.org/c/coreboot/+/37200/comment/ece3d6bc_70d47958 PS15, Line 466: setup_romstage_wb_cbmem_cache(8 * MiB);
Is this related to memmap.c function `fill_postcar_frame`? […] Ah, then I'd look into providing a x86-specific helper function. I'd also encapsulate the cbmem_was_inited thing, while at it. Note that CB:50967 touches related stuff.
-- To view, visit https://review.coreboot.org/c/coreboot/+/37200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9 Gerrit-Change-Number: 37200 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Attention: Arthur Heymans <arthur@aheymans.xyz> Gerrit-Comment-Date: Mon, 22 Mar 2021 20:08:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus@gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur@aheymans.xyz> Gerrit-MessageType: comment