Attention is currently required from: Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37200 ) Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage ...................................................................... Patch Set 15: (1 comment) File src/northbridge/intel/sandybridge/raminit.c: https://review.coreboot.org/c/coreboot/+/37200/comment/dacdd8a5_d5a78b78 PS15, Line 466: setup_romstage_wb_cbmem_cache(8 * MiB);
Ah, then I'd look into providing a x86-specific helper function. I'd also encapsulate the cbmem_was_inited thing, while at it. Note that CB:50967 touches related stuff.
So ideally you'd reuse some of the postcar MTRR setup to speed up operation on cbmem. One difference is however that romstage already has some MTRR in use so that might not always works. Maybe adding a helper to return an MTRR config array to cover a certain range just like how things are done with the postcar frame could come in handy here. -- To view, visit https://review.coreboot.org/c/coreboot/+/37200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9 Gerrit-Change-Number: 37200 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus@gmail.com> Gerrit-Comment-Date: Mon, 22 Mar 2021 20:15:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus@gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur@aheymans.xyz> Gerrit-MessageType: comment