Arthur Heymans uploaded patch set #15 to this change.

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nb/intel/sandybridge: Cache cbmem and stage cache in romstage

The compress postcar option will default to 'y' with this.

Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9
Signed-off-by: Arthur Heymans <>
M src/cpu/intel/model_206ax/Kconfig
M src/northbridge/intel/sandybridge/Kconfig
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
4 files changed, 7 insertions(+), 0 deletions(-)

git pull ssh:// refs/changes/00/37200/15

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9
Gerrit-Change-Number: 37200
Gerrit-PatchSet: 15
Gerrit-Owner: Arthur Heymans <>
Gerrit-Reviewer: Angel Pons <>
Gerrit-Reviewer: Arthur Heymans <>
Gerrit-Reviewer: Patrick Rudolph <>
Gerrit-Reviewer: build bot (Jenkins) <>
Gerrit-CC: Paul Menzel <>
Gerrit-MessageType: newpatchset