Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060 ......................................................................
mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060
Enable PCIE RP0 to fix DEKEL FW download failed for x4 controller (PEG 0:6:0).
TEST=No FSP error seen while loading DEKEL FW.
Change-Id: I3cd8cba02a96185803a0c0d442f3d6aa495d2642 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/49100/1
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 12cd475..4cae2fd 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -69,6 +69,7 @@ register "HybridStorageMode" = "1"
# Enable CPU PCIE RP 1 using PEG CLK 0 + register "PcieRpEnable[0]" = "1" register "PcieClkSrcUsage[0]" = "0x40"
# Enable PCU PCIE PEG Slot 1 and 2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060 ......................................................................
Patch Set 1: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060 ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49100/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/49100/1//COMMIT_MSG@9 PS1, Line 9: Enable PCIE RP0 to fix DEKEL FW download failed for x4 : controller (PEG 0:6:0). : : TEST=No FSP error seen while loading DEKEL FW. Not trying to hold up this patch, but is there a fix coming for the FSP for this? Seems unnecessary to have to load PHY FW for an unused RP.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060 ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49100/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/49100/1//COMMIT_MSG@9 PS1, Line 9: Enable PCIE RP0 to fix DEKEL FW download failed for x4 : controller (PEG 0:6:0). : : TEST=No FSP error seen while loading DEKEL FW.
Not trying to hold up this patch, but is there a fix coming for the FSP for this? Seems unnecessary […]
Or was the port meant to be enabled in the first place?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060 ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49100/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/49100/1//COMMIT_MSG@9 PS1, Line 9: Enable PCIE RP0 to fix DEKEL FW download failed for x4 : controller (PEG 0:6:0). : : TEST=No FSP error seen while loading DEKEL FW.
Or was the port meant to be enabled in the first place?
actually this root port meant to enable at first place.
Tim, this is for CPU PCIE port where we have SSD/NVME. Its expected to have DEKEL PHY FW loaded there.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060 ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49100/1/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49100/1/src/mainboard/intel/adlrvp/... PS1, Line 72: PcieRpEnable There is some disconnect here. PcieRpEnable[0] refers to PCH PCIe RP 1. And this is being enabled under the comment for CPU PCIe RP 1.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060 ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49100/1/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49100/1/src/mainboard/intel/adlrvp/... PS1, Line 71: CPU this comment is wrong. i will fix it in another CL, its not CPU RP, its PCH RP
------------------ PCH PCIe RP PreMem Config ------------------ Port[0] RpEnabled= 1 Clock[0] Usage= 40 Clock[0] ClkReq= 0
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060 ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49100/1/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49100/1/src/mainboard/intel/adlrvp/... PS1, Line 71: CPU
this comment is wrong. i will fix it in another CL, its not CPU RP, its PCH RP […]
If this is PCH RP1, what about its CLKSRC# and CLKREQ# configuration? If RP1 is using CLKSRC0 and CLKREQ0 shouldn't this configuration be:
register "PcieRpEnable[0]" = "1" register "PcieClkSrcUsage[0]" = "0" register "PcieClkSrcClkReq[0]" = "0"
Basically, what you have on line #73 is also incorrect.
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Aamir Bohra,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49100
to look at the new patch set (#2).
Change subject: mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060 ......................................................................
mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060
Enable PCIE RP0 to fix DEKEL FW download failed for x4 controller (PEG 0:6:0).
TEST=No FSP error seen while loading DEKEL FW.
Change-Id: I3cd8cba02a96185803a0c0d442f3d6aa495d2642 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/49100/2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060 ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49100/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49100/2/src/mainboard/intel/adlrvp/... PS2, Line 72: PcieRpEnable this is mostly like a bug in FSP where DEKEL FW is getting loaded based on RP0 of PCH PCIE rather CPU PCIE. But we get the FSP boot we need this W/A for now 😞
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060 ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49100/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49100/2/src/mainboard/intel/adlrvp/... PS2, Line 72: PcieRpEnable
this is mostly like a bug in FSP where DEKEL FW is getting loaded based on RP0 of PCH PCIE rather CP […]
Aha, that makes sense 😊 do you mind adding a comment here then?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060 ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49100/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49100/2/src/mainboard/intel/adlrvp/... PS2, Line 72: PcieRpEnable
Aha, that makes sense 😊 do you mind adding a comment here then?
Is there a bug capturing this? If not, can you please raise a partner issue?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060 ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49100/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49100/2/src/mainboard/intel/adlrvp/... PS2, Line 72: PcieRpEnable
Is there a bug capturing this? If not, can you please raise a partner issue?
we have internal bug file, i will raise a crossbug
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Aamir Bohra,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49100
to look at the new patch set (#3).
Change subject: mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060 ......................................................................
mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060
Enable PCIE RP0 to fix DEKEL FW download failed for x4 controller (PEG 0:6:0).
BUG=b:176940923 TEST=No FSP error seen while loading DEKEL FW.
Change-Id: I3cd8cba02a96185803a0c0d442f3d6aa495d2642 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/49100/3
Attention is currently required from: Subrata Banik. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix DEKEL FW download failed for PEG 060 ......................................................................
Patch Set 3: Code-Review+1
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49100/comment/ccebdb45_eea71c02 PS3, Line 72: register "PcieRpEnable[0]" = "1 a comment here why you're using `PcieRpEnable instead of `CpuPcieRpEnable` would be helpful here
Attention is currently required from: Subrata Banik. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Aamir Bohra,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: mb/intel/adlrvp: Fix FW download failed for PEG 060, 010 ......................................................................
mb/intel/adlrvp: Fix FW download failed for PEG 060, 010
Enable PCIE RP0 to fix DEKEL FW download failed for x4 controller (PEG 0:6:0).
Enable PCIE RP2 to fix HSPHY FW download failed for x8 controller (PEG 0:1:0)
BUG=b:176940923 TEST=No FSP error seen while loading DEKEL, HSPHY FW.
Change-Id: I3cd8cba02a96185803a0c0d442f3d6aa495d2642 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/49100/4
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix FW download failed for PEG 060, 010 ......................................................................
Patch Set 4:
(3 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49100/comment/c316f5e0_849620a1 PS1, Line 72: PcieRpEnable
There is some disconnect here. PcieRpEnable[0] refers to PCH PCIe RP 1. […]
Ack
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49100/comment/881836a1_703aefd3 PS2, Line 72: PcieRpEnable
we have internal bug file, i will raise a crossbug
Ack
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49100/comment/3af73f03_50200bfe PS3, Line 72: register "PcieRpEnable[0]" = "1
a comment here why you're using `PcieRpEnable instead of `CpuPcieRpEnable` would be helpful here
Ack
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix FW download failed for PEG 060, 010 ......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49100/comment/35e8c764_85f09eef PS1, Line 71: CPU
If this is PCH RP1, what about its CLKSRC# and CLKREQ# configuration? If RP1 is using CLKSRC0 and CL […]
Ack
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix FW download failed for PEG 060, 010 ......................................................................
Patch Set 5:
(2 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49100/comment/cd753d02_2d736e94 PS5, Line 262: device pci 1c.2 off end # RP3 Please help turn on this as well. My patch is based on device tree to set the enable bit..
https://review.coreboot.org/c/coreboot/+/49100/comment/faae7100_89943b9a PS5, Line 263: device pci 1c.3 off end # RP4 Same.
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix FW download failed for PEG 060, 010 ......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49100/comment/2336eedf_84661b27 PS5, Line 12: Enable PCIE RP2 to fix HSPHY FW download failed for x8 RP1?
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix FW download failed for PEG 060, 010 ......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49100/comment/5f16524f_a24d3ecf PS5, Line 12: Enable PCIE RP2 to fix HSPHY FW download failed for x8
RP1?
I marked the wrong place.. RP0 should be RP1
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix FW download failed for PEG 060, 010 ......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49100/comment/edcaf22e_6416485c PS5, Line 262: device pci 1c.2 off end # RP3
Please help turn on this as well. My patch is based on device tree to set the enable bit..
Eric, ideally we don't have any device in PCH RP3 and 4 its due to bug in FSP, we had to enable those UPDs. do you still want to enable this ?
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix FW download failed for PEG 060, 010 ......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49100/comment/8946b0bb_24612d98 PS5, Line 262: device pci 1c.2 off end # RP3
Eric, ideally we don't have any device in PCH RP3 and 4 its due to bug in FSP, we had to enable thos […]
Yes, or this will cause the problem with my patch.. I don't want add condition check for the WA...
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Aamir Bohra, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49100
to look at the new patch set (#6).
Change subject: mb/intel/adlrvp: Fix FW download failed for PEG 060, 010 ......................................................................
mb/intel/adlrvp: Fix FW download failed for PEG 060, 010
Enable PCIE RP0 to fix DEKEL FW download failed for x4 controller (PEG 0:6:0).
Enable PCIE RP2 to fix HSPHY FW download failed for x8 controller (PEG 0:1:0)
BUG=b:176940923 TEST=No FSP error seen while loading DEKEL, HSPHY FW.
Change-Id: I3cd8cba02a96185803a0c0d442f3d6aa495d2642 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 8 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/49100/6
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix FW download failed for PEG 060, 010 ......................................................................
Patch Set 6:
(2 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49100/comment/d440cfe3_463d133c PS5, Line 262: device pci 1c.2 off end # RP3
Yes, or this will cause the problem with my patch.. I don't want add condition check for the WA...
Ack
https://review.coreboot.org/c/coreboot/+/49100/comment/092fad9b_f21c00c5 PS5, Line 263: device pci 1c.3 off end # RP4
Same.
Ack
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Aamir Bohra, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49100
to look at the new patch set (#7).
Change subject: mb/intel/adlrvp: Fix FW download failed for PEG 060, 010 ......................................................................
mb/intel/adlrvp: Fix FW download failed for PEG 060, 010
Enable PCIE RP1 to fix DEKEL FW download failed for x4 controller (PEG 0:6:0).
Enable PCIE RP3 to fix HSPHY FW download failed for x8 controller (PEG 0:1:0)
BUG=b:176940923 TEST=No FSP error seen while loading DEKEL, HSPHY FW.
Change-Id: I3cd8cba02a96185803a0c0d442f3d6aa495d2642 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 8 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/49100/7
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix FW download failed for PEG 060, 010 ......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49100/comment/1424a825_97d1a8e8 PS5, Line 12: Enable PCIE RP2 to fix HSPHY FW download failed for x8
I marked the wrong place.. […]
Ack
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix FW download failed for PEG 060, 010 ......................................................................
Patch Set 7: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49100/comment/4fcee6dc_7f2358b4 PS7, Line 12: Enable PCIE RP3 to fix HSPHY FW download failed for x8 nit:still wrong here, RP2 is correct. Sorry for the mistake mark.
RP1: PEG60 : 0:6:0 : CPU SSD1 RP2: PEG10 : 0:1:0 : x8 CPU Slot RP3: PEG62 : 0:6:2 : CPU SSD2
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix FW download failed for PEG 060, 010 ......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49100/comment/1fbed24a_1d09f262 PS7, Line 12: Enable PCIE RP3 to fix HSPHY FW download failed for x8
nit:still wrong here, RP2 is correct. Sorry for the mistake mark. […]
Eric, i meant to say, enable PCH PCIE RP1, 3 for downloading DEKEL and HSPHY FW, i didn't mean CPU PCIE port 👍 in commit msg
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix FW download failed for PEG 060, 010 ......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49100/comment/4e5bd499_4c401dbc PS7, Line 12: Enable PCIE RP3 to fix HSPHY FW download failed for x8
Eric, i meant to say, enable PCH PCIE RP1, 3 for downloading DEKEL and HSPHY FW, i didn't mean CPU P […]
Oh, yes. Misread. Sorry.
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix FW download failed for PEG 060, 010 ......................................................................
mb/intel/adlrvp: Fix FW download failed for PEG 060, 010
Enable PCIE RP1 to fix DEKEL FW download failed for x4 controller (PEG 0:6:0).
Enable PCIE RP3 to fix HSPHY FW download failed for x8 controller (PEG 0:1:0)
BUG=b:176940923 TEST=No FSP error seen while loading DEKEL, HSPHY FW.
Change-Id: I3cd8cba02a96185803a0c0d442f3d6aa495d2642 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/49100 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 8 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 51b781c..cf9afaf 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -80,6 +80,12 @@ register "CpuPcieRpEnable[2]" = "1" register "PcieClkSrcUsage[4]" = "0x42"
+ # W/A to FSP issue where FSP is using PCH PCIE port + # enable UPD to download FW on CPU PCIE + register "PchPcieRpEnable[0]" = "1" + register "PchPcieRpEnable[2]" = "1" + register "PchPcieRpEnable[3]" = "1" + # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED"
@@ -253,8 +259,8 @@ device pci 19.2 off end # UART2 device pci 1c.0 on end # RP1 device pci 1c.1 off end # RP2 - device pci 1c.2 off end # RP3 - device pci 1c.3 off end # RP4 + device pci 1c.2 on end # RP3 # W/A to FSP issue + device pci 1c.3 on end # RP4 # W/A to FSP issue device pci 1c.4 on end # RP5 device pci 1c.5 on end # RP6 device pci 1c.6 off end # RP7
-
Angel Pons (Code Review) -
EricR Lai (Code Review)
-
Furquan Shaikh (Code Review)
-
Subrata Banik (Code Review)
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Tim Wawrzynczak (Code Review)