1 comment:
File src/mainboard/intel/adlrvp/devicetree.cb:
this comment is wrong. i will fix it in another CL, its not CPU RP, its PCH RP […]
If this is PCH RP1, what about its CLKSRC# and CLKREQ# configuration? If RP1 is using CLKSRC0 and CLKREQ0 shouldn't this configuration be:
register "PcieRpEnable[0]" = "1"
register "PcieClkSrcUsage[0]" = "0"
register "PcieClkSrcClkReq[0]" = "0"
Basically, what you have on line #73 is also incorrect.
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