Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49100 )
Change subject: mb/intel/adlrvp: Fix FW download failed for PEG 060, 010 ......................................................................
mb/intel/adlrvp: Fix FW download failed for PEG 060, 010
Enable PCIE RP1 to fix DEKEL FW download failed for x4 controller (PEG 0:6:0).
Enable PCIE RP3 to fix HSPHY FW download failed for x8 controller (PEG 0:1:0)
BUG=b:176940923 TEST=No FSP error seen while loading DEKEL, HSPHY FW.
Change-Id: I3cd8cba02a96185803a0c0d442f3d6aa495d2642 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/49100 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 8 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 51b781c..cf9afaf 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -80,6 +80,12 @@ register "CpuPcieRpEnable[2]" = "1" register "PcieClkSrcUsage[4]" = "0x42"
+ # W/A to FSP issue where FSP is using PCH PCIE port + # enable UPD to download FW on CPU PCIE + register "PchPcieRpEnable[0]" = "1" + register "PchPcieRpEnable[2]" = "1" + register "PchPcieRpEnable[3]" = "1" + # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED"
@@ -253,8 +259,8 @@ device pci 19.2 off end # UART2 device pci 1c.0 on end # RP1 device pci 1c.1 off end # RP2 - device pci 1c.2 off end # RP3 - device pci 1c.3 off end # RP4 + device pci 1c.2 on end # RP3 # W/A to FSP issue + device pci 1c.3 on end # RP4 # W/A to FSP issue device pci 1c.4 on end # RP5 device pci 1c.5 on end # RP6 device pci 1c.6 off end # RP7