Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak.
3 comments:
File src/mainboard/intel/adlrvp/devicetree.cb:
Patch Set #1, Line 72: PcieRpEnable
There is some disconnect here. PcieRpEnable[0] refers to PCH PCIe RP 1. […]
Ack
File src/mainboard/intel/adlrvp/devicetree.cb:
Patch Set #2, Line 72: PcieRpEnable
we have internal bug file, i will raise a crossbug
Ack
File src/mainboard/intel/adlrvp/devicetree.cb:
Patch Set #3, Line 72: register "PcieRpEnable[0]" = "1
a comment here why you're using `PcieRpEnable instead of `CpuPcieRpEnable` would be helpful here
Ack
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