Change in coreboot[master]: soc/intel/{apl,cnl,icl,skl,tgl}: Add comments for above 4GB mem range...
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38388 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Add comments for above 4GB mem range macro ......................................................................
soc/intel/{apl,cnl,icl,skl,tgl}: Add comments for above 4GB mem range macro
Change-Id: Ibe812031ea91932ec63adb030541b5ab5db8f425 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/icelake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/iomap.h 5 files changed, 50 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38388/1
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index e2fa462..6a617bd 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -60,6 +60,16 @@ #define EARLY_I2C_BASE_ADDRESS 0xfe020000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
+/* + * Resource for the Top of Upper Usable DRAM (TOUUD) + * TOUUD base value is TOM minus all memory range as applicable + * (ME stolen memory, reclaim memory etc). + * Base is 2^37 = 128 GB. + * Length is 2^36 = 64 GB. + * The Host interface positively decodes an address towards DRAM if the incoming + * address is less than the value programmed in this register and greater than or + * equal to 4 GB. + */ #define ABOVE_4GB_MEM_BASE_ADDRESS (128ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (64ULL * GiB)
diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index c66cde4..a920940 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -68,6 +68,16 @@
#define HECI1_BASE_ADDRESS 0xfeda2000
+/* + * Resource for the Top of Upper Usable DRAM (TOUUD) + * TOUUD base value is TOM minus all memory range as applicable + * (ME stolen memory, reclaim memory etc). + * Base is 2^38 = 256 GB. + * Length is 2^38 = 256 GB. + * The Host interface positively decodes an address towards DRAM if the incoming + * address is less than the value programmed in this register and greater than or + * equal to 4 GB. + */ #define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB)
diff --git a/src/soc/intel/icelake/include/soc/iomap.h b/src/soc/intel/icelake/include/soc/iomap.h index 50ba005..77a8851 100644 --- a/src/soc/intel/icelake/include/soc/iomap.h +++ b/src/soc/intel/icelake/include/soc/iomap.h @@ -61,6 +61,16 @@ #define VTD_BASE_ADDRESS 0xFED90000 #define VTD_BASE_SIZE 0x00004000
+/* + * Resource for the Top of Upper Usable DRAM (TOUUD) + * TOUUD base value is TOM minus all memory range as applicable + * (ME stolen memory, reclaim memory etc). + * Base is 2^38 = 256 GB. + * Length is 2^38 = 256 GB. + * The Host interface positively decodes an address towards DRAM if the incoming + * address is less than the value programmed in this register and greater than or + * equal to 4 GB. + */ #define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB)
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index b447d79..5cde8c1 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -75,6 +75,16 @@ #define PTT_TXT_BASE_ADDRESS 0xfed30800 #define PTT_PRESENT 0x00070000
+/* + * Resource for the Top of Upper Usable DRAM (TOUUD) + * TOUUD base value is TOM minus all memory range as applicable + * (ME stolen memory, reclaim memory etc). + * Base is 2^37 = 128 GB. + * Length is 2^36 = 64 GB. + * The Host interface positively decodes an address towards DRAM if the incoming + * address is less than the value programmed in this register and greater than or + * equal to 4 GB. + */ #define ABOVE_4GB_MEM_BASE_ADDRESS (128ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (64ULL * GiB)
diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index 72ac25f..72d0a6d 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -67,6 +67,16 @@ #define VTD_BASE_ADDRESS 0xFED90000 #define VTD_BASE_SIZE 0x00004000
+/* + * Resource for the Top of Upper Usable DRAM (TOUUD) + * TOUUD base value is TOM minus all memory range as applicable + * (ME stolen memory, reclaim memory etc). + * Base is 2^38 = 256 GB. + * Length is 2^38 = 256 GB. + * The Host interface positively decodes an address towards DRAM if the incoming + * address is less than the value programmed in this register and greater than or + * equal to 4 GB. + */ #define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB)
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38388 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Add comments for above 4GB mem range macro ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38388/1/src/soc/intel/apollolake/in... File src/soc/intel/apollolake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/38388/1/src/soc/intel/apollolake/in... PS1, Line 68: * Length is 2^36 = 64 GB. Forgive me for being dense, but this base and length are the upper end of TOUUD (base in this case). But it is lowered according to the amount of memory in the system?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38388 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Add comments for above 4GB mem range macro ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38388/1/src/soc/intel/apollolake/in... File src/soc/intel/apollolake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/38388/1/src/soc/intel/apollolake/in... PS1, Line 68: * Length is 2^36 = 64 GB.
Forgive me for being dense, but this base and length are the upper end of TOUUD (base in this case). […]
i understand what your mean Aaron but how do i write the same is my confusion :( Do you think a diagram might help in comment section ?
Hello Aaron Durbin, Patrick Rudolph, Angel Pons, Lance Zhao, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38388
to look at the new patch set (#2).
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Add comments for above 4GB mem range macro ......................................................................
soc/intel/{apl,cnl,icl,skl,tgl}: Add comments for above 4GB mem range macro
Change-Id: Ibe812031ea91932ec63adb030541b5ab5db8f425 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/icelake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/iomap.h 5 files changed, 185 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38388/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38388 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Add comments for above 4GB mem range macro ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Thanks for the nice memory map diagrams, much appreciated :)
https://review.coreboot.org/c/coreboot/+/38388/1/src/soc/intel/apollolake/in... File src/soc/intel/apollolake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/38388/1/src/soc/intel/apollolake/in... PS1, Line 68: * Length is 2^36 = 64 GB.
i understand what your mean Aaron but how do i write the same is my confusion :( […]
As I understand it, the upper DRAM range goes from 4GiB till TOUUD.
However, I'm not sure what the 128 GiB base and 64 GiB size are, and what they correspond to in the diagram. :S
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38388 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Add comments for above 4GB mem range macro ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38388/1/src/soc/intel/apollolake/in... File src/soc/intel/apollolake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/38388/1/src/soc/intel/apollolake/in... PS1, Line 68: * Length is 2^36 = 64 GB.
As I understand it, the upper DRAM range goes from 4GiB till TOUUD.
you are right that BIOS has to program minimum value for TOUUD is 4 GB when reclaim memory is not enable in case of amount of system memory is less than 4GB, else the concept of reclaim memory comes in where amount of memory remapped is the range between TOLUD and 4 GB. And this memory would be above 4GB till TOUUD base.
you can refer to 326769 doc number
However, I'm not sure what the 128 GiB base and 64 GiB size are, and what they correspond to in the diagram. :S
This is telling that TOUUD base of 128GB (above 4GB range) and its till 128GB + 64 GB = 192GB in size
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38388 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Add comments for above 4GB mem range macro ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38388/1/src/soc/intel/apollolake/in... File src/soc/intel/apollolake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/38388/1/src/soc/intel/apollolake/in... PS1, Line 68: * Length is 2^36 = 64 GB.
As I understand it, the upper DRAM range goes from 4GiB till TOUUD. […]
Right, after reading doc 326769, I think I understand now.
There are three chunks of usable DRAM (main memory): 1: DRAM below 4GB, host sees it below 4GB: Main memory below 4GB 2: DRAM above 4GB, host sees it above 4GB: Main memory above 4GB 3: DRAM below 4GB, host sees it above 4GB: Reclaimed / remapped memory
Reclaiming / remapping allows using the memory below 4GB that ends up hidden behind the PCI config space. When decoding Host --> DRAM, the MC hardware does something like this:
if (remap_base <= host_addr && host_addr <= remap_limit) { phys_addr = host_addr - remap_base + (4GB - (remap_limit - remap_base));
/* Equivalent expression */ phys_addr = host_addr + 4GB - remap_limit; }
Using the register names, this means that:
Host [REMAPBASE..REMAPLIMIT] --> DRAM [TOLUD..4GB]
The doc describes the memory map programming steps:
1. Determine TOM: TOM = installed DRAM size. Can be derived from the values of MCHBAR MAD_DIMM_CHx registers.
2. Determine TOM minus Intel ME stolen size This is usually done by asking the ME how much memory it wants. It is then programmed into MESEG_BASE and MESEG_MASK.
3. Determine MMIO allocation This is the size of the MMIO window below 4GB. It can be fixed to a large enough value when the hardware supports remapping.
4. Determine TOLUD TOLUD = 4GB - MMIO window size.
5. Determine graphics stolen base BDSM = TOLUD - GFX data stolen memory size. This depends on the value of the GGC register.
6. Determine graphics GTT stolen base BGSM = BDSM - GFX GTT stolen memory size. This also depends on the GGC register values.
7. Determine TSEG base TSEG base = BGSM - TSEG size. It is usually 8MB, but can be larger if also allocating IEDRAM (Intel Enhanced Debug).
8. Determine remap base/limit If not remapping, then REMAPBASE and REMAPLIMIT should be left at their default values. If remapping, then: REMAPBASE = MAX(4GB, TOM - ME UMA size) REMAPLIMIT = (TOM - ME UMA size) + 4GB - TOLUD - 1MB
Note that the 1MB is because of granularity. On Westmere, the granularity is 64 MiB.
9. Determine TOUUD It is right above REMAPLIMIT: TOUUD = REMAPLIMIT + 1
Then, TOUUD is actually above the remapped range.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38388 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Add comments for above 4GB mem range macro ......................................................................
Patch Set 2:
@Angle: do we need this CL or shall we abandon this ?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38388 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Add comments for above 4GB mem range macro ......................................................................
Patch Set 2:
Patch Set 2:
@Angle: do we need this CL or shall we abandon this ?
It's not strictly necessary (it's just adding comments). I haven't had much time to revisit it, but I like the idea. I wouldn't abandon it for now.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38388 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Add comments for above 4GB mem range macro ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
@Angle: do we need this CL or shall we abandon this ?
It's not strictly necessary (it's just adding comments). I haven't had much time to revisit it, but I like the idea. I wouldn't abandon it for now.
Thanks Angle if you could spent some time in next 2 week would be good. we have some tracker to check open CL and need to explain why. if we need this CL we will merge else i will abandon after 2 week checking with you
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38388 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Add comments for above 4GB mem range macro ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
Patch Set 2:
@Angle: do we need this CL or shall we abandon this ?
It's not strictly necessary (it's just adding comments). I haven't had much time to revisit it, but I like the idea. I wouldn't abandon it for now.
Thanks Angle if you could spent some time in next 2 week would be good. we have some tracker to check open CL and need to explain why. if we need this CL we will merge else i will abandon after 2 week checking with you
Hi Subrata,
I'm afraid I haven't had much time to revisit this change. I would abandon it for now, if it's needed it can be restored later.
Subrata Banik has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/38388 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Add comments for above 4GB mem range macro ......................................................................
Abandoned
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38388 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Add comments for above 4GB mem range macro ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
Patch Set 2:
Patch Set 2:
@Angle: do we need this CL or shall we abandon this ?
It's not strictly necessary (it's just adding comments). I haven't had much time to revisit it, but I like the idea. I wouldn't abandon it for now.
Thanks Angle if you could spent some time in next 2 week would be good. we have some tracker to check open CL and need to explain why. if we need this CL we will merge else i will abandon after 2 week checking with you
Hi Subrata,
I'm afraid I haven't had much time to revisit this change. I would abandon it for now, if it's needed it can be restored later.
Thanks Angel
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Aaron Durbin (Code Review) -
Angel Pons (Code Review)
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Subrata Banik (Code Review)