Subrata Banik has uploaded this change for review.

View Change

soc/intel/{apl,cnl,icl,skl,tgl}: Add comments for above 4GB mem range macro

Change-Id: Ibe812031ea91932ec63adb030541b5ab5db8f425
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/soc/intel/apollolake/include/soc/iomap.h
M src/soc/intel/cannonlake/include/soc/iomap.h
M src/soc/intel/icelake/include/soc/iomap.h
M src/soc/intel/skylake/include/soc/iomap.h
M src/soc/intel/tigerlake/include/soc/iomap.h
5 files changed, 50 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38388/1

diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index e2fa462..6a617bd 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -60,6 +60,16 @@
 #define EARLY_I2C_BASE_ADDRESS		0xfe020000
 #define EARLY_I2C_BASE(x)	(EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
 
+/*
+ * Resource for the Top of Upper Usable DRAM (TOUUD)
+ * TOUUD base value is TOM minus all memory range as applicable
+ * (ME stolen memory, reclaim memory etc).
+ * Base is 2^37 = 128 GB.
+ * Length is 2^36 = 64 GB.
+ * The Host interface positively decodes an address towards DRAM if the incoming
+ * address is less than the value programmed in this register and greater than or
+ * equal to 4 GB.
+ */
 #define ABOVE_4GB_MEM_BASE_ADDRESS	(128ULL * GiB)
 #define ABOVE_4GB_MEM_BASE_SIZE	(64ULL * GiB)
 
diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h
index c66cde4..a920940 100644
--- a/src/soc/intel/cannonlake/include/soc/iomap.h
+++ b/src/soc/intel/cannonlake/include/soc/iomap.h
@@ -68,6 +68,16 @@
 
 #define HECI1_BASE_ADDRESS	0xfeda2000
 
+/*
+ * Resource for the Top of Upper Usable DRAM (TOUUD)
+ * TOUUD base value is TOM minus all memory range as applicable
+ * (ME stolen memory, reclaim memory etc).
+ * Base is 2^38 = 256 GB.
+ * Length is 2^38 = 256 GB.
+ * The Host interface positively decodes an address towards DRAM if the incoming
+ * address is less than the value programmed in this register and greater than or
+ * equal to 4 GB.
+ */
 #define ABOVE_4GB_MEM_BASE_ADDRESS	(256ULL * GiB)
 #define ABOVE_4GB_MEM_BASE_SIZE	(256ULL * GiB)
 
diff --git a/src/soc/intel/icelake/include/soc/iomap.h b/src/soc/intel/icelake/include/soc/iomap.h
index 50ba005..77a8851 100644
--- a/src/soc/intel/icelake/include/soc/iomap.h
+++ b/src/soc/intel/icelake/include/soc/iomap.h
@@ -61,6 +61,16 @@
 #define VTD_BASE_ADDRESS	0xFED90000
 #define VTD_BASE_SIZE		0x00004000
 
+/*
+ * Resource for the Top of Upper Usable DRAM (TOUUD)
+ * TOUUD base value is TOM minus all memory range as applicable
+ * (ME stolen memory, reclaim memory etc).
+ * Base is 2^38 = 256 GB.
+ * Length is 2^38 = 256 GB.
+ * The Host interface positively decodes an address towards DRAM if the incoming
+ * address is less than the value programmed in this register and greater than or
+ * equal to 4 GB.
+ */
 #define ABOVE_4GB_MEM_BASE_ADDRESS	(256ULL * GiB)
 #define ABOVE_4GB_MEM_BASE_SIZE	(256ULL * GiB)
 
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index b447d79..5cde8c1 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -75,6 +75,16 @@
 #define PTT_TXT_BASE_ADDRESS	0xfed30800
 #define PTT_PRESENT		0x00070000
 
+/*
+ * Resource for the Top of Upper Usable DRAM (TOUUD)
+ * TOUUD base value is TOM minus all memory range as applicable
+ * (ME stolen memory, reclaim memory etc).
+ * Base is 2^37 = 128 GB.
+ * Length is 2^36 = 64 GB.
+ * The Host interface positively decodes an address towards DRAM if the incoming
+ * address is less than the value programmed in this register and greater than or
+ * equal to 4 GB.
+ */
 #define ABOVE_4GB_MEM_BASE_ADDRESS	(128ULL * GiB)
 #define ABOVE_4GB_MEM_BASE_SIZE	(64ULL * GiB)
 
diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h
index 72ac25f..72d0a6d 100644
--- a/src/soc/intel/tigerlake/include/soc/iomap.h
+++ b/src/soc/intel/tigerlake/include/soc/iomap.h
@@ -67,6 +67,16 @@
 #define VTD_BASE_ADDRESS	0xFED90000
 #define VTD_BASE_SIZE		0x00004000
 
+/*
+ * Resource for the Top of Upper Usable DRAM (TOUUD)
+ * TOUUD base value is TOM minus all memory range as applicable
+ * (ME stolen memory, reclaim memory etc).
+ * Base is 2^38 = 256 GB.
+ * Length is 2^38 = 256 GB.
+ * The Host interface positively decodes an address towards DRAM if the incoming
+ * address is less than the value programmed in this register and greater than or
+ * equal to 4 GB.
+ */
 #define ABOVE_4GB_MEM_BASE_ADDRESS	(256ULL * GiB)
 #define ABOVE_4GB_MEM_BASE_SIZE	(256ULL * GiB)
 

To view, visit change 38388. To unsubscribe, or for help writing mail filters, visit settings.