Thejaswani Putta has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
mb/google/drallion: Add new mainboard
Drallion is a new mainboard using Intel Comet Lake SOC, It also uses the Chrome EC, that will be enabled in a seperate commit
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4 --- A src/mainboard/google/drallion/Kconfig A src/mainboard/google/drallion/Kconfig.name A src/mainboard/google/drallion/Makefile.inc A src/mainboard/google/drallion/acpi_tables.c A src/mainboard/google/drallion/board_info.txt A src/mainboard/google/drallion/bootblock.c A src/mainboard/google/drallion/chromeos.c A src/mainboard/google/drallion/chromeos.fmd A src/mainboard/google/drallion/dsdt.asl A src/mainboard/google/drallion/ec.c A src/mainboard/google/drallion/hda_verb.c A src/mainboard/google/drallion/ramstage.c A src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/sku.c A src/mainboard/google/drallion/smihandler.c A src/mainboard/google/drallion/variants/drallion/Makefile.inc A src/mainboard/google/drallion/variants/drallion/devicetree.cb A src/mainboard/google/drallion/variants/drallion/gpio.c A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl A src/mainboard/google/drallion/variants/drallion/include/variant/ec.h A src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h A src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h A src/mainboard/google/drallion/variants/drallion/include/variant/variant.h 24 files changed, 1,823 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34497/1
diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig new file mode 100644 index 0000000..f27ba24 --- /dev/null +++ b/src/mainboard/google/drallion/Kconfig @@ -0,0 +1,107 @@ + +config BOARD_GOOGLE_BASEBOARD_DRALLION + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_INTEL_ISH if BOARD_GOOGLE_DRALLION + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EC_GOOGLE_WILCO + select GENERIC_SPD_BIN + select GOOGLE_SMBIOS_MAINBOARD_VERSION + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_I2C_TPM_CR50 + select MAINBOARD_HAS_TPM2 + select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP if BOARD_GOOGLE_DRALLION + select SYSTEM_TYPE_CONVERTIBLE if BOARD_GOOGLE_DRALLION + select TPM2 + select MAINBOARD_USES_IFD_EC_REGION + select MAINBOARD_USES_IFD_GBE_REGION if BOARD_GOOGLE_DRALLION + select USE_SAR + select SAR_ENABLE + +if BOARD_GOOGLE_BASEBOARD_DRALLION + +config CHROMEOS + bool + default y + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_BOOT_LEGACY + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config DRIVER_TPM_I2C_BUS + hex + default 0x4 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 + +config TPM_TIS_ACPI_INTERRUPT + int + default 82 # GPE0_DW2_18 (GPP_D18) + +config POWER_OFF_ON_CR50_UPDATE + bool + default n + +config GBB_HWID + string + depends on CHROMEOS + default "DRALLION TEST 3556" if BOARD_GOOGLE_DRALLION + +config MAINBOARD_DIR + string + default "google/drallion + +config MAINBOARD_FAMILY + string + default "Google_Drallion" if BOARD_GOOGLE_DRALLION + +config MAINBOARD_PART_NUMBER + string + default "Drallion" if BOARD_GOOGLE_DRALLION + +config MAINBOARD_VENDOR + string + default "Google" + +config MAX_CPUS + int + default 8 + +config UART_FOR_CONSOLE + int + default 2 + +config VARIANT_DIR + string + default "drallion" if BOARD_GOOGLE_DRALLION + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config VBOOT + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + select VBOOT_LID_SWITCH + +endif # BOARD_GOOGLE_BASEBOARD_DRALLION diff --git a/src/mainboard/google/drallion/Kconfig.name b/src/mainboard/google/drallion/Kconfig.name new file mode 100644 index 0000000..b471a22 --- /dev/null +++ b/src/mainboard/google/drallion/Kconfig.name @@ -0,0 +1,9 @@ +comment "Drallion" + +config BOARD_GOOGLE_DRALLION + bool "-> Drallion" + select BOARD_GOOGLE_BASEBOARD_DRALLION + +config BOARD_GOOGLE_DRALLION + bool "-> Drallion" + select BOARD_GOOGLE_BASEBOARD_DRALLION diff --git a/src/mainboard/google/drallion/Makefile.inc b/src/mainboard/google/drallion/Makefile.inc new file mode 100644 index 0000000..7e23044 --- /dev/null +++ b/src/mainboard/google/drallion/Makefile.inc @@ -0,0 +1,38 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2018 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c + +ramstage-y += ramstage.c +ramstage-y += sku.c + +romstage-y += romstage.c + +smm-y += smihandler.c + +bootblock-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c + +bootblock-$(CONFIG_EC_GOOGLE_WILCO) += ec.c +ramstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c +romstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c +verstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/drallion/acpi_tables.c b/src/mainboard/google/drallion/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/drallion/acpi_tables.c diff --git a/src/mainboard/google/drallion/board_info.txt b/src/mainboard/google/drallion/board_info.txt new file mode 100644 index 0000000..dfc194b --- /dev/null +++ b/src/mainboard/google/drallion/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Drallion +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/drallion/bootblock.c b/src/mainboard/google/drallion/bootblock.c new file mode 100644 index 0000000..bee9b1a --- /dev/null +++ b/src/mainboard/google/drallion/bootblock.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <ec/google/wilco/bootblock.h> +#include <soc/gpio.h> +#include <variant/gpio.h> + +static void early_config_gpio(void) +{ + const struct pad_config *early_gpio_table; + size_t num_gpios = 0; + + early_gpio_table = variant_early_gpio_table(&num_gpios); + gpio_configure_pads(early_gpio_table, num_gpios); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); + wilco_ec_early_init(); +} diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c new file mode 100644 index 0000000..7aaf401 --- /dev/null +++ b/src/mainboard/google/drallion/chromeos.c @@ -0,0 +1,127 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <variant/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <security/tpm/tss.h> +#include <device/device.h> +#include <intelblocks/pmclib.h> +#include <soc/pmc.h> +#include <soc/pci_devs.h> + +enum rec_mode_state { + REC_MODE_UNINITIALIZED, + REC_MODE_NOT_REQUESTED, + REC_MODE_REQUESTED, +}; + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {GPIO_PCH_WP, ACTIVE_HIGH, get_write_protect_state(), + "write protect"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +static int cros_get_gpio_value(int type) +{ + const struct cros_gpio *cros_gpios; + size_t i, num_gpios = 0; + + cros_gpios = variant_cros_gpios(&num_gpios); + + for (i = 0; i < num_gpios; i++) { + const struct cros_gpio *gpio = &cros_gpios[i]; + if (gpio->type == type) { + int state = gpio_get(gpio->gpio_num); + if (gpio->polarity == CROS_GPIO_ACTIVE_LOW) + return !state; + else + return state; + } + } + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *cros_gpios; + size_t num_gpios = 0; + + cros_gpios = variant_cros_gpios(&num_gpios); + + chromeos_acpi_gpio_generate(cros_gpios, num_gpios); +} + +int get_write_protect_state(void) +{ + return cros_get_gpio_value(CROS_GPIO_WP); +} + +int get_recovery_mode_switch(void) +{ + static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED; + enum rec_mode_state state = REC_MODE_NOT_REQUESTED; + uint8_t cr50_state = 0; + + /* Check cached state, since TPM will only tell us the first time */ + if (saved_rec_mode != REC_MODE_UNINITIALIZED) + return saved_rec_mode == REC_MODE_REQUESTED; + + /* + * Read one-time recovery request from cr50 in verstage only since + * the TPM driver won't be set up in time for other stages like romstage + * and the value from the TPM would be wrong anyway since the verstage + * read would have cleared the value on the TPM. + * + * The TPM recovery request is passed between stages through the + * vboot_get_shared_data or cbmem depending on stage. + */ + if (ENV_VERSTAGE && + tlcl_cr50_get_recovery_button(&cr50_state) == TPM_SUCCESS && + cr50_state) + state = REC_MODE_REQUESTED; + + /* Read state from the GPIO controlled by servo. */ + if (cros_get_gpio_value(CROS_GPIO_REC)) + state = REC_MODE_REQUESTED; + + /* Store the state in case this is called again in verstage. */ + saved_rec_mode = state; + + return state == REC_MODE_REQUESTED; +} + +int get_lid_switch(void) +{ + return 1; +} + +void mainboard_prepare_cr50_reset(void) +{ +#if ENV_RAMSTAGE + /* Ensure system powers up after CR50 reset */ + pmc_set_afterg3(MAINBOARD_POWER_STATE_ON); +#endif +} diff --git a/src/mainboard/google/drallion/chromeos.fmd b/src/mainboard/google/drallion/chromeos.fmd new file mode 100644 index 0000000..ece0eda --- /dev/null +++ b/src/mainboard/google/drallion/chromeos.fmd @@ -0,0 +1,49 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x400000 { + SI_DESC@0x0 0x1000 + SI_EC@0x1000 0x100000 + SI_GBE(PRESERVE)@0x101000 0x2000 + SI_ME@0x103000 0x2f9000 + SI_PDR(PRESERVE)@0x3fc000 0x4000 + } + SI_BIOS@0x400000 0x1c00000 { + RW_DIAG@0x0 0x12d0000 { + RW_LEGACY(CBFS)@0x0 0x12c0000 + DIAG_NVRAM@0x12c0000 0x10000 + } + RW_SECTION_A@0x12d0000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x26ffc0 + RW_FWID_A@0x27ffc0 0x40 + } + RW_SECTION_B@0x1550000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x26ffc0 + RW_FWID_B@0x27ffc0 0x40 + } + RW_MISC@0x17d0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x28000 0x2000 + RW_NVRAM(PRESERVE)@0x2a000 0x6000 + } + WP_RO@0x1800000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x3f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x300000 + } + } + } +} diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl new file mode 100644 index 0000000..58e0704 --- /dev/null +++ b/src/mainboard/google/drallion/dsdt.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/ec.h> + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + /* Some generic macros */ + #include <soc/intel/cannonlake/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/cannonlake/acpi/globalnvs.asl> + + /* CPU */ + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + } + /* Per board variant mainboard hooks. */ + #include <variant/acpi/mainboard.asl> + } + +#if CONFIG(CHROMEOS) + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + /* VPD support */ + #include <vendorcode/google/chromeos/acpi/vpd.asl> + /* MAC address passthru */ + #include <vendorcode/google/chromeos/acpi/amac.asl> +#endif + + /* Chipset specific sleep states */ + #include <soc/intel/cannonlake/acpi/sleepstates.asl> + + /* Low power idle table */ + #include <soc/intel/cannonlake/acpi/lpit.asl> + +#if CONFIG(EC_GOOGLE_WILCO) + /* Chrome OS Embedded Controller */ + Scope (_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/wilco/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/wilco/acpi/ec.asl> + } +#endif + + /* Dynamic Platform Thermal Framework */ + Scope (_SB) + { + /* Per board variant specific definitions. */ + #include <variant/acpi/dptf.asl> + /* Include soc specific DPTF changes */ + #include <soc/intel/cannonlake/acpi/dptf.asl> + /* Include common dptf ASL files */ + #include <soc/intel/common/acpi/dptf/dptf.asl> + } +} diff --git a/src/mainboard/google/drallion/ec.c b/src/mainboard/google/drallion/ec.c new file mode 100644 index 0000000..fd8e84f --- /dev/null +++ b/src/mainboard/google/drallion/ec.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <ec/google/wilco/commands.h> +#include <variant/ec.h> + +void mainboard_post(uint8_t value) +{ + wilco_ec_save_post_code(value); +} diff --git a/src/mainboard/google/drallion/hda_verb.c b/src/mainboard/google/drallion/hda_verb.c new file mode 100644 index 0000000..9ab4778 --- /dev/null +++ b/src/mainboard/google/drallion/hda_verb.c @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "variant/hda_verb.h" diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c new file mode 100644 index 0000000..811afa1 --- /dev/null +++ b/src/mainboard/google/drallion/ramstage.c @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <boardid.h> +#include <drivers/vpd/vpd.h> +#include <smbios.h> +#include <soc/gpio.h> +#include <soc/ramstage.h> +#include <variant/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#if CONFIG(GENERATE_SMBIOS_TABLES) +#define VPD_KEY_SYSTEM_SERIAL "serial_number" +#define VPD_KEY_MAINBOARD_SERIAL "mlb_serial_number" +#define VPD_SERIAL_LEN 64 + +const char *smbios_system_serial_number(void) +{ + static char serial[VPD_SERIAL_LEN]; + if (vpd_gets(VPD_KEY_SYSTEM_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) + return serial; + return ""; +} + +const char *smbios_mainboard_serial_number(void) +{ + static char serial[VPD_SERIAL_LEN]; + if (vpd_gets(VPD_KEY_MAINBOARD_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) + return serial; + return ""; +} + +/* mainboard silk screen shows DIMM-A and DIMM-B */ +void smbios_fill_dimm_locator(const struct dimm_info *dimm, + struct smbios_type17 *t) +{ + switch (dimm->channel_num) { + case 0: + t->device_locator = smbios_add_string(t->eos, "DIMM-A"); + break; + case 1: + t->device_locator = smbios_add_string(t->eos, "DIMM-B"); + break; + default: + t->device_locator = smbios_add_string(t->eos, "UNKNOWN"); + break; + } +} +#endif + +static const struct pad_config gpio_unused[] = { +/* SUSWARN# */ PAD_NC(GPP_A13, NONE), +/* SUSACK# */ PAD_NC(GPP_A15, NONE), +/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), +/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), +}; + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + const struct pad_config *gpio_table; + size_t num_gpios; + + gpio_table = variant_gpio_table(&num_gpios); + cnl_configure_pads(gpio_table, num_gpios); + + /* Disable unused pads for devices with board ID > 2 */ + if (board_id() > 2) + gpio_configure_pads(gpio_unused, ARRAY_SIZE(gpio_unused)); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c new file mode 100644 index 0000000..20eee7f --- /dev/null +++ b/src/mainboard/google/drallion/romstage.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/google/wilco/romstage.h> +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> + +static const struct cnl_mb_cfg memcfg = { + /* Access memory info through SMBUS. */ + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa0}, + }, + .spd[1] = {.read_type = NOT_EXISTING}, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa4}, + }, + .spd[3] = {.read_type = NOT_EXISTING}, + + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = {0, 1, 4, 5, 2, 3, 6, 7}, + .dqs_map[DDR_CH1] = {0, 1, 4, 5, 2, 3, 6, 7}, + + /* Baseboard uses 121, 81 and 100 rcomp resistors */ + .rcomp_resistor = {121, 81, 100}, + + /* + * Baseboard Rcomp target values. + */ + .rcomp_targets = {100, 40, 20, 20, 26}, + + /* Disable Early Command Training */ + .ect = 0, + + /* Base on board design */ + .vref_ca_config = 2, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + wilco_ec_romstage_init(); + + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +} diff --git a/src/mainboard/google/drallion/sku.c b/src/mainboard/google/drallion/sku.c new file mode 100644 index 0000000..d0b48f0 --- /dev/null +++ b/src/mainboard/google/drallion/sku.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/google/wilco/commands.h> +#include <smbios.h> +#include <variant/variant.h> + +uint32_t sku_id(void) +{ + if (wilco_ec_signed_fw()) + return VARIANT_SKU_ID_SIGNED_EC; + else + return VARIANT_SKU_ID; +} + +const char *smbios_system_sku(void) +{ + if (wilco_ec_signed_fw()) + return VARIANT_SKU_NAME_SIGNED_EC; + else + return VARIANT_SKU_NAME; +} diff --git a/src/mainboard/google/drallion/smihandler.c b/src/mainboard/google/drallion/smihandler.c new file mode 100644 index 0000000..0efcaa9 --- /dev/null +++ b/src/mainboard/google/drallion/smihandler.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/smm.h> +#include <ec/google/wilco/smm.h> +#include <soc/smm.h> +#include <variant/ec.h> + +void mainboard_smi_espi_handler(void) +{ + wilco_ec_smi_espi(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + wilco_ec_smi_sleep(slp_typ); +} + +int mainboard_smi_apmc(u8 apmc) +{ + wilco_ec_smi_apmc(apmc); + return 0; +} diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc new file mode 100644 index 0000000..2bf028e --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2018 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += gpio.c +ramstage-y += gpio.c +romstage-y += gpio.c +verstage-y += gpio.c diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb new file mode 100644 index 0000000..5b0d7a4 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -0,0 +1,389 @@ +chip soc/intel/cannonlake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "PMC_GPP_A" + register "gpe0_dw1" = "PMC_GPP_C" + register "gpe0_dw2" = "PMC_GPP_D" + + # EC host command ranges + register "gen1_dec" = "0x00040931" # 0x930-0x937 + register "gen2_dec" = "0x00040941" # 0x940-0x947 + register "gen3_dec" = "0x000c0951" # 0x950-0x95f + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "HeciEnabled" = "0" + register "SataSalpSupport" = "1" + register "SataMode" = "Sata_AHCI" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[2]" = "1" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "4" # 4s + register "PchPmSlpSusMinAssert" = "4" # 4s + register "PchPmSlpAMinAssert" = "4" # 2s + register "PchUnlockGpioPads" = "1" + + register "speed_shift_enable" = "1" + register "psys_pmax" = "140" + register "s0ix_enable" = "1" + register "dptf_enable" = "1" + register "dmipwroptimize" = "1" + register "satapwroptimize" = "1" + register "tdp_pl1_override" = "25" + register "tdp_pl2_override" = "51" + register "Device4Enable" = "1" + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" + register "SlowSlewRateForSa" = "0" + register "SlowSlewRateForFivr" = "2" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + # Enable DDC for DDI port B + register "DdiPortBDdc" = "1" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 6A | 70A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #+----------------+-------+-------+-------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(6), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(70), + .voltage_limit = 1520, + .ac_loadline = 180, + .dc_loadline = 180, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Intel Common SoC Config + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port + register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port + register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port + register "usb2_ports[3]" = "USB2_PORT_EMPTY" + register "usb2_ports[4]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera + register "usb2_ports[6]" = "{ + .enable = 1, \ + .ocpin = OC_SKIP, \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_28P15MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ + }" # WWAN + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Left Type-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN + register "usb3_ports[4]" = "USB3_PORT_EMPTY" + register "usb3_ports[5]" = "USB3_PORT_EMPTY" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| I2C0 | Touchscreen | + #| I2C1 | Touchpad | + #| I2C4 | H1 TPM | + #+-------------------+---------------------------+ + + register "tcc_offset" = "1" + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 52, + .fall_time_ns = 110, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 52, + .fall_time_ns = 110, + .data_hold_time_ns = 330, + }, + .i2c[4] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 36, + .fall_time_ns = 99, + }, + }" + + # PCIe port 10 for M.2 2230 WLAN + register "PcieRpEnable[9]" = "1" + register "PcieClkSrcUsage[2]" = "9" + register "PcieClkSrcClkReq[2]" = "2" + + # PCIe port 11 for card reader + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + register "PcieClkSrcUsage[1]" = "10" + register "PcieClkSrcClkReq[1]" = "1" + + # PCIe port 13 for M.2 2280 SSD + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[4]" = "12" + register "PcieClkSrcClkReq[4]" = "4" + + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 on # Integrated Sensor Hub + chip drivers/intel/ish + register "firmware_name" = ""drallion_ish.bin"" + device generic 0 on end + end + end + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""USH"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.7 on end + end + chip drivers/usb/acpi + register "desc" = ""Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.8 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H15)" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.3 on end + end + end + end + end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + chip drivers/intel/wifi + register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + end + device pci 14.5 off end # SDCard + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM48E2"" + register "generic.desc" = ""Wacom Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.reset_delay_ms" = "20" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "generic.enable_delay_ms" = "55" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0A on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "probed" = "1" + device i2c 2c on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)" + device i2c 50 on end + end + end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 (USB) + device pci 1c.1 off end # PCI Express Port 2 (USB) + device pci 1c.2 off end # PCI Express Port 3 (USB) + device pci 1c.3 off end # PCI Express Port 4 (USB) + device pci 1c.4 off end # PCI Express Port 5 (USB) + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + end # PCI Express Port 9 + device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.2 on end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + end # PCI Express Port 13 (x4) + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on + chip ec/google/wilco + device pnp 0c09.0 on end + end + end # LPC/eSPI + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c new file mode 100644 index 0000000..ff0240c --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -0,0 +1,279 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <variant/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_NC(GPP_A0, NONE), +/* ESPI_IO0 */ +/* ESPI_IO1 */ +/* ESPI_IO2 */ +/* ESPI_IO3 */ +/* ESPI_CS# */ +/* SERIRQ */ +/* PIRQA# */ PAD_NC(GPP_A7, NONE), +/* CLKRUN# */ PAD_NC(GPP_A8, NONE), +/* ESPI_CLK */ +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), +/* PME# */ PAD_NC(GPP_A11, NONE), + /* ISH_LID_CL#_TAB */ +/* ISH_GP6 */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF2), +/* SUSWARN# */ PAD_NC(GPP_A13, NONE), +/* ESPI_RESET# */ +/* SUSACK# */ PAD_NC(GPP_A15, NONE), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), + /* ISH_ACC1_INT# */ +/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* ISH_ACC2_INT# */ +/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), + /* ISH_NB_MODE */ +/* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), + /* ISH_LID_CL#_NB */ +/* ISH_GP5 */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + +/* CORE_VID0 */ +/* CORE_VID1 */ +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ +/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ + /* LAN_CLKREQ_CPU_N */ +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* CARD_CLKREQ_CPU_N */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* WLAN_CLKREQ_CPU_N */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* WWAN_CLKREQ_CPU_N */ +/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* SSD_CKLREQ_CPU_N */ +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* TBT_CLKREQ_CPU_N (nostuff) */ +/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), /* PRIM_CORE_OPT_DIS (nostuff) */ +/* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */ +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* RTC_DET# */ +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ +/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), +/* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), + +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */ +/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */ +/* SMBALERT# */ PAD_NC(GPP_C2, DN_20K), +/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SMBCLK */ +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_SMBDATA */ +/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K), +/* SM1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */ +/* SM1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */ +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), /* PCH_TBT_PERST# (nostuff) */ +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */ +/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */ +/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, + EDGE_SINGLE), /* SIO_EXT_WAKE# */ +/* UART1_TXD */ PAD_NC(GPP_C13, NONE), +/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */ +/* UART1_CTS# */ PAD_NC(GPP_C15, NONE), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */ +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */ +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ +/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), +/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, + LEVEL, NONE), /* TS_INT# */ + +/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), +/* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* ISH_LAN# */ +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TBT_FORCE_PWR (nostuff) */ + /* ISH_I2C0_ACC_SDA */ +/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* ISH_I2C0_ACC_SCL */ +/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), /* IR_CAM_DET# */ +/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), +/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */ +/* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), + /* ISH_CPU_UART0_RX */ +/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), + /* ISH_CPU_UART0_TX */ +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), +/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */ +/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ +/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), +/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), +/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 1, DEEP), /* WWAN_BB_RST# */ +/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* WWAN_GPIO_PERST# */ +/* I2S_MCLK */ PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP, + EDGE_SINGLE), /* WWAN_GPIO_WAKE# */ + +/* SATAXPCIE0 */ PAD_NC(GPP_E0, NONE), + /* M3042_PCIE#_SATA */ +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* M2880_PCIE_SATA# */ +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), +/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */ +/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */ +/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */ +/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ +/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ +/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ +/* USB2_OC2# */ PAD_NC(GPP_E11, NONE), +/* USB2_OC3# */ PAD_NC(GPP_E12, NONE), +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */ +/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_SCL_CPU */ +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_SDA_CPU */ +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), + +/* CNV_PA_BLANKING */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_COEX3 */ +/* GPP_F1 */ PAD_NC(GPP_F1, NONE), +/* GPP_F2 */ PAD_NC(GPP_F2, NONE), +/* GPP_F3 */ PAD_NC(GPP_F3, NONE), +/* CNV_BRI_DT */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), +/* CNV_BRI_RSP */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), +/* CNV_RGI_DT */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), +/* CNV_RGI_RSP */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), +/* CNV_MFUART2_RXD */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* CNV_COEX2 */ +/* CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* CNV_COEX1 */ +/* GPP_F10 */ PAD_NC(GPP_F10, NONE), +/* EMMC_CMD */ PAD_NC(GPP_F11, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F19, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F20, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_RESET# */ PAD_NC(GPP_F22, NONE), +/* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE), + +/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */ +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */ +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */ +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */ +/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */ +/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */ +/* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, DEEP), /* SPK_DET# */ + +/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), +/* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */ +/* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */ +/* I2S2_RXD */ PAD_NC(GPP_H3, NONE), +/* I2C2_SDA */ PAD_NC(GPP_H4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_H5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_H6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_H7, NONE), +/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ +/* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */ +/* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */ +/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), +/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ +/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), +/* DPPF_CTRLDATA */ PAD_NC(GPP_H17, NONE), +/* CPU_C10_GATE# */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10_GATE# */ +/* TIMESYNC0 */ PAD_NC(GPP_H19, NONE), +/* IMGCLKOUT1 */ PAD_NC(GPP_H20, NONE), +/* GPP_H21 */ PAD_NC(GPP_H21, NONE), +/* GPP_H22 */ PAD_NC(GPP_H22, NONE), /* RTD3_CIO_PWR_EN (nostuff) */ +/* GPP_H23 */ PAD_NC(GPP_H23, NONE), + +/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */ +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */ +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */ +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */ +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */ +/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */ +/* GPD7 */ PAD_NC(GPD7, NONE), /* TBT_RTD3_WAKE# (nostuff) */ +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK */ +/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */ +/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */ +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */ +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ +/* SSD RESET pin will stay low first */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ +/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ +/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ +/* RESET# need to stay low before FULL_CARD_POWER_OFF assert */ +/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ +/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ +/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ +/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..73e1dec --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 98 +#define DPTF_CPU_CRITICAL 108 + +/* Skin Sensor for CPU VR temperature monitor */ +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "Skin" +#define DPTF_TSR0_PASSIVE 55 +#define DPTF_TSR0_CRITICAL 100 + +/* Memory Sensor for DDR temperature monitor */ +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "DDR" +#define DPTF_TSR1_PASSIVE 53 +#define DPTF_TSR1_CRITICAL 100 + +/* M.2 Sensor for Ambient temperature monitor */ +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "Ambient" +#define DPTF_TSR2_PASSIVE 38 +#define DPTF_TSR2_CRITICAL 93 + +#undef DPTF_ENABLE_FAN_CONTROL +#undef DPTF_ENABLE_CHARGER + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 500, 100, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Skin (TSR0) */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 400, 40, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on DDR (TSR1) */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR1, 300, 50, 2, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR2) */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR2, 1000, 100, 1, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 21000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 51000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..41121d2 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CAM_EN GPP_B11 /* Active low */ +#define TS_PD GPP_E7 + +/* Method called from LPIT prior to enter s0ix state */ +Method (MS0X, 1) +{ + If (Arg0) { + /* Turn off camera power */ + _SB.PCI0.STXS (CAM_EN) + } Else { + /* Turn on camera power */ + _SB.PCI0.CTXS (CAM_EN) + } +} + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) +{ + _SB.PCI0.LPCB.EC0.PTS (Arg0) + + /* Clear touch screen pd pin to avoid leakage */ + _SB.PCI0.CTXS (TS_PD) +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) +{ + _SB.PCI0.LPCB.EC0.WAK (Arg0) +} diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h new file mode 100644 index 0000000..01a17b5 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* EC wake pin */ +#define EC_WAKE_PIN GPE0_DW1_12 + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* Enable PS/2 keyboard */ +#define SIO_EC_ENABLE_PS2K + +/* Enable DPTF */ +#define EC_ENABLE_DPTF + +#endif diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h new file mode 100644 index 0000000..f7e0403 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* Flash Write Protect */ +#define GPIO_PCH_WP GPP_E15 + +/* Recovery mode */ +#define GPIO_REC_MODE GPP_E8 + +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +struct cros_gpio; +const struct cros_gpio *variant_cros_gpios(size_t *num); + +#endif diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h b/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h new file mode 100644 index 0000000..10fbaf1 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h @@ -0,0 +1,209 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_HDA_VERB_H +#define MAINBOARD_HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0295, // Codec Vendor / Device ID: Realtek ALC3204 + 0xffffffff, // Subsystem ID + 0x0000002b, // Number of jacks (NID entries) + + /* Rest Codec First */ + AZALIA_RESET(0x1), + /* NID 0x01, HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0x0, 0x102808b6), + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(0x0, 0x12, 0xb7a60130), + AZALIA_PIN_CFG(0x0, 0x13, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x16, 0x40000000), + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x19, 0x04a11030), + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1d, 0x40c00001), + AZALIA_PIN_CFG(0x0, 0x1e, 0x421212f2), + AZALIA_PIN_CFG(0x0, 0x21, 0x04211020), + + /* D reset */ + 0x0205003C, + 0x0204F254, + 0x0205003C, + 0x0204F214, + /* JD1 - 2port JD mode */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + /* Set TRS type-1 */ + 0x02050045, + 0x02045289, + 0x02050049, + 0x02040049, + /* Set TRS type-2 + Set UAJ Line2 vref(ALC3254) */ + 0x0205004A, + 0x0204A830, + 0x02050063, + 0x0204CF00, + /* NID 0x20 set class-D to 2W@4ohm (+12dB gain) + * + Set sine tone gain(0x34) */ + 0x02050038, + 0x02043909, + 0x05C50000, + 0x05C43482, + /* AGC-1 Disable + (Front Gain=0dB ) */ + 0x05D50006, + 0x05D44C50, + 0x05D50002, + 0x05D44004, + /* AGC-2 (Backt Boost Gain= -0.375dB ,Limiter = -3dB) */ + 0x05D50003, + 0x05D45E5E, + 0x05D50001, + 0x05D4D788, + /* AGC-3 + AGC Enable */ + 0x05D50009, + 0x05D451FF, + 0x05D50006, + 0x05D44E50, + /* HP-JD Enable +Nokia type */ + 0x0205004A, + 0x02042010, + 0x02050008, + 0x02046A0C, + /* EAPD set to verb-control + I2C Un-use+ DVDD3.3V */ + 0x02050010, + 0x02040020, + 0x02050034, + 0x0204A23D, + /* Class D silent detection Enable -84dB threshold */ + 0x02050030, + 0x02049000, + 0x02050037, + 0x0204FE15, + /* Disable EQ + set 250Hz 3rd High Pass filter */ + 0x05350000, + 0x0534203A, + 0x05350000, + 0x0534203A, + /* Left Channel-1 */ + 0x0535001d, + 0x05340800, + 0x0535001e, + 0x05340800, + /* Left Channel-2 */ + 0x05350003, + 0x05341EF8, + 0x05350004, + 0x05340000, + /* Left Channel-3 */ + 0x05350005, + 0x053403EE, + 0x05350006, + 0x0534FA60, + /* Left Channel-4 */ + 0x05350007, + 0x05341E10, + 0x05350008, + 0x05347B86, + /* Left Channel-5 */ + 0x05350009, + 0x053401F7, + 0x0535000A, + 0x05349FB6, + /* Left Channel-6 */ + 0x0535000B, + 0x05341C00, + 0x0535000C, + 0x05340000, + /* Left Channel-7 */ + 0x0535000D, + 0x05340200, + 0x0535000E, + 0x05340000, + /* Right Channel-1 */ + 0x05450000, + 0x05442000, + 0x0545001d, + 0x05440800, + /* Right Channel-2 */ + 0x0545001e, + 0x05440800, + 0x05450003, + 0x05441EF8, + /* Right Channel-3 */ + 0x05450004, + 0x05440000, + 0x05450005, + 0x054403EE, + /* Right Channel-4 */ + 0x05450006, + 0x0544FA60, + 0x05450007, + 0x05441E10, + /* Right Channel-5 */ + 0x05450008, + 0x05447B86, + 0x05450009, + 0x054401F7, + /* Right Channel-6 */ + 0x0545000A, + 0x05449FB6, + 0x0545000B, + 0x05441C00, + /* Right Channel-7 */ + 0x0545000C, + 0x05440000, + 0x0545000D, + 0x05440200, + /* Right Channel-8 + EQ Update & Enable */ + 0x0545000E, + 0x05440000, + 0x05350000, + 0x0534E03A, + /* Enable all Microphone */ + 0x0205000D, + 0x0204A023, + 0x0205000D, + 0x0204A023, + /* Enable Internal Speaker (NID14) */ + 0x0205000F, + 0x02040000, + 0x0205000F, + 0x02040000, +}; + +const u32 pc_beep_verbs[] = { + /* PCBeep pass through to NID14 for ePSA test-1 */ + 0x02050036, + 0x020477D7, + 0x0143B000, + 0x01470740, + /* PCBeep pass through to NID14 for ePSA test-2 */ + 0x01470C02, + 0x01470C02, + 0x01470C02, + 0x01470C02, +}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h new file mode 100644 index 0000000..156a8f6 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* Need to update for Drallion with right SKU IDs + Arcada is SKU ID 2 and 4 */ +#define VARIANT_SKU_ID 2 +#define VARIANT_SKU_NAME "sku2" +#define VARIANT_SKU_ID_SIGNED_EC 4 +#define VARIANT_SKU_NAME_SIGNED_EC "sku4" + +#endif
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34497/1/src/mainboard/google/dralli... File src/mainboard/google/drallion/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/34497/1/src/mainboard/google/dralli... PS1, Line 7: config BOARD_GOOGLE_DRALLION : bool "-> Drallion" : select BOARD_GOOGLE_BASEBOARD_DRALLION You'll need to delete this second instance - This is the reason your build is failing.
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34497/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34497/1//COMMIT_MSG@9 PS1, Line 9: can you mention that you copied sarien board as a starting point, and changed soc to CML.
https://review.coreboot.org/c/coreboot/+/34497/1//COMMIT_MSG@10 PS1, Line 10: uses the Chrome EC, that will be enabled in a seperate commit it is not using Chrome EC
Hello Pratikkumar V Prajapati, AndreX Andraos, Bernardo Perez Priego, Mathew King, Selma Bensaid, John Zhao, Bora Guvendik, build bot (Jenkins), Krzysztof M Sywula, Martin Roth, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34497
to look at the new patch set (#2).
Change subject: mb/google/drallion: Add new mainboard ......................................................................
mb/google/drallion: Add new mainboard
Drallion is a new mainboard using Intel Comet Lake SOC & Wilco EC As a starting point, I took mainboard/sarien as the reference code and modified WHL to Comet Lake.
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4 --- A src/mainboard/google/drallion/Kconfig A src/mainboard/google/drallion/Kconfig.name A src/mainboard/google/drallion/Makefile.inc A src/mainboard/google/drallion/acpi_tables.c A src/mainboard/google/drallion/board_info.txt A src/mainboard/google/drallion/bootblock.c A src/mainboard/google/drallion/chromeos.c A src/mainboard/google/drallion/chromeos.fmd A src/mainboard/google/drallion/dsdt.asl A src/mainboard/google/drallion/ec.c A src/mainboard/google/drallion/hda_verb.c A src/mainboard/google/drallion/ramstage.c A src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/sku.c A src/mainboard/google/drallion/smihandler.c A src/mainboard/google/drallion/variants/drallion/Makefile.inc A src/mainboard/google/drallion/variants/drallion/devicetree.cb A src/mainboard/google/drallion/variants/drallion/gpio.c A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl A src/mainboard/google/drallion/variants/drallion/include/variant/ec.h A src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h A src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h A src/mainboard/google/drallion/variants/drallion/include/variant/variant.h 24 files changed, 1,820 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34497/2
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34497/2/src/mainboard/google/dralli... File src/mainboard/google/drallion/Kconfig:
https://review.coreboot.org/c/coreboot/+/34497/2/src/mainboard/google/dralli... PS2, Line 72: "google/drallion missing "
Hello Pratikkumar V Prajapati, AndreX Andraos, Bernardo Perez Priego, Mathew King, Selma Bensaid, John Zhao, Bora Guvendik, build bot (Jenkins), Krzysztof M Sywula, Martin Roth, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34497
to look at the new patch set (#3).
Change subject: mb/google/drallion: Add new mainboard ......................................................................
mb/google/drallion: Add new mainboard
Drallion is a new mainboard using Intel Comet Lake SOC & Wilco EC As a starting point, I took mainboard/sarien as the reference code and modified WHL to Comet Lake.
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4 --- A src/mainboard/google/drallion/Kconfig A src/mainboard/google/drallion/Kconfig.name A src/mainboard/google/drallion/Makefile.inc A src/mainboard/google/drallion/acpi_tables.c A src/mainboard/google/drallion/board_info.txt A src/mainboard/google/drallion/bootblock.c A src/mainboard/google/drallion/chromeos.c A src/mainboard/google/drallion/chromeos.fmd A src/mainboard/google/drallion/dsdt.asl A src/mainboard/google/drallion/ec.c A src/mainboard/google/drallion/hda_verb.c A src/mainboard/google/drallion/ramstage.c A src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/sku.c A src/mainboard/google/drallion/smihandler.c A src/mainboard/google/drallion/variants/drallion/Makefile.inc A src/mainboard/google/drallion/variants/drallion/devicetree.cb A src/mainboard/google/drallion/variants/drallion/gpio.c A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl A src/mainboard/google/drallion/variants/drallion/include/variant/ec.h A src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h A src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h A src/mainboard/google/drallion/variants/drallion/include/variant/variant.h 24 files changed, 1,820 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34497/3
Hello Bernardo Perez Priego, Selma Bensaid, Duncan Laurie, John Zhao, Bora Guvendik, build bot (Jenkins), Patrick Georgi, Pratikkumar V Prajapati, AndreX Andraos, Mathew King, Krzysztof M Sywula, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34497
to look at the new patch set (#4).
Change subject: mb/google/drallion: Add new mainboard ......................................................................
mb/google/drallion: Add new mainboard
Drallion is a new mainboard using Intel Comet Lake SOC & Wilco EC As a starting point, I took mainboard/sarien as the reference code and modified WHL to Comet Lake.
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4 --- A src/mainboard/google/drallion/Kconfig A src/mainboard/google/drallion/Kconfig.name A src/mainboard/google/drallion/Makefile.inc A src/mainboard/google/drallion/acpi_tables.c A src/mainboard/google/drallion/board_info.txt A src/mainboard/google/drallion/bootblock.c A src/mainboard/google/drallion/chromeos.c A src/mainboard/google/drallion/chromeos.fmd A src/mainboard/google/drallion/dsdt.asl A src/mainboard/google/drallion/ec.c A src/mainboard/google/drallion/hda_verb.c A src/mainboard/google/drallion/ramstage.c A src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/sku.c A src/mainboard/google/drallion/smihandler.c A src/mainboard/google/drallion/variants/drallion/Makefile.inc A src/mainboard/google/drallion/variants/drallion/devicetree.cb A src/mainboard/google/drallion/variants/drallion/gpio.c A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl A src/mainboard/google/drallion/variants/drallion/include/variant/ec.h A src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h A src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h A src/mainboard/google/drallion/variants/drallion/include/variant/variant.h 24 files changed, 1,819 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34497/4
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 4:
(7 comments)
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... File src/mainboard/google/drallion/Kconfig:
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... PS4, Line 7: if BOARD_GOOGLE_DRALLION not needed? (throughout)
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... PS4, Line 23: select SYSTEM_TYPE_LAPTOP if BOARD_GOOGLE_DRALLION : select SYSTEM_TYPE_CONVERTIBLE if BOARD_GOOGLE_DRALLION Need to pick one here to avoid confusion.
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... PS4, Line 27: select MAINBOARD_USES_IFD_GBE_REGION if BOARD_GOOGLE_DRALLION can remove
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... File src/mainboard/google/drallion/ramstage.c:
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... PS4, Line 79: /* Disable unused pads for devices with board ID > 2 */ : if (board_id() > 2) : gpio_configure_pads(gpio_unused, ARRAY_SIZE(gpio_unused)); The board id check is probably not needed.
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... PS4, Line 62: cannonlake_memcfg_init cometlake?
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... PS4, Line 1: cannonlake cometlake
(I'm ignoring the rest of this file as I don't have block diagram here)
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/include/variant/variant.h:
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... PS4, Line 19: /* Need to update for Drallion with right SKU IDs : Arcada is SKU ID 2 and 4 */ : #define VARIANT_SKU_ID 2 : #define VARIANT_SKU_NAME "sku2" : #define VARIANT_SKU_ID_SIGNED_EC 4 : #define VARIANT_SKU_NAME_SIGNED_EC "sku4" This needs to be defined still, but probably at least remove the "Arcada" string.
Hello Bernardo Perez Priego, Selma Bensaid, Duncan Laurie, John Zhao, Bora Guvendik, build bot (Jenkins), Patrick Georgi, Pratikkumar V Prajapati, AndreX Andraos, Mathew King, Krzysztof M Sywula, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34497
to look at the new patch set (#5).
Change subject: mb/google/drallion: Add new mainboard ......................................................................
mb/google/drallion: Add new mainboard
Drallion is a new mainboard using Intel Comet Lake SOC & Wilco EC As a starting point, I took mainboard/sarien as the reference code and modified WHL to Comet Lake.
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4 --- A src/mainboard/google/drallion/Kconfig A src/mainboard/google/drallion/Kconfig.name A src/mainboard/google/drallion/Makefile.inc A src/mainboard/google/drallion/acpi_tables.c A src/mainboard/google/drallion/board_info.txt A src/mainboard/google/drallion/bootblock.c A src/mainboard/google/drallion/chromeos.c A src/mainboard/google/drallion/chromeos.fmd A src/mainboard/google/drallion/dsdt.asl A src/mainboard/google/drallion/ec.c A src/mainboard/google/drallion/hda_verb.c A src/mainboard/google/drallion/ramstage.c A src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/sku.c A src/mainboard/google/drallion/smihandler.c A src/mainboard/google/drallion/variants/drallion/Makefile.inc A src/mainboard/google/drallion/variants/drallion/devicetree.cb A src/mainboard/google/drallion/variants/drallion/gpio.c A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl A src/mainboard/google/drallion/variants/drallion/include/variant/ec.h A src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h A src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h A src/mainboard/google/drallion/variants/drallion/include/variant/variant.h 24 files changed, 1,817 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34497/5
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 5:
(10 comments)
https://review.coreboot.org/c/coreboot/+/34497/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34497/1//COMMIT_MSG@9 PS1, Line 9:
can you mention that you copied sarien board as a starting point, and changed soc to CML.
Done
https://review.coreboot.org/c/coreboot/+/34497/1//COMMIT_MSG@10 PS1, Line 10: uses the Chrome EC, that will be enabled in a seperate commit
it is not using Chrome EC
Modified to Wilco EC
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... File src/mainboard/google/drallion/Kconfig:
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... PS4, Line 7: if BOARD_GOOGLE_DRALLION
not needed? (throughout)
Done
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... PS4, Line 23: select SYSTEM_TYPE_LAPTOP if BOARD_GOOGLE_DRALLION : select SYSTEM_TYPE_CONVERTIBLE if BOARD_GOOGLE_DRALLION
Need to pick one here to avoid confusion.
Done
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... PS4, Line 27: select MAINBOARD_USES_IFD_GBE_REGION if BOARD_GOOGLE_DRALLION
can remove
Arcada uses GBE region. May I know why to remove it for Drallion?
https://review.coreboot.org/c/coreboot/+/34497/1/src/mainboard/google/dralli... File src/mainboard/google/drallion/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/34497/1/src/mainboard/google/dralli... PS1, Line 7: config BOARD_GOOGLE_DRALLION : bool "-> Drallion" : select BOARD_GOOGLE_BASEBOARD_DRALLION
You'll need to delete this second instance - This is the reason your build is failing.
Agree, done.
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... File src/mainboard/google/drallion/ramstage.c:
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... PS4, Line 79: /* Disable unused pads for devices with board ID > 2 */ : if (board_id() > 2) : gpio_configure_pads(gpio_unused, ARRAY_SIZE(gpio_unused));
The board id check is probably not needed.
For the EV drallion boards we will be using the Arcada and Sarien boards with its SOC replaced by Cometlake. I am not sure if this check is required in that case or not. Please advice!
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... PS4, Line 62: cannonlake_memcfg_init
cometlake?
Done
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... PS4, Line 1: cannonlake
cometlake […]
Done
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/include/variant/variant.h:
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... PS4, Line 19: /* Need to update for Drallion with right SKU IDs : Arcada is SKU ID 2 and 4 */ : #define VARIANT_SKU_ID 2 : #define VARIANT_SKU_NAME "sku2" : #define VARIANT_SKU_ID_SIGNED_EC 4 : #define VARIANT_SKU_NAME_SIGNED_EC "sku4"
This needs to be defined still, but probably at least remove the "Arcada" string.
Done
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 5:
(6 comments)
https://review.coreboot.org/c/coreboot/+/34497/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34497/1//COMMIT_MSG@9 PS1, Line 9:
Done
Done
https://review.coreboot.org/c/coreboot/+/34497/1//COMMIT_MSG@9 PS1, Line 9:
Done
Done
https://review.coreboot.org/c/coreboot/+/34497/1//COMMIT_MSG@10 PS1, Line 10: uses the Chrome EC, that will be enabled in a seperate commit
Modified to Wilco EC
Done
https://review.coreboot.org/c/coreboot/+/34497/1//COMMIT_MSG@10 PS1, Line 10: uses the Chrome EC, that will be enabled in a seperate commit
Modified to Wilco EC
Done
https://review.coreboot.org/c/coreboot/+/34497/2/src/mainboard/google/dralli... File src/mainboard/google/drallion/Kconfig:
https://review.coreboot.org/c/coreboot/+/34497/2/src/mainboard/google/dralli... PS2, Line 72: "google/drallion
missing "
Done
https://review.coreboot.org/c/coreboot/+/34497/1/src/mainboard/google/dralli... File src/mainboard/google/drallion/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/34497/1/src/mainboard/google/dralli... PS1, Line 7: config BOARD_GOOGLE_DRALLION : bool "-> Drallion" : select BOARD_GOOGLE_BASEBOARD_DRALLION
Agree, done.
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34497/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34497/5//COMMIT_MSG@9 PS5, Line 9: Drallion is a new mainboard using Intel Comet Lake SOC & Wilco EC Please add a dot at the end of the sentence.
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34497/5/src/mainboard/google/dralli... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/34497/5/src/mainboard/google/dralli... PS5, Line 62: cometlake_memcfg_init I think this should be cannonlake_memcfg_init, hatch uses cannonlake_memcfg_init as well.
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34497/5/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34497/5/src/mainboard/google/dralli... PS5, Line 1: cometlake cannonlake is what hatch uses
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34497/5/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34497/5/src/mainboard/google/dralli... PS5, Line 1: cometlake
cannonlake is what hatch uses
yes it does, sorry I should have taken a closer look before recommending this.
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 5:
Since so much of this leverages soc/intel/cannonlake and the existing sarien/arcada devices does it make sense to have this be another variant of mb/google/sarien?
Hello Bernardo Perez Priego, Selma Bensaid, Duncan Laurie, John Zhao, Bora Guvendik, build bot (Jenkins), Patrick Georgi, Pratikkumar V Prajapati, AndreX Andraos, Mathew King, Krzysztof M Sywula, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34497
to look at the new patch set (#6).
Change subject: mb/google/drallion: Add new mainboard ......................................................................
mb/google/drallion: Add new mainboard
Drallion is a new mainboard using Intel Comet Lake SOC & Wilco EC. As a starting point, I took mainboard/sarien as the reference code and modified WHL to Comet Lake.
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4 --- A src/mainboard/google/drallion/Kconfig A src/mainboard/google/drallion/Kconfig.name A src/mainboard/google/drallion/Makefile.inc A src/mainboard/google/drallion/acpi_tables.c A src/mainboard/google/drallion/board_info.txt A src/mainboard/google/drallion/bootblock.c A src/mainboard/google/drallion/chromeos.c A src/mainboard/google/drallion/chromeos.fmd A src/mainboard/google/drallion/dsdt.asl A src/mainboard/google/drallion/ec.c A src/mainboard/google/drallion/hda_verb.c A src/mainboard/google/drallion/ramstage.c A src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/sku.c A src/mainboard/google/drallion/smihandler.c A src/mainboard/google/drallion/variants/drallion/Makefile.inc A src/mainboard/google/drallion/variants/drallion/devicetree.cb A src/mainboard/google/drallion/variants/drallion/gpio.c A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl A src/mainboard/google/drallion/variants/drallion/include/variant/ec.h A src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h A src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h A src/mainboard/google/drallion/variants/drallion/include/variant/variant.h 24 files changed, 1,817 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34497/6
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 6:
Patch Set 5:
(1 comment)
Done.
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34497/5/src/mainboard/google/dralli... File src/mainboard/google/drallion/romstage.c:
https://review.coreboot.org/c/coreboot/+/34497/5/src/mainboard/google/dralli... PS5, Line 62: cometlake_memcfg_init
I think this should be cannonlake_memcfg_init, hatch uses cannonlake_memcfg_init as well.
Done
https://review.coreboot.org/c/coreboot/+/34497/5/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34497/5/src/mainboard/google/dralli... PS5, Line 1: cometlake
yes it does, sorry I should have taken a closer look before recommending this.
Done
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 6:
Patch Set 5:
Since so much of this leverages soc/intel/cannonlake and the existing sarien/arcada devices does it make sense to have this be another variant of mb/google/sarien?
Drallion EV uses sarien/arcada boards with cometlake SOC. But from Drallion EVT, the boards are different in memory, Audio codec, WIFI modules and if we add it as a variant now, we might have to move the code again in the EVT phase. Also, since the SOC is different it would be good if we don't add it as a Sarien Variant. Please advice!
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 6: Code-Review+1
Patch Set 6:
Patch Set 5:
Since so much of this leverages soc/intel/cannonlake and the existing sarien/arcada devices does it make sense to have this be another variant of mb/google/sarien?
Drallion EV uses sarien/arcada boards with cometlake SOC. But from Drallion EVT, the boards are different in memory, Audio codec, WIFI modules and if we add it as a variant now, we might have to move the code again in the EVT phase. Also, since the SOC is different it would be good if we don't add it as a Sarien Variant. Please advice!
I discussed this with Duncan and we are going to keep drallion as its own mainboard and not a sarien variant.
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 6:
Patch Set 6: Code-Review+1
Patch Set 6:
Patch Set 5:
Since so much of this leverages soc/intel/cannonlake and the existing sarien/arcada devices does it make sense to have this be another variant of mb/google/sarien?
Drallion EV uses sarien/arcada boards with cometlake SOC. But from Drallion EVT, the boards are different in memory, Audio codec, WIFI modules and if we add it as a variant now, we might have to move the code again in the EVT phase. Also, since the SOC is different it would be good if we don't add it as a Sarien Variant. Please advice!
I discussed this with Duncan and we are going to keep drallion as its own mainboard and not a sarien variant.
Great, Thanks!
Hello Bernardo Perez Priego, Selma Bensaid, Duncan Laurie, John Zhao, Bora Guvendik, build bot (Jenkins), Patrick Georgi, Pratikkumar V Prajapati, AndreX Andraos, Mathew King, Krzysztof M Sywula, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34497
to look at the new patch set (#7).
Change subject: mb/google/drallion: Add new mainboard ......................................................................
mb/google/drallion: Add new mainboard
Drallion is a new mainboard using Intel Comet Lake SOC. As a starting point, I took mainboard/sarien as the reference codeand modified WHL to Comet Lake.
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4 --- A src/mainboard/google/drallion/Kconfig A src/mainboard/google/drallion/Kconfig.name A src/mainboard/google/drallion/Makefile.inc A src/mainboard/google/drallion/acpi_tables.c A src/mainboard/google/drallion/board_info.txt A src/mainboard/google/drallion/bootblock.c A src/mainboard/google/drallion/chromeos.c A src/mainboard/google/drallion/chromeos.fmd A src/mainboard/google/drallion/dsdt.asl A src/mainboard/google/drallion/ec.c A src/mainboard/google/drallion/hda_verb.c A src/mainboard/google/drallion/ramstage.c A src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/sku.c A src/mainboard/google/drallion/smihandler.c A src/mainboard/google/drallion/variants/drallion/Makefile.inc A src/mainboard/google/drallion/variants/drallion/devicetree.cb A src/mainboard/google/drallion/variants/drallion/gpio.c A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl A src/mainboard/google/drallion/variants/drallion/include/variant/ec.h A src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h A src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h A src/mainboard/google/drallion/variants/drallion/include/variant/variant.h 24 files changed, 1,817 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34497/7
Hello Bernardo Perez Priego, Selma Bensaid, Duncan Laurie, John Zhao, Bora Guvendik, build bot (Jenkins), Patrick Georgi, Pratikkumar V Prajapati, AndreX Andraos, Mathew King, Krzysztof M Sywula, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34497
to look at the new patch set (#8).
Change subject: mb/google/drallion: Add new mainboard ......................................................................
mb/google/drallion: Add new mainboard
Drallion is a new mainboard using Intel Comet Lake SOC. As a starting point, I took mainboard/sarien as the reference code and modified WHL to Comet Lake.
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4 --- A src/mainboard/google/drallion/Kconfig A src/mainboard/google/drallion/Kconfig.name A src/mainboard/google/drallion/Makefile.inc A src/mainboard/google/drallion/acpi_tables.c A src/mainboard/google/drallion/board_info.txt A src/mainboard/google/drallion/bootblock.c A src/mainboard/google/drallion/chromeos.c A src/mainboard/google/drallion/chromeos.fmd A src/mainboard/google/drallion/dsdt.asl A src/mainboard/google/drallion/ec.c A src/mainboard/google/drallion/hda_verb.c A src/mainboard/google/drallion/ramstage.c A src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/sku.c A src/mainboard/google/drallion/smihandler.c A src/mainboard/google/drallion/variants/drallion/Makefile.inc A src/mainboard/google/drallion/variants/drallion/devicetree.cb A src/mainboard/google/drallion/variants/drallion/gpio.c A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl A src/mainboard/google/drallion/variants/drallion/include/variant/ec.h A src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h A src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h A src/mainboard/google/drallion/variants/drallion/include/variant/variant.h 24 files changed, 1,817 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34497/8
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 8:
Please add Documentation as well, that answers the following question: Which flash IC does it use? Where does the flash reside? Can you flash in-circuit? Are there debug headers? Can you provide a picture of the flash IC? What was tested and what works/does not?
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 8:
Patch Set 8:
Please add Documentation as well, that answers the following question: Which flash IC does it use? Where does the flash reside? Can you flash in-circuit? Are there debug headers? Can you provide a picture of the flash IC? What was tested and what works/does not?
Hi Patrick,
This is an unreleased Chromebook and that is not public information yet.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 8:
Patch Set 8:
Please add Documentation as well, that answers the following question: Which flash IC does it use? Where does the flash reside? Can you flash in-circuit? Are there debug headers? Can you provide a picture of the flash IC? What was tested and what works/does not?
Patrick, You might want to add the above list to documentation about what you'd like to see for new mainboards that we can point people to. Obviously we can't give out this information right now, but we could create a bug to add this information when the chromebook is released.
Maybe make a template page for new devices?
We could add a field to board_info.txt - Unreleased/Released (date)/No longer for sale. If it's marked as released, we could require documentation.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 8: Code-Review-1
Patch Set 8:
Patch Set 8:
Please add Documentation as well, that answers the following question: Which flash IC does it use? Where does the flash reside? Can you flash in-circuit? Are there debug headers? Can you provide a picture of the flash IC? What was tested and what works/does not?
Patrick, You might want to add the above list to documentation about what you'd like to see for new mainboards that we can point people to. Obviously we can't give out this information right now, but we could create a bug to add this information when the chromebook is released.
Maybe make a template page for new devices?
We could add a field to board_info.txt - Unreleased/Released (date)/No longer for sale. If it's marked as released, we could require documentation.
Sure will add it to the documentation.
Releasing the source code but not giving further details sounds like a lame excuse.
It allows you to release broken, plain wrong and undocumented code that nobody can verify, as you are not able to publicly acknowledge or deny anything.
Giving -1 until it's clear how it was tested and what is actually working.
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 8:
Patch Set 8: Code-Review-1
Patch Set 8:
Patch Set 8:
Please add Documentation as well, that answers the following question: Which flash IC does it use? Where does the flash reside? Can you flash in-circuit? Are there debug headers? Can you provide a picture of the flash IC? What was tested and what works/does not?
Patrick, You might want to add the above list to documentation about what you'd like to see for new mainboards that we can point people to. Obviously we can't give out this information right now, but we could create a bug to add this information when the chromebook is released.
Maybe make a template page for new devices?
We could add a field to board_info.txt - Unreleased/Released (date)/No longer for sale. If it's marked as released, we could require documentation.
Sure will add it to the documentation.
Releasing the source code but not giving further details sounds like a lame excuse.
It allows you to release broken, plain wrong and undocumented code that nobody can verify, as you are not able to publicly acknowledge or deny anything.
Giving -1 until it's clear how it was tested and what is actually working.
Thejaswani, can you include a what you have tested in the description?
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 8:
Patch Set 8:
Patch Set 8: Code-Review-1
Patch Set 8:
Patch Set 8:
Please add Documentation as well, that answers the following question: Which flash IC does it use? Where does the flash reside? Can you flash in-circuit? Are there debug headers? Can you provide a picture of the flash IC? What was tested and what works/does not?
Patrick, You might want to add the above list to documentation about what you'd like to see for new mainboards that we can point people to. Obviously we can't give out this information right now, but we could create a bug to add this information when the chromebook is released.
Maybe make a template page for new devices?
We could add a field to board_info.txt - Unreleased/Released (date)/No longer for sale. If it's marked as released, we could require documentation.
Sure will add it to the documentation.
Releasing the source code but not giving further details sounds like a lame excuse.
It allows you to release broken, plain wrong and undocumented code that nobody can verify, as you are not able to publicly acknowledge or deny anything.
Giving -1 until it's clear how it was tested and what is actually working.
Thejaswani, can you include a what you have tested in the description?
Patrick, frequently when we initially add boards, they don't even *EXIST* yet. I'm going to be pushing a board shortly that is currently just a schematic. How do you propose that we test that? Not everything that we're doing fits in the same model that you're used to.
Why does it matter how this board has been tested when it's just being added and will see continued development for a long period of time? We prefer to develop in upstream coreboot so that everything's in the open, but you have to know that we can't really talk about things until the board is released.
Please just ignore this board from a documentation standpoint until it's actually released. If you have questions about the chipset, I could understand that, but you're asking questions that can't really be answered right now.
Mathew King has uploaded a new patch set (#9) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
mb/google/drallion: Add new mainboard
Drallion is a new mainboard using Intel Comet Lake SOC. As a starting point, I took mainboard/sarien as the reference code and modified WHL to Comet Lake.
BUG=b:138098572 TEST=compiles
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4 --- A src/mainboard/google/drallion/Kconfig A src/mainboard/google/drallion/Kconfig.name A src/mainboard/google/drallion/Makefile.inc A src/mainboard/google/drallion/acpi_tables.c A src/mainboard/google/drallion/board_info.txt A src/mainboard/google/drallion/bootblock.c A src/mainboard/google/drallion/chromeos.c A src/mainboard/google/drallion/chromeos.fmd A src/mainboard/google/drallion/dsdt.asl A src/mainboard/google/drallion/ec.c A src/mainboard/google/drallion/hda_verb.c A src/mainboard/google/drallion/ramstage.c A src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/sku.c A src/mainboard/google/drallion/smihandler.c A src/mainboard/google/drallion/variants/drallion/Makefile.inc A src/mainboard/google/drallion/variants/drallion/devicetree.cb A src/mainboard/google/drallion/variants/drallion/gpio.c A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl A src/mainboard/google/drallion/variants/drallion/include/variant/ec.h A src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h A src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h A src/mainboard/google/drallion/variants/drallion/include/variant/variant.h 24 files changed, 1,817 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34497/9
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 9:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... File src/mainboard/google/drallion/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... PS9, Line 32: CONFIG_EC_GOOGLE_WILCO Nit: I think these could just be changed to '-y' I don't think the board would build without wilco ec being selected. If I'm wrong, please feel free to ignore this.
Or ignore it even if I'm right. It's just a nit.
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... File src/mainboard/google/drallion/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... PS9, Line 62: #if CONFIG(EC_GOOGLE_WILCO) Nit: You're selecting EC_GOOGLE_WILCO in the kconfig. You have calls to various wilco ec functions all over the mainboard. I doubt it would build without the EC_GOOGLE_WILCO enabled, so this seems like a useless #if.
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... File src/mainboard/google/drallion/ramstage.c:
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... PS9, Line 25: #if CONFIG(GENERATE_SMBIOS_TABLES) Is this guard needed? Wouldn't they just not get called?
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... PS9, Line 210: "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" Nit: Maybe wrap this line?
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 9:
Thejaswani, Any thoughts on my comments?
Patrick, I understand that you're not happy with not getting the documentation. Matt added the TEST=compiles line to the commit message. Since the board itself doesn't really exist yet, is this sufficient?
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 9:
Patch Set 9:
Thejaswani, Any thoughts on my comments?
Patrick, I understand that you're not happy with not getting the documentation. Matt added the TEST=compiles line to the commit message. Since the board itself doesn't really exist yet, is this sufficient?
Yes Martin, I am working on your comments, I will test the changes and then update the patch.
Hello Patrick Rudolph, Bernardo Perez Priego, Selma Bensaid, Duncan Laurie, John Zhao, Bora Guvendik, build bot (Jenkins), Patrick Georgi, Pratikkumar V Prajapati, AndreX Andraos, Mathew King, Krzysztof M Sywula, Martin Roth, Chiranjeevi Rapolu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34497
to look at the new patch set (#10).
Change subject: mb/google/drallion: Add new mainboard ......................................................................
mb/google/drallion: Add new mainboard
Drallion is a new mainboard using Intel Comet Lake SOC. As a starting point, I took mainboard/sarien as the reference code and modified WHL to Comet Lake.
BUG=None Test=Needs to be tested
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4 --- A src/mainboard/google/drallion/Kconfig A src/mainboard/google/drallion/Kconfig.name A src/mainboard/google/drallion/Makefile.inc A src/mainboard/google/drallion/acpi_tables.c A src/mainboard/google/drallion/board_info.txt A src/mainboard/google/drallion/bootblock.c A src/mainboard/google/drallion/chromeos.c A src/mainboard/google/drallion/chromeos.fmd A src/mainboard/google/drallion/dsdt.asl A src/mainboard/google/drallion/ec.c A src/mainboard/google/drallion/hda_verb.c A src/mainboard/google/drallion/ramstage.c A src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/sku.c A src/mainboard/google/drallion/smihandler.c A src/mainboard/google/drallion/variants/drallion/Makefile.inc A src/mainboard/google/drallion/variants/drallion/devicetree.cb A src/mainboard/google/drallion/variants/drallion/gpio.c A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl A src/mainboard/google/drallion/variants/drallion/include/variant/ec.h A src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h A src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h A src/mainboard/google/drallion/variants/drallion/include/variant/variant.h 24 files changed, 1,817 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34497/10
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 10:
(4 comments)
Patch Set 9:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... File src/mainboard/google/drallion/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... PS9, Line 32: CONFIG_EC_GOOGLE_WILCO
Nit: I think these could just be changed to '-y' I don't think the board would build without wilco […]
Done
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... File src/mainboard/google/drallion/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... PS9, Line 62: #if CONFIG(EC_GOOGLE_WILCO)
Nit: You're selecting EC_GOOGLE_WILCO in the kconfig. […]
Done
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... File src/mainboard/google/drallion/ramstage.c:
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... PS9, Line 25: #if CONFIG(GENERATE_SMBIOS_TABLES)
Is this guard needed? Wouldn't they just not get called?
Done
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... PS9, Line 210: "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN"
Nit: Maybe wrap this line?
Done! Is this what you ask for?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... File src/mainboard/google/drallion/ramstage.c:
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... PS9, Line 64: static const struct pad_config gpio_unused[] = { I think if we use D3 hot, we can just remove W/A from here.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h:
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... PS9, Line 21: const u32 cim_verb_data[] = { Could you help confirm verb table? I always get audio init timeout in depthcharge... If I want let it beep.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 10:
Patch Set 10:
(1 comment)
I used the Sarien with CML cpu. So the codec should be Sarien's.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 10:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34497/10//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34497/10//COMMIT_MSG@13 PS10, Line 13: BUG=None : Test=Needs to be tested were these not correct in the last patch?
BUG=b:138098572 TEST=compiles
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... PS9, Line 210: "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN"
Done! […]
Sure, that'll work. Thanks much.
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h:
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... PS9, Line 21: const u32 cim_verb_data[] = {
Could you help confirm verb table? I always get audio init timeout in depthcharge... […]
EricR, would you be ok if that was handled in a follow-on patch, or does it need to be done in the initial commit?
Hello Patrick Rudolph, Bernardo Perez Priego, Selma Bensaid, Duncan Laurie, John Zhao, Bora Guvendik, build bot (Jenkins), Patrick Georgi, Pratikkumar V Prajapati, AndreX Andraos, Mathew King, Krzysztof M Sywula, Martin Roth, Chiranjeevi Rapolu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34497
to look at the new patch set (#11).
Change subject: mb/google/drallion: Add new mainboard ......................................................................
mb/google/drallion: Add new mainboard
Drallion is a new mainboard using Intel Comet Lake SOC. As a starting point, I took mainboard/sarien as the reference code and modified WHL to Comet Lake.
BUG=b:138098572 Test=compiles
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4 --- A src/mainboard/google/drallion/Kconfig A src/mainboard/google/drallion/Kconfig.name A src/mainboard/google/drallion/Makefile.inc A src/mainboard/google/drallion/acpi_tables.c A src/mainboard/google/drallion/board_info.txt A src/mainboard/google/drallion/bootblock.c A src/mainboard/google/drallion/chromeos.c A src/mainboard/google/drallion/chromeos.fmd A src/mainboard/google/drallion/dsdt.asl A src/mainboard/google/drallion/ec.c A src/mainboard/google/drallion/hda_verb.c A src/mainboard/google/drallion/ramstage.c A src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/sku.c A src/mainboard/google/drallion/smihandler.c A src/mainboard/google/drallion/variants/drallion/Makefile.inc A src/mainboard/google/drallion/variants/drallion/devicetree.cb A src/mainboard/google/drallion/variants/drallion/gpio.c A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl A src/mainboard/google/drallion/variants/drallion/include/variant/ec.h A src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h A src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h A src/mainboard/google/drallion/variants/drallion/include/variant/variant.h 24 files changed, 1,817 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34497/11
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34497/10//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34497/10//COMMIT_MSG@13 PS10, Line 13: BUG=None : Test=Needs to be tested
were these not correct in the last patch? […]
Agreed! Done.
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... PS9, Line 210: "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN"
Sure, that'll work. Thanks much.
Thank you!
Thejaswani Putta has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... File src/mainboard/google/drallion/ramstage.c:
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... PS9, Line 64: static const struct pad_config gpio_unused[] = {
I think if we use D3 hot, we can just remove W/A from here.
Ack
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h:
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... PS9, Line 21: const u32 cim_verb_data[] = {
EricR, would you be ok if that was handled in a follow-on patch, or does it need to be done in the i […]
Ack
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 11:
Please add the VBT as well.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h:
https://review.coreboot.org/c/coreboot/+/34497/9/src/mainboard/google/dralli... PS9, Line 21: const u32 cim_verb_data[] = {
Ack
I am fine with this, just check. We can fix this after the real board comes out.
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 11: Code-Review+2
Patch Set 11:
Please add the VBT as well.
I will file a bug to have it added to coreboot.
Bernardo Perez Priego has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 11:
Patch Set 11: Code-Review+2
Patch Set 11:
Please add the VBT as well.
I will file a bug to have it added to coreboot.
I will be uploading vbt in drallion overlay.
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
Patch Set 11:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34497/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34497/5//COMMIT_MSG@9 PS5, Line 9: Drallion is a new mainboard using Intel Comet Lake SOC & Wilco EC
Please add a dot at the end of the sentence.
Done
https://review.coreboot.org/c/coreboot/+/34497/10//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34497/10//COMMIT_MSG@13 PS10, Line 13: BUG=None : Test=Needs to be tested
Agreed! Done.
Done
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... File src/mainboard/google/drallion/Kconfig:
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... PS4, Line 27: select MAINBOARD_USES_IFD_GBE_REGION if BOARD_GOOGLE_DRALLION
Arcada uses GBE region. […]
Drallion will not have GbE but the test build based on sarien will so lets leave it for now.
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... File src/mainboard/google/drallion/ramstage.c:
https://review.coreboot.org/c/coreboot/+/34497/4/src/mainboard/google/dralli... PS4, Line 79: /* Disable unused pads for devices with board ID > 2 */ : if (board_id() > 2) : gpio_configure_pads(gpio_unused, ARRAY_SIZE(gpio_unused));
For the EV drallion boards we will be using the Arcada and Sarien boards with its SOC replaced by Co […]
I think that this may not be necessary for the final build, but we can leave it for now with the test units.
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34497 )
Change subject: mb/google/drallion: Add new mainboard ......................................................................
mb/google/drallion: Add new mainboard
Drallion is a new mainboard using Intel Comet Lake SOC. As a starting point, I took mainboard/sarien as the reference code and modified WHL to Comet Lake.
BUG=b:138098572 Test=compiles
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34497 Reviewed-by: Mathew King mathewk@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- A src/mainboard/google/drallion/Kconfig A src/mainboard/google/drallion/Kconfig.name A src/mainboard/google/drallion/Makefile.inc A src/mainboard/google/drallion/acpi_tables.c A src/mainboard/google/drallion/board_info.txt A src/mainboard/google/drallion/bootblock.c A src/mainboard/google/drallion/chromeos.c A src/mainboard/google/drallion/chromeos.fmd A src/mainboard/google/drallion/dsdt.asl A src/mainboard/google/drallion/ec.c A src/mainboard/google/drallion/hda_verb.c A src/mainboard/google/drallion/ramstage.c A src/mainboard/google/drallion/romstage.c A src/mainboard/google/drallion/sku.c A src/mainboard/google/drallion/smihandler.c A src/mainboard/google/drallion/variants/drallion/Makefile.inc A src/mainboard/google/drallion/variants/drallion/devicetree.cb A src/mainboard/google/drallion/variants/drallion/gpio.c A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl A src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl A src/mainboard/google/drallion/variants/drallion/include/variant/ec.h A src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h A src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h A src/mainboard/google/drallion/variants/drallion/include/variant/variant.h 24 files changed, 1,817 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Mathew King: Looks good to me, approved
diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig new file mode 100644 index 0000000..deeca15 --- /dev/null +++ b/src/mainboard/google/drallion/Kconfig @@ -0,0 +1,106 @@ + +config BOARD_GOOGLE_BASEBOARD_DRALLION + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_INTEL_ISH + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EC_GOOGLE_WILCO + select GENERIC_SPD_BIN + select GOOGLE_SMBIOS_MAINBOARD_VERSION + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_I2C_TPM_CR50 + select MAINBOARD_HAS_TPM2 + select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + select TPM2 + select MAINBOARD_USES_IFD_EC_REGION + select MAINBOARD_USES_IFD_GBE_REGION + select USE_SAR + select SAR_ENABLE + +if BOARD_GOOGLE_BASEBOARD_DRALLION + +config CHROMEOS + bool + default y + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_BOOT_LEGACY + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config DRIVER_TPM_I2C_BUS + hex + default 0x4 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 + +config TPM_TIS_ACPI_INTERRUPT + int + default 82 # GPE0_DW2_18 (GPP_D18) + +config POWER_OFF_ON_CR50_UPDATE + bool + default n + +config GBB_HWID + string + depends on CHROMEOS + default "DRALLION TEST 3556" + +config MAINBOARD_DIR + string + default "google/drallion" + +config MAINBOARD_FAMILY + string + default "Google_Drallion" + +config MAINBOARD_PART_NUMBER + string + default "Drallion" + +config MAINBOARD_VENDOR + string + default "Google" + +config MAX_CPUS + int + default 8 + +config UART_FOR_CONSOLE + int + default 2 + +config VARIANT_DIR + string + default "drallion" + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config VBOOT + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + select VBOOT_LID_SWITCH + +endif # BOARD_GOOGLE_BASEBOARD_DRALLION diff --git a/src/mainboard/google/drallion/Kconfig.name b/src/mainboard/google/drallion/Kconfig.name new file mode 100644 index 0000000..bd5d903 --- /dev/null +++ b/src/mainboard/google/drallion/Kconfig.name @@ -0,0 +1,5 @@ +comment "Drallion" + +config BOARD_GOOGLE_DRALLION + bool "-> Drallion" + select BOARD_GOOGLE_BASEBOARD_DRALLION diff --git a/src/mainboard/google/drallion/Makefile.inc b/src/mainboard/google/drallion/Makefile.inc new file mode 100644 index 0000000..c16e7d2 --- /dev/null +++ b/src/mainboard/google/drallion/Makefile.inc @@ -0,0 +1,38 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2018 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c + +ramstage-y += ramstage.c +ramstage-y += sku.c + +romstage-y += romstage.c + +smm-y += smihandler.c + +bootblock-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c + +bootblock-y += ec.c +ramstage-y += ec.c +romstage-y += ec.c +verstage-y += ec.c + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/drallion/acpi_tables.c b/src/mainboard/google/drallion/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/drallion/acpi_tables.c diff --git a/src/mainboard/google/drallion/board_info.txt b/src/mainboard/google/drallion/board_info.txt new file mode 100644 index 0000000..dfc194b --- /dev/null +++ b/src/mainboard/google/drallion/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Drallion +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/drallion/bootblock.c b/src/mainboard/google/drallion/bootblock.c new file mode 100644 index 0000000..bee9b1a --- /dev/null +++ b/src/mainboard/google/drallion/bootblock.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <ec/google/wilco/bootblock.h> +#include <soc/gpio.h> +#include <variant/gpio.h> + +static void early_config_gpio(void) +{ + const struct pad_config *early_gpio_table; + size_t num_gpios = 0; + + early_gpio_table = variant_early_gpio_table(&num_gpios); + gpio_configure_pads(early_gpio_table, num_gpios); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); + wilco_ec_early_init(); +} diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c new file mode 100644 index 0000000..7aaf401 --- /dev/null +++ b/src/mainboard/google/drallion/chromeos.c @@ -0,0 +1,127 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <variant/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <security/tpm/tss.h> +#include <device/device.h> +#include <intelblocks/pmclib.h> +#include <soc/pmc.h> +#include <soc/pci_devs.h> + +enum rec_mode_state { + REC_MODE_UNINITIALIZED, + REC_MODE_NOT_REQUESTED, + REC_MODE_REQUESTED, +}; + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {GPIO_PCH_WP, ACTIVE_HIGH, get_write_protect_state(), + "write protect"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +static int cros_get_gpio_value(int type) +{ + const struct cros_gpio *cros_gpios; + size_t i, num_gpios = 0; + + cros_gpios = variant_cros_gpios(&num_gpios); + + for (i = 0; i < num_gpios; i++) { + const struct cros_gpio *gpio = &cros_gpios[i]; + if (gpio->type == type) { + int state = gpio_get(gpio->gpio_num); + if (gpio->polarity == CROS_GPIO_ACTIVE_LOW) + return !state; + else + return state; + } + } + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *cros_gpios; + size_t num_gpios = 0; + + cros_gpios = variant_cros_gpios(&num_gpios); + + chromeos_acpi_gpio_generate(cros_gpios, num_gpios); +} + +int get_write_protect_state(void) +{ + return cros_get_gpio_value(CROS_GPIO_WP); +} + +int get_recovery_mode_switch(void) +{ + static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED; + enum rec_mode_state state = REC_MODE_NOT_REQUESTED; + uint8_t cr50_state = 0; + + /* Check cached state, since TPM will only tell us the first time */ + if (saved_rec_mode != REC_MODE_UNINITIALIZED) + return saved_rec_mode == REC_MODE_REQUESTED; + + /* + * Read one-time recovery request from cr50 in verstage only since + * the TPM driver won't be set up in time for other stages like romstage + * and the value from the TPM would be wrong anyway since the verstage + * read would have cleared the value on the TPM. + * + * The TPM recovery request is passed between stages through the + * vboot_get_shared_data or cbmem depending on stage. + */ + if (ENV_VERSTAGE && + tlcl_cr50_get_recovery_button(&cr50_state) == TPM_SUCCESS && + cr50_state) + state = REC_MODE_REQUESTED; + + /* Read state from the GPIO controlled by servo. */ + if (cros_get_gpio_value(CROS_GPIO_REC)) + state = REC_MODE_REQUESTED; + + /* Store the state in case this is called again in verstage. */ + saved_rec_mode = state; + + return state == REC_MODE_REQUESTED; +} + +int get_lid_switch(void) +{ + return 1; +} + +void mainboard_prepare_cr50_reset(void) +{ +#if ENV_RAMSTAGE + /* Ensure system powers up after CR50 reset */ + pmc_set_afterg3(MAINBOARD_POWER_STATE_ON); +#endif +} diff --git a/src/mainboard/google/drallion/chromeos.fmd b/src/mainboard/google/drallion/chromeos.fmd new file mode 100644 index 0000000..ece0eda --- /dev/null +++ b/src/mainboard/google/drallion/chromeos.fmd @@ -0,0 +1,49 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x400000 { + SI_DESC@0x0 0x1000 + SI_EC@0x1000 0x100000 + SI_GBE(PRESERVE)@0x101000 0x2000 + SI_ME@0x103000 0x2f9000 + SI_PDR(PRESERVE)@0x3fc000 0x4000 + } + SI_BIOS@0x400000 0x1c00000 { + RW_DIAG@0x0 0x12d0000 { + RW_LEGACY(CBFS)@0x0 0x12c0000 + DIAG_NVRAM@0x12c0000 0x10000 + } + RW_SECTION_A@0x12d0000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x26ffc0 + RW_FWID_A@0x27ffc0 0x40 + } + RW_SECTION_B@0x1550000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x26ffc0 + RW_FWID_B@0x27ffc0 0x40 + } + RW_MISC@0x17d0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x28000 0x2000 + RW_NVRAM(PRESERVE)@0x2a000 0x6000 + } + WP_RO@0x1800000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x3f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x300000 + } + } + } +} diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl new file mode 100644 index 0000000..2568800 --- /dev/null +++ b/src/mainboard/google/drallion/dsdt.asl @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/ec.h> + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + /* Some generic macros */ + #include <soc/intel/cannonlake/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/cannonlake/acpi/globalnvs.asl> + + /* CPU */ + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + } + /* Per board variant mainboard hooks. */ + #include <variant/acpi/mainboard.asl> + } + +#if CONFIG(CHROMEOS) + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + /* VPD support */ + #include <vendorcode/google/chromeos/acpi/vpd.asl> + /* MAC address passthru */ + #include <vendorcode/google/chromeos/acpi/amac.asl> +#endif + + /* Chipset specific sleep states */ + #include <soc/intel/cannonlake/acpi/sleepstates.asl> + + /* Low power idle table */ + #include <soc/intel/cannonlake/acpi/lpit.asl> + + /* Chrome OS Embedded Controller */ + Scope (_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/wilco/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/wilco/acpi/ec.asl> + } + + /* Dynamic Platform Thermal Framework */ + Scope (_SB) + { + /* Per board variant specific definitions. */ + #include <variant/acpi/dptf.asl> + /* Include soc specific DPTF changes */ + #include <soc/intel/cannonlake/acpi/dptf.asl> + /* Include common dptf ASL files */ + #include <soc/intel/common/acpi/dptf/dptf.asl> + } +} diff --git a/src/mainboard/google/drallion/ec.c b/src/mainboard/google/drallion/ec.c new file mode 100644 index 0000000..fd8e84f --- /dev/null +++ b/src/mainboard/google/drallion/ec.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <ec/google/wilco/commands.h> +#include <variant/ec.h> + +void mainboard_post(uint8_t value) +{ + wilco_ec_save_post_code(value); +} diff --git a/src/mainboard/google/drallion/hda_verb.c b/src/mainboard/google/drallion/hda_verb.c new file mode 100644 index 0000000..9ab4778 --- /dev/null +++ b/src/mainboard/google/drallion/hda_verb.c @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "variant/hda_verb.h" diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c new file mode 100644 index 0000000..b3bf102 --- /dev/null +++ b/src/mainboard/google/drallion/ramstage.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <boardid.h> +#include <drivers/vpd/vpd.h> +#include <smbios.h> +#include <soc/gpio.h> +#include <soc/ramstage.h> +#include <variant/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#define VPD_KEY_SYSTEM_SERIAL "serial_number" +#define VPD_KEY_MAINBOARD_SERIAL "mlb_serial_number" +#define VPD_SERIAL_LEN 64 + +const char *smbios_system_serial_number(void) +{ + static char serial[VPD_SERIAL_LEN]; + if (vpd_gets(VPD_KEY_SYSTEM_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) + return serial; + return ""; +} + +const char *smbios_mainboard_serial_number(void) +{ + static char serial[VPD_SERIAL_LEN]; + if (vpd_gets(VPD_KEY_MAINBOARD_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) + return serial; + return ""; +} + +/* mainboard silk screen shows DIMM-A and DIMM-B */ +void smbios_fill_dimm_locator(const struct dimm_info *dimm, + struct smbios_type17 *t) +{ + switch (dimm->channel_num) { + case 0: + t->device_locator = smbios_add_string(t->eos, "DIMM-A"); + break; + case 1: + t->device_locator = smbios_add_string(t->eos, "DIMM-B"); + break; + default: + t->device_locator = smbios_add_string(t->eos, "UNKNOWN"); + break; + } +} + +static const struct pad_config gpio_unused[] = { +/* SUSWARN# */ PAD_NC(GPP_A13, NONE), +/* SUSACK# */ PAD_NC(GPP_A15, NONE), +/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), +/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), +}; + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + const struct pad_config *gpio_table; + size_t num_gpios; + + gpio_table = variant_gpio_table(&num_gpios); + cnl_configure_pads(gpio_table, num_gpios); + + /* Disable unused pads for devices with board ID > 2 */ + if (board_id() > 2) + gpio_configure_pads(gpio_unused, ARRAY_SIZE(gpio_unused)); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c new file mode 100644 index 0000000..20eee7f --- /dev/null +++ b/src/mainboard/google/drallion/romstage.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/google/wilco/romstage.h> +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> + +static const struct cnl_mb_cfg memcfg = { + /* Access memory info through SMBUS. */ + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa0}, + }, + .spd[1] = {.read_type = NOT_EXISTING}, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa4}, + }, + .spd[3] = {.read_type = NOT_EXISTING}, + + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = {0, 1, 4, 5, 2, 3, 6, 7}, + .dqs_map[DDR_CH1] = {0, 1, 4, 5, 2, 3, 6, 7}, + + /* Baseboard uses 121, 81 and 100 rcomp resistors */ + .rcomp_resistor = {121, 81, 100}, + + /* + * Baseboard Rcomp target values. + */ + .rcomp_targets = {100, 40, 20, 20, 26}, + + /* Disable Early Command Training */ + .ect = 0, + + /* Base on board design */ + .vref_ca_config = 2, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + wilco_ec_romstage_init(); + + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +} diff --git a/src/mainboard/google/drallion/sku.c b/src/mainboard/google/drallion/sku.c new file mode 100644 index 0000000..d0b48f0 --- /dev/null +++ b/src/mainboard/google/drallion/sku.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/google/wilco/commands.h> +#include <smbios.h> +#include <variant/variant.h> + +uint32_t sku_id(void) +{ + if (wilco_ec_signed_fw()) + return VARIANT_SKU_ID_SIGNED_EC; + else + return VARIANT_SKU_ID; +} + +const char *smbios_system_sku(void) +{ + if (wilco_ec_signed_fw()) + return VARIANT_SKU_NAME_SIGNED_EC; + else + return VARIANT_SKU_NAME; +} diff --git a/src/mainboard/google/drallion/smihandler.c b/src/mainboard/google/drallion/smihandler.c new file mode 100644 index 0000000..0efcaa9 --- /dev/null +++ b/src/mainboard/google/drallion/smihandler.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/smm.h> +#include <ec/google/wilco/smm.h> +#include <soc/smm.h> +#include <variant/ec.h> + +void mainboard_smi_espi_handler(void) +{ + wilco_ec_smi_espi(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + wilco_ec_smi_sleep(slp_typ); +} + +int mainboard_smi_apmc(u8 apmc) +{ + wilco_ec_smi_apmc(apmc); + return 0; +} diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc new file mode 100644 index 0000000..2bf028e --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2018 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += gpio.c +ramstage-y += gpio.c +romstage-y += gpio.c +verstage-y += gpio.c diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb new file mode 100644 index 0000000..575b610 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -0,0 +1,393 @@ +chip soc/intel/cannonlake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "PMC_GPP_A" + register "gpe0_dw1" = "PMC_GPP_C" + register "gpe0_dw2" = "PMC_GPP_D" + + # EC host command ranges + register "gen1_dec" = "0x00040931" # 0x930-0x937 + register "gen2_dec" = "0x00040941" # 0x940-0x947 + register "gen3_dec" = "0x000c0951" # 0x950-0x95f + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "HeciEnabled" = "0" + register "SataSalpSupport" = "1" + register "SataMode" = "Sata_AHCI" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[2]" = "1" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "4" # 4s + register "PchPmSlpSusMinAssert" = "4" # 4s + register "PchPmSlpAMinAssert" = "4" # 2s + register "PchUnlockGpioPads" = "1" + + register "speed_shift_enable" = "1" + register "psys_pmax" = "140" + register "s0ix_enable" = "1" + register "dptf_enable" = "1" + register "dmipwroptimize" = "1" + register "satapwroptimize" = "1" + register "tdp_pl1_override" = "25" + register "tdp_pl2_override" = "51" + register "Device4Enable" = "1" + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" + register "SlowSlewRateForSa" = "0" + register "SlowSlewRateForFivr" = "2" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + # Enable DDC for DDI port B + register "DdiPortBDdc" = "1" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 6A | 70A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #+----------------+-------+-------+-------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(6), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(70), + .voltage_limit = 1520, + .ac_loadline = 180, + .dc_loadline = 180, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Intel Common SoC Config + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port + register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port + register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port + register "usb2_ports[3]" = "USB2_PORT_EMPTY" + register "usb2_ports[4]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera + register "usb2_ports[6]" = "{ + .enable = 1, \ + .ocpin = OC_SKIP, \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_28P15MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ + }" # WWAN + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Left Type-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN + register "usb3_ports[4]" = "USB3_PORT_EMPTY" + register "usb3_ports[5]" = "USB3_PORT_EMPTY" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| I2C0 | Touchscreen | + #| I2C1 | Touchpad | + #| I2C4 | H1 TPM | + #+-------------------+---------------------------+ + + register "tcc_offset" = "1" + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 52, + .fall_time_ns = 110, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 52, + .fall_time_ns = 110, + .data_hold_time_ns = 330, + }, + .i2c[4] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 36, + .fall_time_ns = 99, + }, + }" + + # PCIe port 10 for M.2 2230 WLAN + register "PcieRpEnable[9]" = "1" + register "PcieClkSrcUsage[2]" = "9" + register "PcieClkSrcClkReq[2]" = "2" + + # PCIe port 11 for card reader + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + register "PcieClkSrcUsage[1]" = "10" + register "PcieClkSrcClkReq[1]" = "1" + + # PCIe port 13 for M.2 2280 SSD + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[4]" = "12" + register "PcieClkSrcClkReq[4]" = "4" + + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | + MISCCFG_GPRTCDLCGEN | + MISCCFG_GSXSLCGEN | + MISCCFG_GPDPCGEN | + MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 on # Integrated Sensor Hub + chip drivers/intel/ish + register "firmware_name" = ""drallion_ish.bin"" + device generic 0 on end + end + end + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""USH"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.7 on end + end + chip drivers/usb/acpi + register "desc" = ""Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.8 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H15)" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.3 on end + end + end + end + end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + chip drivers/intel/wifi + register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + end + device pci 14.5 off end # SDCard + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM48E2"" + register "generic.desc" = ""Wacom Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.reset_delay_ms" = "20" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "generic.enable_delay_ms" = "55" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0A on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "probed" = "1" + device i2c 2c on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)" + device i2c 50 on end + end + end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 (USB) + device pci 1c.1 off end # PCI Express Port 2 (USB) + device pci 1c.2 off end # PCI Express Port 3 (USB) + device pci 1c.3 off end # PCI Express Port 4 (USB) + device pci 1c.4 off end # PCI Express Port 5 (USB) + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + end # PCI Express Port 9 + device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.2 on end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + end # PCI Express Port 13 (x4) + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on + chip ec/google/wilco + device pnp 0c09.0 on end + end + end # LPC/eSPI + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c new file mode 100644 index 0000000..ff0240c --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -0,0 +1,279 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <variant/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_NC(GPP_A0, NONE), +/* ESPI_IO0 */ +/* ESPI_IO1 */ +/* ESPI_IO2 */ +/* ESPI_IO3 */ +/* ESPI_CS# */ +/* SERIRQ */ +/* PIRQA# */ PAD_NC(GPP_A7, NONE), +/* CLKRUN# */ PAD_NC(GPP_A8, NONE), +/* ESPI_CLK */ +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), +/* PME# */ PAD_NC(GPP_A11, NONE), + /* ISH_LID_CL#_TAB */ +/* ISH_GP6 */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF2), +/* SUSWARN# */ PAD_NC(GPP_A13, NONE), +/* ESPI_RESET# */ +/* SUSACK# */ PAD_NC(GPP_A15, NONE), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), + /* ISH_ACC1_INT# */ +/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* ISH_ACC2_INT# */ +/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), + /* ISH_NB_MODE */ +/* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), + /* ISH_LID_CL#_NB */ +/* ISH_GP5 */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + +/* CORE_VID0 */ +/* CORE_VID1 */ +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ +/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ + /* LAN_CLKREQ_CPU_N */ +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* CARD_CLKREQ_CPU_N */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* WLAN_CLKREQ_CPU_N */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* WWAN_CLKREQ_CPU_N */ +/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* SSD_CKLREQ_CPU_N */ +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* TBT_CLKREQ_CPU_N (nostuff) */ +/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), /* PRIM_CORE_OPT_DIS (nostuff) */ +/* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */ +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* RTC_DET# */ +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ +/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), +/* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), + +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */ +/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */ +/* SMBALERT# */ PAD_NC(GPP_C2, DN_20K), +/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SMBCLK */ +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_SMBDATA */ +/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K), +/* SM1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */ +/* SM1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */ +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), /* PCH_TBT_PERST# (nostuff) */ +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */ +/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */ +/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, + EDGE_SINGLE), /* SIO_EXT_WAKE# */ +/* UART1_TXD */ PAD_NC(GPP_C13, NONE), +/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */ +/* UART1_CTS# */ PAD_NC(GPP_C15, NONE), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */ +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */ +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ +/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), +/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, + LEVEL, NONE), /* TS_INT# */ + +/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), +/* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* ISH_LAN# */ +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TBT_FORCE_PWR (nostuff) */ + /* ISH_I2C0_ACC_SDA */ +/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* ISH_I2C0_ACC_SCL */ +/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), /* IR_CAM_DET# */ +/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), +/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */ +/* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), + /* ISH_CPU_UART0_RX */ +/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), + /* ISH_CPU_UART0_TX */ +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), +/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */ +/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ +/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), +/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), +/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 1, DEEP), /* WWAN_BB_RST# */ +/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* WWAN_GPIO_PERST# */ +/* I2S_MCLK */ PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP, + EDGE_SINGLE), /* WWAN_GPIO_WAKE# */ + +/* SATAXPCIE0 */ PAD_NC(GPP_E0, NONE), + /* M3042_PCIE#_SATA */ +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* M2880_PCIE_SATA# */ +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), +/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */ +/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */ +/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */ +/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ +/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ +/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ +/* USB2_OC2# */ PAD_NC(GPP_E11, NONE), +/* USB2_OC3# */ PAD_NC(GPP_E12, NONE), +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */ +/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_SCL_CPU */ +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_SDA_CPU */ +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), + +/* CNV_PA_BLANKING */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_COEX3 */ +/* GPP_F1 */ PAD_NC(GPP_F1, NONE), +/* GPP_F2 */ PAD_NC(GPP_F2, NONE), +/* GPP_F3 */ PAD_NC(GPP_F3, NONE), +/* CNV_BRI_DT */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), +/* CNV_BRI_RSP */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), +/* CNV_RGI_DT */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), +/* CNV_RGI_RSP */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), +/* CNV_MFUART2_RXD */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* CNV_COEX2 */ +/* CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* CNV_COEX1 */ +/* GPP_F10 */ PAD_NC(GPP_F10, NONE), +/* EMMC_CMD */ PAD_NC(GPP_F11, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F19, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F20, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_RESET# */ PAD_NC(GPP_F22, NONE), +/* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE), + +/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */ +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */ +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */ +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */ +/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */ +/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */ +/* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, DEEP), /* SPK_DET# */ + +/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), +/* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */ +/* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */ +/* I2S2_RXD */ PAD_NC(GPP_H3, NONE), +/* I2C2_SDA */ PAD_NC(GPP_H4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_H5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_H6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_H7, NONE), +/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ +/* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */ +/* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */ +/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), +/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ +/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), +/* DPPF_CTRLDATA */ PAD_NC(GPP_H17, NONE), +/* CPU_C10_GATE# */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10_GATE# */ +/* TIMESYNC0 */ PAD_NC(GPP_H19, NONE), +/* IMGCLKOUT1 */ PAD_NC(GPP_H20, NONE), +/* GPP_H21 */ PAD_NC(GPP_H21, NONE), +/* GPP_H22 */ PAD_NC(GPP_H22, NONE), /* RTD3_CIO_PWR_EN (nostuff) */ +/* GPP_H23 */ PAD_NC(GPP_H23, NONE), + +/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */ +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */ +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */ +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */ +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */ +/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */ +/* GPD7 */ PAD_NC(GPD7, NONE), /* TBT_RTD3_WAKE# (nostuff) */ +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK */ +/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */ +/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */ +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */ +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ +/* SSD RESET pin will stay low first */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ +/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ +/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ +/* RESET# need to stay low before FULL_CARD_POWER_OFF assert */ +/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ +/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ +/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ +/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..73e1dec --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 98 +#define DPTF_CPU_CRITICAL 108 + +/* Skin Sensor for CPU VR temperature monitor */ +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "Skin" +#define DPTF_TSR0_PASSIVE 55 +#define DPTF_TSR0_CRITICAL 100 + +/* Memory Sensor for DDR temperature monitor */ +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "DDR" +#define DPTF_TSR1_PASSIVE 53 +#define DPTF_TSR1_CRITICAL 100 + +/* M.2 Sensor for Ambient temperature monitor */ +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "Ambient" +#define DPTF_TSR2_PASSIVE 38 +#define DPTF_TSR2_CRITICAL 93 + +#undef DPTF_ENABLE_FAN_CONTROL +#undef DPTF_ENABLE_CHARGER + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 500, 100, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Skin (TSR0) */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 400, 40, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on DDR (TSR1) */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR1, 300, 50, 2, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR2) */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR2, 1000, 100, 1, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 21000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 51000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..41121d2 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CAM_EN GPP_B11 /* Active low */ +#define TS_PD GPP_E7 + +/* Method called from LPIT prior to enter s0ix state */ +Method (MS0X, 1) +{ + If (Arg0) { + /* Turn off camera power */ + _SB.PCI0.STXS (CAM_EN) + } Else { + /* Turn on camera power */ + _SB.PCI0.CTXS (CAM_EN) + } +} + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) +{ + _SB.PCI0.LPCB.EC0.PTS (Arg0) + + /* Clear touch screen pd pin to avoid leakage */ + _SB.PCI0.CTXS (TS_PD) +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) +{ + _SB.PCI0.LPCB.EC0.WAK (Arg0) +} diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h new file mode 100644 index 0000000..01a17b5 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* EC wake pin */ +#define EC_WAKE_PIN GPE0_DW1_12 + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* Enable PS/2 keyboard */ +#define SIO_EC_ENABLE_PS2K + +/* Enable DPTF */ +#define EC_ENABLE_DPTF + +#endif diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h new file mode 100644 index 0000000..f7e0403 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* Flash Write Protect */ +#define GPIO_PCH_WP GPP_E15 + +/* Recovery mode */ +#define GPIO_REC_MODE GPP_E8 + +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +struct cros_gpio; +const struct cros_gpio *variant_cros_gpios(size_t *num); + +#endif diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h b/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h new file mode 100644 index 0000000..10fbaf1 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h @@ -0,0 +1,209 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_HDA_VERB_H +#define MAINBOARD_HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0295, // Codec Vendor / Device ID: Realtek ALC3204 + 0xffffffff, // Subsystem ID + 0x0000002b, // Number of jacks (NID entries) + + /* Rest Codec First */ + AZALIA_RESET(0x1), + /* NID 0x01, HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0x0, 0x102808b6), + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(0x0, 0x12, 0xb7a60130), + AZALIA_PIN_CFG(0x0, 0x13, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x16, 0x40000000), + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x19, 0x04a11030), + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1d, 0x40c00001), + AZALIA_PIN_CFG(0x0, 0x1e, 0x421212f2), + AZALIA_PIN_CFG(0x0, 0x21, 0x04211020), + + /* D reset */ + 0x0205003C, + 0x0204F254, + 0x0205003C, + 0x0204F214, + /* JD1 - 2port JD mode */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + /* Set TRS type-1 */ + 0x02050045, + 0x02045289, + 0x02050049, + 0x02040049, + /* Set TRS type-2 + Set UAJ Line2 vref(ALC3254) */ + 0x0205004A, + 0x0204A830, + 0x02050063, + 0x0204CF00, + /* NID 0x20 set class-D to 2W@4ohm (+12dB gain) + * + Set sine tone gain(0x34) */ + 0x02050038, + 0x02043909, + 0x05C50000, + 0x05C43482, + /* AGC-1 Disable + (Front Gain=0dB ) */ + 0x05D50006, + 0x05D44C50, + 0x05D50002, + 0x05D44004, + /* AGC-2 (Backt Boost Gain= -0.375dB ,Limiter = -3dB) */ + 0x05D50003, + 0x05D45E5E, + 0x05D50001, + 0x05D4D788, + /* AGC-3 + AGC Enable */ + 0x05D50009, + 0x05D451FF, + 0x05D50006, + 0x05D44E50, + /* HP-JD Enable +Nokia type */ + 0x0205004A, + 0x02042010, + 0x02050008, + 0x02046A0C, + /* EAPD set to verb-control + I2C Un-use+ DVDD3.3V */ + 0x02050010, + 0x02040020, + 0x02050034, + 0x0204A23D, + /* Class D silent detection Enable -84dB threshold */ + 0x02050030, + 0x02049000, + 0x02050037, + 0x0204FE15, + /* Disable EQ + set 250Hz 3rd High Pass filter */ + 0x05350000, + 0x0534203A, + 0x05350000, + 0x0534203A, + /* Left Channel-1 */ + 0x0535001d, + 0x05340800, + 0x0535001e, + 0x05340800, + /* Left Channel-2 */ + 0x05350003, + 0x05341EF8, + 0x05350004, + 0x05340000, + /* Left Channel-3 */ + 0x05350005, + 0x053403EE, + 0x05350006, + 0x0534FA60, + /* Left Channel-4 */ + 0x05350007, + 0x05341E10, + 0x05350008, + 0x05347B86, + /* Left Channel-5 */ + 0x05350009, + 0x053401F7, + 0x0535000A, + 0x05349FB6, + /* Left Channel-6 */ + 0x0535000B, + 0x05341C00, + 0x0535000C, + 0x05340000, + /* Left Channel-7 */ + 0x0535000D, + 0x05340200, + 0x0535000E, + 0x05340000, + /* Right Channel-1 */ + 0x05450000, + 0x05442000, + 0x0545001d, + 0x05440800, + /* Right Channel-2 */ + 0x0545001e, + 0x05440800, + 0x05450003, + 0x05441EF8, + /* Right Channel-3 */ + 0x05450004, + 0x05440000, + 0x05450005, + 0x054403EE, + /* Right Channel-4 */ + 0x05450006, + 0x0544FA60, + 0x05450007, + 0x05441E10, + /* Right Channel-5 */ + 0x05450008, + 0x05447B86, + 0x05450009, + 0x054401F7, + /* Right Channel-6 */ + 0x0545000A, + 0x05449FB6, + 0x0545000B, + 0x05441C00, + /* Right Channel-7 */ + 0x0545000C, + 0x05440000, + 0x0545000D, + 0x05440200, + /* Right Channel-8 + EQ Update & Enable */ + 0x0545000E, + 0x05440000, + 0x05350000, + 0x0534E03A, + /* Enable all Microphone */ + 0x0205000D, + 0x0204A023, + 0x0205000D, + 0x0204A023, + /* Enable Internal Speaker (NID14) */ + 0x0205000F, + 0x02040000, + 0x0205000F, + 0x02040000, +}; + +const u32 pc_beep_verbs[] = { + /* PCBeep pass through to NID14 for ePSA test-1 */ + 0x02050036, + 0x020477D7, + 0x0143B000, + 0x01470740, + /* PCBeep pass through to NID14 for ePSA test-2 */ + 0x01470C02, + 0x01470C02, + 0x01470C02, + 0x01470C02, +}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h new file mode 100644 index 0000000..d878623 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* Need to update for Drallion with right SKU IDs*/ +#define VARIANT_SKU_ID 2 +#define VARIANT_SKU_NAME "sku2" +#define VARIANT_SKU_ID_SIGNED_EC 4 +#define VARIANT_SKU_NAME_SIGNED_EC "sku4" + +#endif