coreboot-gerrit March 2025

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[L] Change in coreboot[main]: Docs: Updated 25.03 release notes
by Matt DeVillier (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Angel Pons, Felix Singer, Jason Glenesk, Martin L Roth. Matt DeVillier has posted comments on this change by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/87042?usp=email ) Change subject: Docs: Updated 25.03 release notes ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87042?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a3894fd617e95b8014c3cf1afe6472994e3fb16 Gerrit-Change-Number: 87042 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Mar 2025 21:22:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: Docs: Updated 25.03 release notes
by Martin L Roth (Code Review) 28 Mar '25

28 Mar '25

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87042?usp=email ) Change subject: Docs: Updated 25.03 release notes ...................................................................... Docs: Updated 25.03 release notes These are the release notes for the 25.03 release. We will update again after the release is done with the final statistics and information. Change-Id: I4a3894fd617e95b8014c3cf1afe6472994e3fb16 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- M Documentation/releases/coreboot-25.03-relnotes.md 1 file changed, 285 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/87042/1 diff --git a/Documentation/releases/coreboot-25.03-relnotes.md b/Documentation/releases/coreboot-25.03-relnotes.md index 4b579fe..125437b 100644 --- a/Documentation/releases/coreboot-25.03-relnotes.md +++ b/Documentation/releases/coreboot-25.03-relnotes.md @@ -1,37 +1,172 @@ Upcoming release - coreboot 25.03 ======================================================================== -The 25.03 release is scheduled for the end of March, 2025 +The coreboot project is pleased to announce the release of coreboot +25.03, marking another milestone in our ongoing work to delivering +open-source firmware. This release brings important improvements to +display handling, USB debugging capabilities, and CPU topology +management, along with various other enhancements that further improve +the reliability and performance of coreboot across supported platforms. - -Update this document with changes that should be in the release notes. - -* Please use Markdown. -* See the past few release notes for the general format. -* The chip and board additions and removals will be updated right - before the release, so those do not need to be added. -* Note that all changes before the release are done are marked upcoming. - A final version of the notes are done after the release. +We extend our sincere thanks to all contributors who have made this +release possible. Your expertise and collaborative efforts continue to +propel the coreboot project forward. As always, we value the +participation of everyone in the community, from long-time developers to +those new to the project. The next coreboot release, 25.06, is scheduled +for the end of June 2025. Significant or interesting changes ---------------------------------- -* Add changes that need a full description here +### drivers/intel/fsp2_0: Enable panel-orientation aware bitmap rotation -* This section should have full descriptions and can or should have - a link to the referenced commits. +Implement logo bitmap rotation within fsp_convert_bmp_to_gop_blt() to +support devices with portrait-oriented displays. The rotation is driven +by the panel framebuffer orientation, allowing the logo to be displayed +correctly regardless of physical panel orientation. + +This resolves issues where the logo was displayed incorrectly on +portrait-oriented displays. + +Additionally, discard the display orientation change if the LID is +closed aka built-in display is not active. This will ensure that display +orientation is proper when extended display is attached w/o any display +rotation. + + +### util/find_usbdebug: Fix lsusb -t parsing for usbutils v016 and newer + +Commit e24294ff9ade ("lsusb -t: print ports and buses and devices with +same width") [1] in the usbutils repository changed the format of the +lsusb -t output, breaking the find_usbdebug.sh script. This commit is +present in usbutils version 016 and later. + +Use the output of lsusb -V to set the parsing patterns based on the +version in order to maintain compatibility with older versions of +usbutils. A simple integer comparison of the version number is used for +this, which will not work with versions older than v001 as those use a +0.nn version number format. However, since v001 was released in late +2010, it is probably safe to assume that no one will be using a version +of usbutils older than that. Usbutils v016 was released in late 2023 so +there could still conceivably be systems using older versions, such as +Ubuntu 22.04 LTS which is on v014. + +[1] https://github.com/gregkh/usbutils/commit/e24294ff9ade6dafcd1909763e888d97b… + + +### cpu/x86/topology: Fix FSP-S crash caused by shared core ID + +This resolves a crash issue observed on Meteor Lake and introduced by +commit 70bdd2e1fad9fe89835aab240ed4b41a02f15078 ("cpu/x86/topology: +Simplify CPU topology initialization"). This commit simplifies the code +and provides more detailed CPU topology information by generalizing the +use of the Extended Topology Enumeration Leaves 0x1f. As a result, the +coreboot APIC core_id field does not provide the fully detailed path +information. + +It turns out that the topology core identifier is used by the coreboot +MP service mp_get_processor_info() implementation. But the MP Service +EFI_CPU_PHYSICAL_LOCATION data structure only captures information about +the package, core, and thread. The core identifier returned to the MP +service caller must incorporate the full hierarchical path (die group, +die, module, tile, module and core). + +This commit adds a new field to the cpu topology structure to represent +the core ID within the package. + +For reference, here is that signature of the crash: + + LAPIC 0x40 in X2APIC mode. + CPU Index 2 - APIC 64 Unexpected Exception:13 @ 10:69f3d1e4 - Halting + Code: 0 eflags: 00010046 cr2: 00000000 + eax: 00000001 ebx: 69f313e8 ecx: 0000004e edx: 00000000 + edi: 69f38018 esi: 00000029 ebp: 69aeee0c esp: 69aeedc0 + [...] + +The crash occurred when FSP attempted to lock the Protected +Processor Inventory Number Enable Control MSR (IA32_PPIN_CTL +0x4e). + + 69f3d1d3: 8b 43 f4 mov -0xc(%ebx),%eax + 69f3d1d6: 89 4d c4 mov %ecx,-0x3c(%ebp) + 69f3d1d9: 89 45 dc mov %eax,-0x24(%ebp) + 69f3d1dc: 8b 55 c4 mov -0x3c(%ebp),%edx + 69f3d1df: 8b 45 c0 mov -0x40(%ebp),%eax + 69f3d1e2: 8b 4d dc mov -0x24(%ebp),%ecx + 69f3d1e5: 0f 30 wrmsr + 69f3d1e7: e9 ee fd ff ff jmp 0xfffffe39 + +FSP experiences issues due to attempting to lock the same register +multiple times for a single core. This is caused by an inconsistency in +the processor information data structure, where multiple cores share the +same identifier. This is not permitted and triggers a General Protection +Fault Exception. + + +### {drivers, lib}: Move low-battery user notification logic outside FSP + +This patch refactors low-battery user notification logic (Kconfig, APIs +to check if low-battery rendering is required, low-battery shutdown is +required) outside FSP driver code to ensure in future non-FSP platforms +might still be able to leverage this feature/logics to render the +low-battery indicator icon during boot. + +Specifically, it: + +- Moves Kconfig options related to low-battery notifications from + drivers/intel/fsp to lib/ +- Relocates the low-battery check and shutdown APIs drivers/intel/fsp + to bootsplash.h +* Adjusts the vendor driver to utilize the new APIs for low-battery + rendering decisions. +* Drop the unwanted header file "fsp/api.h" from bmp_logo.c + +This change avoids tight coupling of low-battery functionality to FSP, +promoting code reusability across platforms. + + +### soc/intel/cannonlake: Use common ACPI code for SRAM and HECI + +Use the newly-created ACPI devices in common/acpi, and adjust the SoC +ACPI name for the CSE/HECI device to match. + + +### lib: Introduce early power off support Kconfig option + +This commit introduces the `HAVE_EARLY_POWEROFF_SUPPORT` Kconfig option +and the `platform_do_early_poweroff()` API. + +The Kconfig option enables platform-specific early power off support, +which is often required on Intel platforms. The corresponding API allows +platforms to implement the necessary hardware operations for early power +off, typically before memory initialization. Additional coreboot changes --------------------------- -The following are changes across a number of patches, or changes worth -noting, but not needing a full description. - -* Changes that only need a line or two of description go here. +* Numerous changes to Haswell open source ram init +* Numerous additions to intelp2m tool +* Enhanced power management and thermal control across multiple platforms +* Improved USB Type-C and Thunderbolt support +* Added support for early power off and low battery detection +* Enhanced display and graphics support across multiple platforms +* Improved memory initialization and training +* Added support for various new memory parts and configurations +* Enhanced ACPI support and device handling +* Improved security features and TPM support +* Enhanced EC (Embedded Controller) support across platforms +* Added support for various new touch panels and input devices +* Refactored and improved code organization across multiple subsystems +* Enhanced build system and toolchain support +* Improved documentation and testing infrastructure +* Added support for RISC-V architecture improvements +* Enhanced debugging and logging capabilities +* Improved error handling and recovery mechanisms +* Added 7500 MT/s support for DDR5 @@ -40,12 +175,17 @@ ### Toolchain updates +* Update CMake from 3.30.2 to 3.31.3 +* Update ACPICA from 20230628 to 20241212 ### Git submodule pointers - -### External payloads +* arm-trusted-firmware: Update from commit id 15e5c6c91d to e5a1f4abee (608 commits) +* blobs: Update from commit id 14f8fcc1b4 to a0726508b8 (10 commits) +* fsp: Update from commit id 851f7105d8 to 86c9111639 (30 commits) +* intel-microcode: Update from commit id 8ac9378a84 to 8a62de41c0 (1 commits) +* vboot: Update from commit id f1f70f46dc to 3f94e2c7ed (49 commits) @@ -53,35 +193,143 @@ ---------------- ### Added mainboards: -* To be filled in immediately before the release by the release team - - -### Removed Mainboards -* To be filled in immediately before the release by the release team - +* AMD Crater for Renoir SoC +* ASROCK Z87 Extreme3 +* ASROCK Z87 Extreme4 +* ASROCK Z87M Extreme4 +* ASROCK Z87 Pro4 +* ASUS P8H67-I DELUXE +* Google Dirks +* Google Guren +* Google Meliks +* Google Moxie +* Google Ocelot +* Google Pujjoniru +* Google Quandiso2 +* Google Wyrdeer +* HP Pro 3400 Series +* Intel Ptlrvp +* Lenovo ThinkCentre M900 +* NovaCustom V540TU (14") +* NovaCustom V560TU (16") +* StarLabs StarLite Mk V Smart Battery (N200) +* StarLabs StarBook Mk VII (165H) +* StarLabs StarBook Mk VII (N200) ### Updated SoCs -* To be filled in immediately before the release by the release team - - - -Plans to move platform support to a branch ------------------------------------------- -* To be filled in immediately before the release by the release team +* Added src/soc/xilinx/zynq7000 Statistics from the 24.12 to the 25.03 release --------------------------------------------- -* To be filled in immediately before the release by the release team +---------------------------------------------- + +* Total Commits: 992 +* Average Commits per day: 10.09 +* Total lines added: 87471 +* Average lines added per commit: 88.18 +* Number of patches adding more than 100 lines: 95 +* Average lines added per small commit: 40.50 +* Total lines removed: 22845 +* Average lines removed per commit: 23.03 +* Total difference between added and removed: 64626 +* Total authors: 129 +* New authors: 28 Significant Known and Open Issues --------------------------------- -Issues from the coreboot bugtracker: <https://ticket.coreboot.org/> -* To be filled in immediately before the release by the release team +### coreboot-wide or architecture-wide issues + ++-----+-----------------------------------------------------------------+ +| # | Subject | ++=====+=================================================================+ +| 519 | make gconfig - could not find glade file | ++-----+-----------------------------------------------------------------+ +| 518 | make xconfig - g++: fatal error: no input files | ++-----+-----------------------------------------------------------------+ + + +### Payload-specific issues + ++-----+-----------------------------------------------------------------+ +| # | Subject | ++=====+=================================================================+ +| 577 | SeaBIOS/EDK2 Windows 10 BSOD "UNSUPPORTED PROCESSOR" | ++-----+-----------------------------------------------------------------+ +| 552 | X201 not booting with edk2 payload | ++-----+-----------------------------------------------------------------+ +| 549 | SeaBIOS Windows 10/11 BSOD "ACPI BIOS ERROR" (Thinkpad W530) | ++-----+-----------------------------------------------------------------+ +| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled | ++-----+-----------------------------------------------------------------+ +| 496 | Missing malloc check in libpayload | ++-----+-----------------------------------------------------------------+ +| 484 | No USB keyboard support with secondary payloads | ++-----+-----------------------------------------------------------------+ +| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT | ++-----+-----------------------------------------------------------------+ + + +### Platform-specific issues + ++-----+-----------------------------------------------------------------+ +| # | Subject | ++=====+=================================================================+ +| 579 | MAC address set by coreboot to RTL8111F does not persist | ++-----+-----------------------------------------------------------------+ +| 565 | Wifi card not recognized on Lenovo M700 tiny | ++-----+-----------------------------------------------------------------+ +| 563 | tty doesn't show on external display using edk2 on W530 | ++-----+-----------------------------------------------------------------+ +| 548 | Lenovo X201 Fails To Recognize Upgraded WiFi Card | ++-----+-----------------------------------------------------------------+ +| 538 | x230: Dock Causes Internal Display to "Permanently" Malfunction | ++-----+-----------------------------------------------------------------+ +| 535 | T420: Power light stays off after reboot | ++-----+-----------------------------------------------------------------+ +| 528 | Building qemu-i440fx with CONFIG_CBFS_VERIFICATION fails | ++-----+-----------------------------------------------------------------+ +| 524 | X2APIC Options cause Linux to crash on emulation/qemu-i440fx | ++-----+-----------------------------------------------------------------+ +| 517 | lenovo x230 boot stuck with connected external monitor | ++-----+-----------------------------------------------------------------+ +| 509 | SD Card hotplug not working on Apollo Lake | ++-----+-----------------------------------------------------------------+ +| 506 | APL/GML don't boot OS when CPU microcode included "from tree" | ++-----+-----------------------------------------------------------------+ +| 505 | Harcuvar CRB - 15 of 16 cores present in the operating system | ++-----+-----------------------------------------------------------------+ +| 499 | T440p - EDK2 fails with RESOURCE_ALLOCATION_TOP_DOWN enabled | ++-----+-----------------------------------------------------------------+ +| 495 | Stoney Chromebooks not booting PSPSecureOS | ++-----+-----------------------------------------------------------------+ +| 478 | X200 booting Linux takes a long time with TSC | ++-----+-----------------------------------------------------------------+ +| 474 | X200s crashes after graphic init with 8GB RAM | ++-----+-----------------------------------------------------------------+ +| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb | ++-----+-----------------------------------------------------------------+ +| 453 | Intel HDMI / DP Audio not present in Windows after libgfxinit | ++-----+-----------------------------------------------------------------+ +| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking | ++-----+-----------------------------------------------------------------+ +| 448 | Thinkpad T440P ACPI Battery Value Issues | ++-----+-----------------------------------------------------------------+ +| 446 | Optiplex 9010 No Post | ++-----+-----------------------------------------------------------------+ +| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz) | ++-----+-----------------------------------------------------------------+ +| 427 | x200: Two battery charging issues | ++-----+-----------------------------------------------------------------+ +| 412 | x230 reboots on suspend | ++-----+-----------------------------------------------------------------+ +| 393 | T500 restarts rather than waking up from suspend | ++-----+-----------------------------------------------------------------+ +| 350 | I225 PCIe device not detected on Harcuvar | ++-----+-----------------------------------------------------------------+ @@ -94,3 +342,4 @@ * Documentation: <https://doc.coreboot.org> * Issue tracker: <https://ticket.coreboot.org/projects/coreboot> * Donations: <https://coreboot.org/donate.html> + -- To view, visit https://review.coreboot.org/c/coreboot/+/87042?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a3894fd617e95b8014c3cf1afe6472994e3fb16 Gerrit-Change-Number: 87042 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com>

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[S] Change in coreboot[main]: docs/security/vboot: Update supported board list
by Felix Singer (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Matt DeVillier. Felix Singer has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/87029?usp=email ) Change subject: docs/security/vboot: Update supported board list ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87029?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I079e02d24671a76520587b03a9d83fdc9f33e55b Gerrit-Change-Number: 87029 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Mar 2025 21:17:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: docs/security/vboot: Update supported board list
by Martin L Roth (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Matt DeVillier. Martin L Roth has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/87029?usp=email ) Change subject: docs/security/vboot: Update supported board list ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87029?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I079e02d24671a76520587b03a9d83fdc9f33e55b Gerrit-Change-Number: 87029 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Mar 2025 20:30:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: include/endian.h: Add 'always aligned access' support
by Matt DeVillier (Code Review) 28 Mar '25

28 Mar '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86609?usp=email ) Change subject: include/endian.h: Add 'always aligned access' support ...................................................................... include/endian.h: Add 'always aligned access' support RISC-V doesn't support unaligned access, so check for that before decoding and encoding. It is not perfectly performant, but still much better then invoking the misaligned exception handler every time there is a misaligned access. We can't modify our whole codebase to always do aligned access, because it is neither feasible in long term nor is fair to add that performance penalty onto other architectures that do support unaligned access. So this is the next best thing. On architectures that do support unaligned access the compiler will just optimize the RISCV_ENV part out and should result in the exact same binary. tested: identical binary on QEMU-aarch64 and QEMU-q35. Change-Id: I4dfccfdc2b302dd30b7ce5a29520c86add13169d Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86609 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/include/endian.h 1 file changed, 24 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/include/endian.h b/src/include/endian.h index 552ce002..5cdcb2d 100644 --- a/src/include/endian.h +++ b/src/include/endian.h @@ -5,6 +5,7 @@ #include <arch/byteorder.h> #include <stdint.h> +#include <string.h> #include <swab.h> #if defined(__LITTLE_ENDIAN) @@ -67,12 +68,22 @@ #define clrsetbits_le16(addr, clear, set) __clrsetbits(le, 16, addr, clear, set) #define clrsetbits_be16(addr, clear, set) __clrsetbits(be, 16, addr, clear, set) -/* be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions. */ +/* + * be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions. + * RISC-V doesn't support misaligned access so decode it byte by byte. + */ #define DEFINE_ENDIAN_DEC(endian, width) \ static inline uint##width##_t endian##width##dec(const void *p) \ { \ - return endian##width##_to_cpu(*(uint##width##_t *)p); \ + if (ENV_RISCV) { \ + uint##width##_t val; \ + memcpy(&val, p, sizeof(val)); \ + return endian##width##_to_cpu(val); \ + } else { \ + return endian##width##_to_cpu(*(uint##width##_t *)p); \ + } \ } + DEFINE_ENDIAN_DEC(be, 16) DEFINE_ENDIAN_DEC(be, 32) DEFINE_ENDIAN_DEC(be, 64) @@ -80,12 +91,21 @@ DEFINE_ENDIAN_DEC(le, 32) DEFINE_ENDIAN_DEC(le, 64) -/* be16enc/be32enc/be64enc/le16enc/le32enc/le64enc family of functions. */ +/* + * be16enc/be32enc/be64enc/le16enc/le32enc/le64enc family of functions. + * RISC-V doesn't support misaligned access so encode it byte by byte. + */ #define DEFINE_ENDIAN_ENC(endian, width) \ static inline void endian##width##enc(void *p, uint##width##_t u) \ { \ - *(uint##width##_t *)p = cpu_to_##endian##width(u); \ + if (ENV_RISCV) { \ + uint##width##_t val = cpu_to_##endian##width(u); \ + memcpy(p, &val, sizeof(val)); \ + } else { \ + *(uint##width##_t *)p = cpu_to_##endian##width(u); \ + } \ } + DEFINE_ENDIAN_ENC(be, 16) DEFINE_ENDIAN_ENC(be, 32) DEFINE_ENDIAN_ENC(be, 64) -- To view, visit https://review.coreboot.org/c/coreboot/+/86609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4dfccfdc2b302dd30b7ce5a29520c86add13169d Gerrit-Change-Number: 86609 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/emulation/qemu-aarch64/include: Update ECAM comment
by Matt DeVillier (Code Review) 28 Mar '25

28 Mar '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86872?usp=email ) Change subject: mb/emulation/qemu-aarch64/include: Update ECAM comment ...................................................................... mb/emulation/qemu-aarch64/include: Update ECAM comment Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I5864cb742ba8e7be54f67c234766cd8a5272f8e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86872 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h M src/mainboard/emulation/qemu-aarch64/mainboard.c 2 files changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h index 70acac8..f3ca0e1 100644 --- a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h +++ b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h @@ -41,7 +41,8 @@ * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last * index of base_memmap). */ -#define VIRT_PCIE_ECAM_BASE 0x4010000000 /* The one in lower memory does not seem to work */ +#define VIRT_PCIE_LOW_ECAM_BASE 0x3f000000 /* only used if highmem-ecam=off (QEMU cmdline) */ +#define VIRT_PCIE_HIGH_ECAM_BASE 0x4010000000 /* only used if highmem-ecam=on (default) */ #define VIRT_PCIE_ECAM_SIZE (256 * MiB) -#define VIRT_PCIE_HIGH_MMIO_BASE 0x8000000000ULL +#define VIRT_PCIE_HIGH_MMIO_BASE 0x8000000000ULL #define VIRT_PCIE_HIGH_MMIO_LIMIT 0xffffffffffULL diff --git a/src/mainboard/emulation/qemu-aarch64/mainboard.c b/src/mainboard/emulation/qemu-aarch64/mainboard.c index 2701072..ac6b46d 100644 --- a/src/mainboard/emulation/qemu-aarch64/mainboard.c +++ b/src/mainboard/emulation/qemu-aarch64/mainboard.c @@ -41,7 +41,7 @@ res->limit = VIRT_PCIE_HIGH_MMIO_LIMIT; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - mmio_range(dev, index++, VIRT_PCIE_ECAM_BASE, VIRT_PCIE_ECAM_SIZE); + mmio_range(dev, index++, VIRT_PCIE_HIGH_ECAM_BASE, VIRT_PCIE_ECAM_SIZE); ram_from_to(dev, index++, (uintptr_t)_dram, cbmem_top()); } -- To view, visit https://review.coreboot.org/c/coreboot/+/86872?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5864cb742ba8e7be54f67c234766cd8a5272f8e2 Gerrit-Change-Number: 86872 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/fatcat/var/francka: Add audio_disable_pins
by Matt DeVillier (Code Review) 28 Mar '25

28 Mar '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87023?usp=email ) Change subject: mb/google/fatcat/var/francka: Add audio_disable_pins ...................................................................... mb/google/fatcat/var/francka: Add audio_disable_pins disable audio-related pins when the CBI FW_Config is not defined. BUG=b:392007428 TEST=emerge-fatcat coreboot Signed-off-by: Mac Chiang <mac.chiang(a)intel.com> Change-Id: I278106df53635adf2bb9f2eb787231724ad4b372 Reviewed-on: https://review.coreboot.org/c/coreboot/+/87023 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/fatcat/variants/francka/fw_config.c 1 file changed, 21 insertions(+), 1 deletion(-) Approvals: Jayvik Desai: Looks good to me, approved Pranava Y N: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/fatcat/variants/francka/fw_config.c b/src/mainboard/google/fatcat/variants/francka/fw_config.c index b087e27..91aa200 100644 --- a/src/mainboard/google/fatcat/variants/francka/fw_config.c +++ b/src/mainboard/google/fatcat/variants/francka/fw_config.c @@ -43,6 +43,23 @@ PAD_NC(GPP_S05, NONE), }; +static const struct pad_config audio_disable_pads[] = { + PAD_NC(GPP_D09, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_S00, NONE), + PAD_NC(GPP_S01, NONE), + PAD_NC(GPP_S02, NONE), + PAD_NC(GPP_S03, NONE), + PAD_NC(GPP_S04, NONE), + PAD_NC(GPP_S05, NONE), + PAD_NC(GPP_S06, NONE), + PAD_NC(GPP_S07, NONE), +}; + /* * WWAN: power sequence requires three stages: * step 1: 3.3V power, FCP# (Full Card Power), RST#, and PERST# off @@ -123,8 +140,11 @@ return; } - if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256M_CG_HDA))) + if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256M_CG_HDA))) { GPIO_PADBASED_OVERRIDE(padbased_table, hda_enable_pads); + } else { + GPIO_PADBASED_OVERRIDE(padbased_table, audio_disable_pads); + } if (fw_config_probe(FW_CONFIG(WWAN, WWAN_PRESENT))) { GPIO_PADBASED_OVERRIDE(padbased_table, wwan_pwr_seq3_pads); -- To view, visit https://review.coreboot.org/c/coreboot/+/87023?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I278106df53635adf2bb9f2eb787231724ad4b372 Gerrit-Change-Number: 87023 Gerrit-PatchSet: 2 Gerrit-Owner: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: Makefile: Add build/3rdparty as an exception for project_filelist.txt
by Matt DeVillier (Code Review) 28 Mar '25

28 Mar '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86868?usp=email ) Change subject: Makefile: Add build/3rdparty as an exception for project_filelist.txt ...................................................................... Makefile: Add build/3rdparty as an exception for project_filelist.txt The ctags tool (called by ctags-project target) currently complains about not finding certain files: ``` ctags: Warning: cannot open input file "bl31/aarch64/bl31_entrypoint.S" : No such file or directory ctags: Warning: cannot open input file "bl31/aarch64/crash_reporting.S" : No such file or directory ctags: Warning: cannot open input file "bl31/aarch64/runtime_exceptions.S" : No such file or directory ctags: Warning: cannot open input file "bl31/bl31.ld.S" : No such file or directory ctags: Warning: cannot open input file "bl31/bl31_context_mgmt.c" : No such file or directory ctags: Warning: cannot open input file "bl31/bl31_main.c" : No such file or directory ctags: Warning: cannot open input file "bl31/bl31_traps.c" : No such file or directory ctags: Warning: cannot open input file "bl31/interrupt_mgmt.c" : No such file or directory ctags: Warning: cannot open input file "common/aarch64/debug.S" : No such file or directory ctags: Warning: cannot open input file "common/bl_common.c" : No such file or directory ctags: Warning: cannot open input file "common/fdt_fixup.c" : No such file or directory ... ``` The project_filelist.txt generation includes the compiler generated "*.d" files, except for files found in build/util. Most file paths in these "*.d" files are file paths relative to the root directory of coreboot. Some projects though are compiled separately from coreboot (e.g. payload, vboot, util). Some of these (e.g. util, vboot) are also put into the build directory of coreboot and relative file paths are relative to these projects instead of coreboot. This has the uncanning side effect that the ctags Makefile target can't find these files, since they are not relative to the coreboot root directory. This patch excludes the build/3rdparty directory from those files, since they contain 'separately' compiled projects like 3rdparty/arm-trusted-firmware. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I18d0377e327530d9ef9382c324a305d156c5c681 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86868 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M Makefile 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/Makefile b/Makefile index 49c19cb..24b7c96 100644 --- a/Makefile +++ b/Makefile @@ -473,7 +473,7 @@ echo "*** Error: Project must be built before generating file list ***"; \ exit 1; \ fi - find $(obj) -path "$(obj)/util" -prune -o -path "$(obj)/external" -prune -o -name "*.d" -exec cat {} \; | \ + find $(obj) -path "$(obj)/util" -prune -o -path "$(obj)/external" -prune -o -path "$(obj)/3rdparty" -prune -o -name "*.d" -exec cat {} \; | \ sed "s|$(top)/||" | sed 's/[:\\]/ /g' | sed 's/ /\n/g' | sort | uniq | \ grep -v '\.o$$' > $(obj)/project_filelist.txt -- To view, visit https://review.coreboot.org/c/coreboot/+/86868?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18d0377e327530d9ef9382c324a305d156c5c681 Gerrit-Change-Number: 86868 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/starlabs/starbook/mtl: Don't configure GPIOs to IOSTANDBY_IGNORE
by Matt DeVillier (Code Review) 28 Mar '25

28 Mar '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87013?usp=email ) Change subject: mb/starlabs/starbook/mtl: Don't configure GPIOs to IOSTANDBY_IGNORE ...................................................................... mb/starlabs/starbook/mtl: Don't configure GPIOs to IOSTANDBY_IGNORE This is just simply incorrect, as these signals are used to pull various devices into low power states during S3. Change-Id: Ic2950cc43fd17dda4205964c851b09cfd86d90d9 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87013 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/mtl/gpio.c 1 file changed, 8 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c index 8619f24..d1b915a 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c @@ -29,17 +29,17 @@ * End: GPP_V22 */ /* V00: PM_BATLOW_N */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V00, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), /* V01: CHG_ACOK */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V01, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), /* V02: PCIE_WAKE_LAN */ PAD_NC(GPP_V02, NONE), /* V03: EC_PWRBTN_N */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V03, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1), /* V04: PM_SLP_S3_N */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V04, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), /* V05: SLP S4# */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V05, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), /* V06: GPD_6_SLP_A_N */ PAD_NC(GPP_V06, NONE), /* V07: */ @@ -97,9 +97,9 @@ * WEAK INTERNAL PD 20K */ PAD_CFG_GPO(GPP_C05, 0, PLTRST), /* C06: SML1_CLK_USBC_PD_N */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C06, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1), /* C07: SML1_DATA_USBC_PD_N */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C07, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1), /* C08: SML1ALERT */ PAD_CFG_NF(GPP_C08, NONE, DEEP, NF1), /* C09: */ @@ -182,7 +182,7 @@ /* A20: M.2_CPU_SSD_RESET_N */ PAD_CFG_GPO(GPP_A20, 1, PLTRST), /* A21: I2C_PMC_PD_INT_N */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* A22: */ PAD_NC(GPP_A22, NONE), /* A23: */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2950cc43fd17dda4205964c851b09cfd86d90d9 Gerrit-Change-Number: 87013 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Set PsysPmax to auto
by Matt DeVillier (Code Review) 28 Mar '25

28 Mar '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87006?usp=email ) Change subject: mb/starlabs/starbook/mtl: Set PsysPmax to auto ...................................................................... mb/starlabs/starbook/mtl: Set PsysPmax to auto Set PsysPmax to 0, which is auto instead of the FSP default which is 21.5W (0xac). Change-Id: Ia2503077067fa719a09f9877d7fe0bedf2a662f1 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87006 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/mtl/romstage.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c index acd384e..6f553a2 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c @@ -37,4 +37,5 @@ mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 8); mupd->FspmConfig.PchHdaSubSystemIds = 0x70381e50; + mupd->FspmConfig.PsysPmax = 0; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/87006?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2503077067fa719a09f9877d7fe0bedf2a662f1 Gerrit-Change-Number: 87006 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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