coreboot-gerrit March 2025

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[S] Change in coreboot[main]: drivers/intel/usb4: Add mainboard function to get EC port
by Derek Huang (Code Review) 01 Mar '25

01 Mar '25

Derek Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86673?usp=email ) Change subject: drivers/intel/usb4: Add mainboard function to get EC port ...................................................................... drivers/intel/usb4: Add mainboard function to get EC port This patch adds mainboard override function which allows for custome port mapping between CPU physical port and EC port to accommodate the non-sequential mapping. Mainboard code must implement this function if the CPU physical port to EC port mapping is not sequential. BUG=b:399032094 TEST=build and verify TCSS port and EC port mapping Change-Id: Ibaad2a95d8624564ae012d23e8a7f19f6701db2c Signed-off-by: Derek Huang <derekhuang(a)google.com> --- M src/drivers/intel/usb4/retimer/retimer.h M src/soc/intel/meteorlake/retimer.c 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/86673/1 diff --git a/src/drivers/intel/usb4/retimer/retimer.h b/src/drivers/intel/usb4/retimer/retimer.h index 228f29b..7f811b1 100644 --- a/src/drivers/intel/usb4/retimer/retimer.h +++ b/src/drivers/intel/usb4/retimer/retimer.h @@ -51,4 +51,16 @@ */ int retimer_get_index_for_typec(uint8_t typec_port); +/* + * This function maps CPU physical ports to EC logical ports. + * Mainboard designs may not have a sequential mapping between CPU + * physical ports and EC ports. For example, a board might enable TCSS + * ports 1 and 2, which map to EC ports 1 and 0, respectively. + * This function allows for custom port mapping to accommodate + * these non-sequential designs. Mainboard code must implement this + * function if the CPU physical port to EC port mapping is not + * sequential. + */ +int mainboard_retimer_get_index_for_typec(uint8_t typec_port); + #endif /* _DRIVERS_INTEL_USB4_RETIMER_H_ */ diff --git a/src/soc/intel/meteorlake/retimer.c b/src/soc/intel/meteorlake/retimer.c index a559cfc..7f708d0 100644 --- a/src/soc/intel/meteorlake/retimer.c +++ b/src/soc/intel/meteorlake/retimer.c @@ -6,10 +6,23 @@ #include <intelblocks/tcss.h> #include <static.h> +__weak int mainboard_retimer_get_index_for_typec(uint8_t typec_port) +{ + return -1; +} + int retimer_get_index_for_typec(uint8_t typec_port) { int ec_port = 0; + ec_port = mainboard_retimer_get_index_for_typec(typec_port); + if (ec_port >= 0) { + printk(BIOS_INFO, "USB Type-C %d mapped to EC port %d\n", typec_port, + ec_port); + return ec_port; + } else + ec_port = 0; + const struct device *tcss_port_arr[] = { DEV_PTR(tcss_usb3_port0), DEV_PTR(tcss_usb3_port1), -- To view, visit https://review.coreboot.org/c/coreboot/+/86673?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaad2a95d8624564ae012d23e8a7f19f6701db2c Gerrit-Change-Number: 86673 Gerrit-PatchSet: 1 Gerrit-Owner: Derek Huang <derekhuang(a)google.com>

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coreboot-gerrit March 2025