coreboot-gerrit March 2025

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[S] Change in coreboot[main]: drivers/efi/capsules.c: fix recording capsule size
by Matt DeVillier (Code Review) 01 Mar '25

01 Mar '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84542?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: drivers/efi/capsules.c: fix recording capsule size ...................................................................... drivers/efi/capsules.c: fix recording capsule size As mentioned in comments on CB:83422, size of the current data block (which is … [View More]also the last block of a capsule) was incorrectly used in place of the capsule size: - when publishing a capsule in CBMEM (this worked in practice because CapsuleApp.efi allocates a continuous physical memory) - when aligning target address (which could move output pointer past previously allocated buffer by up to 7 bytes per capsule block) Change-Id: I97a528e2611fcd711c555d0f01e9aadcd2031217 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84542 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/efi/capsules.c 1 file changed, 8 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/drivers/efi/capsules.c b/src/drivers/efi/capsules.c index 38178c6..e8078bb 100644 --- a/src/drivers/efi/capsules.c +++ b/src/drivers/efi/capsules.c @@ -596,6 +596,7 @@ { struct block_descr block = block_chain; uint8_t *capsule_start = NULL; + uint32_t capsule_size = 0; uint32_t size_left = 0; /* No safety checks in this function, as all of them were done earlier. */ @@ -610,8 +611,10 @@ if (size_left == 0) { const EFI_CAPSULE_HEADER *capsule_hdr = map_range(block.addr, sizeof(*capsule_hdr)); - size_left = capsule_hdr->CapsuleImageSize; + capsule_size = capsule_hdr->CapsuleImageSize; capsule_start = target; + + size_left = capsule_size; } uint64_t addr = block.addr; @@ -641,13 +644,14 @@ } uefi_capsules[uefi_capsule_count].base = (uintptr_t)capsule_start; - uefi_capsules[uefi_capsule_count].len = block.len; + uefi_capsules[uefi_capsule_count].len = capsule_size; uefi_capsule_count++; /* This is to align start of the next capsule (assumes that initial value of target was suitably aligned). */ - if (!IS_ALIGNED(block.len, CAPSULE_ALIGNMENT)) - target += ALIGN_UP(block.len, CAPSULE_ALIGNMENT) - block.len; + if (!IS_ALIGNED(capsule_size, CAPSULE_ALIGNMENT)) + target += ALIGN_UP(capsule_size, CAPSULE_ALIGNMENT) - + capsule_size; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/84542?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I97a528e2611fcd711c555d0f01e9aadcd2031217 Gerrit-Change-Number: 84542 Gerrit-PatchSet: 8 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> [View Less]

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[S] Change in coreboot[main]: soc/amd/glinda/cpu: Update smbios parameters
by Matt DeVillier (Code Review) 01 Mar '25

01 Mar '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85637?usp=email ) Change subject: soc/amd/glinda/cpu: Update smbios parameters ...................................................................... soc/amd/glinda/cpu: Update smbios parameters Update smbios parameters for cache type, operation mode & error correction type. source: UEFI reference BIOS Change-Id: If8eaa54c9a0086f4d397a7ddb01009acfd3f1aee Signed-off-by: Naresh Solanki <naresh.solanki(… [View More]

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[XS] Change in coreboot[main]: soc/amd/cpu: smbios: Set external clock to 100 MHz
by Matt DeVillier (Code Review) 01 Mar '25

01 Mar '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85636?usp=email ) Change subject: soc/amd/cpu: smbios: Set external clock to 100 MHz ...................................................................... soc/amd/cpu: smbios: Set external clock to 100 MHz Set external clock to 100MHz. source: PPR #57254 Change-Id: I99f73695019612d58b0c78c6985370d23c78b729 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> Reviewed-on: https://review.… [View More]

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[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Correct GPP_D21 configuration
by Matt DeVillier (Code Review) 01 Mar '25

01 Mar '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86654?usp=email ) Change subject: mb/starlabs/starbook/mtl: Correct GPP_D21 configuration ...................................................................... mb/starlabs/starbook/mtl: Correct GPP_D21 configuration This GPIO is used for clock request 5, which is NF2. Change-Id: Ic5712090339a39a269aa1aefca9f54da11cb6528 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.… [View More]

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[S] Change in coreboot[main]: Kconfig: Update prompt and help text for CBFS_SIZE
by Matt DeVillier (Code Review) 01 Mar '25

01 Mar '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86571?usp=email ) Change subject: Kconfig: Update prompt and help text for CBFS_SIZE ...................................................................... Kconfig: Update prompt and help text for CBFS_SIZE Kconfig item CBFS_SIZE is actually indicating the host firmware size, a.k.a. coreboot owned flash region size, covering CBFS, FMAP, console, MRC cache, VPD, etc. Revise the prompt and help documentation … [View More]to reflect recent usage updates. Change-Id: I762042fae6357ee368b22a47b8e1168902041675 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86571 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/Kconfig 1 file changed, 10 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, approved diff --git a/src/Kconfig b/src/Kconfig index e4c8467..58c2e07 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -634,18 +634,19 @@ When an fmd is specified, it overrides the default format. config CBFS_SIZE - hex "Size of CBFS filesystem in ROM" + hex "Size of coreboot owned area in ROM" depends on FMDFILE = "" # Default value set at the end of the file help - This is the part of the ROM actually managed by CBFS, located at the - end of the ROM (passed through cbfstool -o) on x86 and at the start - of the ROM (passed through cbfstool -s) everywhere else. It defaults - to span the whole ROM on all but Intel systems that use an Intel Firmware - Descriptor. It can be overridden to make coreboot live alongside other - components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE - binaries. This symbol should only be used to generate a default FMAP and - is unused when a non-default fmd file is provided via CONFIG_FMDFILE. + This is the part of ROM (Read-Only Memory) actually managed by coreboot, + located at the end of the ROM on x86 systems and at the start of the ROM + everywhere else. It defaults to span the whole ROM on all systems except for + Intel systems that use an Intel Flash Descriptor. It can be overridden to + make coreboot live alongside other vendor blobs like Intel's IFD (Intel + Flash Descriptor), ME (Management Engine), and TXE (Trusted Execution + Engine) binaries. This symbol is only used to generate a default FMAP + (Flash Memory Map) and is unused when a .fmd file is provided + via CONFIG_FMDFILE. endmenu -- To view, visit https://review.coreboot.org/c/coreboot/+/86571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I762042fae6357ee368b22a47b8e1168902041675 Gerrit-Change-Number: 86571 Gerrit-PatchSet: 11 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com [View Less]

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[S] Change in coreboot[main]: mb/starlabs/starbook/mtl: Don't configure MUX pins
by Matt DeVillier (Code Review) 01 Mar '25

01 Mar '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86651?usp=email ) Change subject: mb/starlabs/starbook/mtl: Don't configure MUX pins ...................................................................... mb/starlabs/starbook/mtl: Don't configure MUX pins These were incorrectly copied from Alder Lake so remove them as they are not correct nor needed. Change-Id: I70708212c4652ed77c875242340c30edf5b935a1 Signed-off-by: Sean Rhodes <sean(a)starlabs.… [View More]systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86651 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk D src/mainboard/starlabs/starbook/variants/mtl/ramstage.c 2 files changed, 0 insertions(+), 15 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk b/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk index 9abc069..2a505c3 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk +++ b/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk @@ -7,4 +7,3 @@ ramstage-y += devtree.c ramstage-y += gpio.c ramstage-y += hda_verb.c -ramstage-y += ramstage.c diff --git a/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c b/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c deleted file mode 100644 index c01c4dd1..0000000 --- a/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <option.h> -#include <soc/ramstage.h> - -void mainboard_silicon_init_params(FSP_S_CONFIG *supd) -{ - /* - * FSP defaults to pins that are used for LPC; given that - * coreboot only supports eSPI, set these pins accordingly. - */ - supd->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 - supd->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 -} -- To view, visit https://review.coreboot.org/c/coreboot/+/86651?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70708212c4652ed77c875242340c30edf5b935a1 Gerrit-Change-Number: 86651 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> [View Less]

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[XS] Change in coreboot[main]: mb/google/brya/lisbon: Enable RTD3 for SSD
by Matt DeVillier (Code Review) 01 Mar '25

01 Mar '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86645?usp=email ) Change subject: mb/google/brya/lisbon: Enable RTD3 for SSD ...................................................................... mb/google/brya/lisbon: Enable RTD3 for SSD Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. BUG=b:391612392 TEST=Run suspend_stress_test … [View More]on lisbon and verify that the device suspends to S0ix. Change-Id: I124b63061650c85ed84324f3e1558a583a1875e0 Signed-off-by: Pranava Y N <pranavayn(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86645 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/lisbon/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/lisbon/overridetree.cb b/src/mainboard/google/brya/variants/lisbon/overridetree.cb index 4c3ffff..6c3eaf9 100644 --- a/src/mainboard/google/brya/variants/lisbon/overridetree.cb +++ b/src/mainboard/google/brya/variants/lisbon/overridetree.cb @@ -149,6 +149,13 @@ .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end probe STORAGE STORAGE_NVME end #NVMe device ref tbt_pcie_rp0 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/86645?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I124b63061650c85ed84324f3e1558a583a1875e0 Gerrit-Change-Number: 86645 Gerrit-PatchSet: 2 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> [View Less]

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[XS] Change in coreboot[main]: mb/google/brya/bujia: Enable RTD3 for SSD
by Matt DeVillier (Code Review) 01 Mar '25

01 Mar '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86644?usp=email ) Change subject: mb/google/brya/bujia: Enable RTD3 for SSD ...................................................................... mb/google/brya/bujia: Enable RTD3 for SSD Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. BUG=b:391612392 TEST=Run suspend_stress_test on … [View More]Bujia and verify that the device suspends to S0ix. Change-Id: Idee14e7d4df0a9cf8b06b33a52016c1b9228e459 Signed-off-by: Pranava Y N <pranavayn(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86644 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/bujia/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/bujia/overridetree.cb b/src/mainboard/google/brya/variants/bujia/overridetree.cb index 6db60ac..370c052 100644 --- a/src/mainboard/google/brya/variants/bujia/overridetree.cb +++ b/src/mainboard/google/brya/variants/bujia/overridetree.cb @@ -119,6 +119,13 @@ .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end end #NVME device ref tbt_pcie_rp0 off end device ref tbt_pcie_rp1 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/86644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idee14e7d4df0a9cf8b06b33a52016c1b9228e459 Gerrit-Change-Number: 86644 Gerrit-PatchSet: 2 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> [View Less]

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[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Don't reconfigure GPIOs in ramstage
by Matt DeVillier (Code Review) 01 Mar '25

01 Mar '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86650?usp=email ) Change subject: mb/starlabs/starbook/mtl: Don't reconfigure GPIOs in ramstage ...................................................................... mb/starlabs/starbook/mtl: Don't reconfigure GPIOs in ramstage GPP_H08 and GPP_H09 are configured in the bootblock, so remove the configuration in ramstage to allow the serial output in ramstage. Change-Id: … [View More]

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Don't generate a TME on S3 exit
by Matt DeVillier (Code Review) 01 Mar '25

01 Mar '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86625?usp=email ) Change subject: soc/intel/meteorlake: Don't generate a TME on S3 exit ...................................................................... soc/intel/meteorlake: Don't generate a TME on S3 exit Generate a new TME key will cause S3 exit to fail, so don't do it. Change-Id: Ie19cb7f11ad633405a9fc3c1faf1c3cc53113f51 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https:… [View More]//review.coreboot.org/c/coreboot/+/86625 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/meteorlake/romstage/fsp_params.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index dd9d2b5..8e49afa 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> #include <assert.h> #include <bootmode.h> #include <console/console.h> @@ -190,7 +191,7 @@ static void fill_tme_params(FSP_M_CONFIG *m_cfg) { m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported(); - if (!m_cfg->TmeEnable) + if (!m_cfg->TmeEnable || acpi_is_wakeup_s3()) return; m_cfg->GenerateNewTmeKey = CONFIG(TME_KEY_REGENERATION_ON_WARM_BOOT) && CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP); -- To view, visit https://review.coreboot.org/c/coreboot/+/86625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie19cb7f11ad633405a9fc3c1faf1c3cc53113f51 Gerrit-Change-Number: 86625 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> [View Less]

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coreboot-gerrit March 2025