coreboot-gerrit March 2025

coreboot-gerrit@coreboot.org

1 participants
2811 discussions

[S] Change in coreboot[main]: cpu/x86: Replace LAPIC_DM_* with LAPIC_MT_*
by Maximilian Brune (Code Review) 02 Mar '25

02 Mar '25

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86683?usp=email ) Change subject: cpu/x86: Replace LAPIC_DM_* with LAPIC_MT_* ...................................................................... cpu/x86: Replace LAPIC_DM_* with LAPIC_MT_* AMD64 spec referst to the field as MT (message type), but the IA64 spec refers to it as DM (Delivery Mode). The problem is that there is another field abbreviated as DM (Destination Mode) right next to it. So for better readabillity just stick to the AMD64 terminology. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I25cf69d555fe22526f128ff7ed41f82b71f2acf2 --- M src/cpu/x86/mp_init.c M src/include/cpu/x86/lapic_def.h 2 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/86683/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 47b3a9e..574f28e 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -434,7 +434,7 @@ printk(BIOS_DEBUG, "done.\n"); } - lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | sipi_vector); + lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_MT_STARTUP | sipi_vector); printk(BIOS_DEBUG, "Waiting for SIPI to complete...\n"); if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */) != CB_SUCCESS) { printk(BIOS_ERR, "timed out.\n"); @@ -474,7 +474,7 @@ } /* Send INIT IPI to all but self. */ - lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_DM_INIT); + lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_MT_INIT); if (!CONFIG(X86_INIT_NEED_1_SIPI)) { printk(BIOS_DEBUG, "Waiting for 10ms after sending INIT.\n"); @@ -658,7 +658,7 @@ printk(BIOS_DEBUG, "done.\n"); } - lapic_send_ipi_self(LAPIC_INT_ASSERT | LAPIC_DM_SMI); + lapic_send_ipi_self(LAPIC_INT_ASSERT | LAPIC_MT_SMI); if (lapic_busy()) { if (apic_wait_timeout(1000 /* 1 ms */, 100 /* us */) != CB_SUCCESS) { diff --git a/src/include/cpu/x86/lapic_def.h b/src/include/cpu/x86/lapic_def.h index e118b6b..d762e0f 100644 --- a/src/include/cpu/x86/lapic_def.h +++ b/src/include/cpu/x86/lapic_def.h @@ -42,14 +42,14 @@ #define LAPIC_INT_ASSERT 0x04000 #define LAPIC_ICR_BUSY 0x01000 #define LAPIC_DEST_LOGICAL 0x00800 -#define LAPIC_DM_FIXED 0x00000 -#define LAPIC_DM_LOWEST 0x00100 -#define LAPIC_DM_SMI 0x00200 -#define LAPIC_DM_REMRD 0x00300 -#define LAPIC_DM_NMI 0x00400 -#define LAPIC_DM_INIT 0x00500 -#define LAPIC_DM_STARTUP 0x00600 -#define LAPIC_DM_EXTINT 0x00700 +#define LAPIC_MT_FIXED 0x00000 +#define LAPIC_MT_LOWEST 0x00100 +#define LAPIC_MT_SMI 0x00200 +#define LAPIC_MT_REMRD 0x00300 +#define LAPIC_MT_NMI 0x00400 +#define LAPIC_MT_INIT 0x00500 +#define LAPIC_MT_STARTUP 0x00600 +#define LAPIC_MT_EXTINT 0x00700 #define LAPIC_VECTOR_MASK 0x000FF #define LAPIC_ICR2 0x310 #define GET_LAPIC_DEST_FIELD(x) (((x)>>24)&0xFF) -- To view, visit https://review.coreboot.org/c/coreboot/+/86683?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I25cf69d555fe22526f128ff7ed41f82b71f2acf2 Gerrit-Change-Number: 86683 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

1 0

[S] Change in coreboot[main]: soc/intel/xeon_sp: Use common smm_info function
by Maximilian Brune (Code Review) 02 Mar '25

02 Mar '25

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86682?usp=email ) Change subject: soc/intel/xeon_sp: Use common smm_info function ...................................................................... soc/intel/xeon_sp: Use common smm_info function Xeons implementation and the common intel implementation are identical so just use the common function. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I0ed42a93444e7cc0d339cf63cec4c4411b5b4f73 --- M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/gnr/cpu.c M src/soc/intel/xeon_sp/include/soc/smmrelocate.h M src/soc/intel/xeon_sp/skx/cpu.c M src/soc/intel/xeon_sp/smmrelocate.c M src/soc/intel/xeon_sp/spr/cpu.c 6 files changed, 4 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/86682/1 diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index ae3f0fb..5df399a 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -186,7 +186,7 @@ static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_platform_thread_count, - .get_smm_info = get_smm_info, + .get_smm_info = smm_info, .pre_mp_smm_init = smm_southbridge_clear_state, .relocation_handler = smm_relocation_handler, .get_microcode_info = get_microcode_info, diff --git a/src/soc/intel/xeon_sp/gnr/cpu.c b/src/soc/intel/xeon_sp/gnr/cpu.c index 71edd70..44f466d 100644 --- a/src/soc/intel/xeon_sp/gnr/cpu.c +++ b/src/soc/intel/xeon_sp/gnr/cpu.c @@ -73,7 +73,7 @@ .pre_mp_init = pre_mp_init, .get_cpu_count = get_platform_thread_count, #if CONFIG(HAVE_SMI_HANDLER) - .get_smm_info = get_smm_info, + .get_smm_info = smm_info, .pre_mp_smm_init = smm_southbridge_clear_state, .relocation_handler = smm_relocation_handler, #endif diff --git a/src/soc/intel/xeon_sp/include/soc/smmrelocate.h b/src/soc/intel/xeon_sp/include/soc/smmrelocate.h index b18d057..c3b179c 100644 --- a/src/soc/intel/xeon_sp/include/soc/smmrelocate.h +++ b/src/soc/intel/xeon_sp/include/soc/smmrelocate.h @@ -5,9 +5,6 @@ #include <cpu/x86/smm.h> -void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); - void soc_ubox_store_resources(struct smm_pci_resource_info *slots, size_t size); #endif diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index 1becda8..e829aa9 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -268,7 +268,7 @@ static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_platform_thread_count, - .get_smm_info = get_smm_info, + .get_smm_info = smm_info, .pre_mp_smm_init = smm_southbridge_clear_state, .relocation_handler = smm_relocation_handler, .get_microcode_info = get_microcode_info, diff --git a/src/soc/intel/xeon_sp/smmrelocate.c b/src/soc/intel/xeon_sp/smmrelocate.c index c359237..79764de 100644 --- a/src/soc/intel/xeon_sp/smmrelocate.c +++ b/src/soc/intel/xeon_sp/smmrelocate.c @@ -71,19 +71,6 @@ memset(ied_base + 1 * MiB, 0, 32 * KiB); } -void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - if (smm_reloc_params.ied_size) - setup_ied_area(&smm_reloc_params); - - *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); -} - static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, struct smm_relocation_params *relo_params) diff --git a/src/soc/intel/xeon_sp/spr/cpu.c b/src/soc/intel/xeon_sp/spr/cpu.c index febc72b..1162da4 100644 --- a/src/soc/intel/xeon_sp/spr/cpu.c +++ b/src/soc/intel/xeon_sp/spr/cpu.c @@ -234,7 +234,7 @@ .pre_mp_init = pre_mp_init, .get_cpu_count = get_platform_thread_count, #if CONFIG(HAVE_SMI_HANDLER) - .get_smm_info = get_smm_info, + .get_smm_info = smm_info, .pre_mp_smm_init = smm_southbridge_clear_state, .relocation_handler = smm_relocation_handler, #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/86682?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ed42a93444e7cc0d339cf63cec4c4411b5b4f73 Gerrit-Change-Number: 86682 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

1 0

[XS] Change in coreboot[main]: cpu/intel/haswell: Usee boolean for haswell_is_ult()
by Nicholas Chin (Code Review) 02 Mar '25

02 Mar '25

Attention is currently required from: Elyes Haouas. Nicholas Chin has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/84857?usp=email ) Change subject: cpu/intel/haswell: Usee boolean for haswell_is_ult() ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84857?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c98ee819fc937ed6da9ee1340c2af10cec19eb3 Gerrit-Change-Number: 84857 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 02 Mar 2025 19:30:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: Documentation/util/intelp2m: Add info for developers
by Maximilian Brune (Code Review) 02 Mar '25

02 Mar '25

Attention is currently required from: Maxim Polyakov. Maximilian Brune has posted comments on this change by Maxim Polyakov. ( https://review.coreboot.org/c/coreboot/+/85791?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: Documentation/util/intelp2m: Add info for developers ...................................................................... Patch Set 4: (1 comment) File Documentation/util/intelp2m/index.md: https://review.coreboot.org/c/coreboot/+/85791/comment/0eaa078c_db30e162?us… : PS4, Line 275: It depends on the changes: the `major` is incremented if a new platform is added, `minor` - if I don't think that makes much sense. The versions should be about compatibility. So major version increment would mean that breaking changes were introduced (like removing/changing a command line option or the output/input of the program. minor versions should be incremented whenever it doesn't matter to any shell scripts using this tool whether it changed or not. That could be a new platform or a new feature that is added. Otherwise I don't see why our tooling should have a version in the first place. -- To view, visit https://review.coreboot.org/c/coreboot/+/85791?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9cc886e607c1aba92b94e06419d45d9581371065 Gerrit-Change-Number: 85791 Gerrit-PatchSet: 4 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Comment-Date: Sun, 02 Mar 2025 18:28:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[L] Change in coreboot[main]: util/intelp2m: Drop multi-template support
by Maximilian Brune (Code Review) 02 Mar '25

02 Mar '25

Attention is currently required from: Maxim Polyakov. Maximilian Brune has posted comments on this change by Maxim Polyakov. ( https://review.coreboot.org/c/coreboot/+/70307?usp=email ) Change subject: util/intelp2m: Drop multi-template support ...................................................................... Patch Set 17: Code-Review+2 (1 comment) Patchset: PS17: > Hi! […] I agree that we need a linter config for our programs written in golang. I am not happy about all this formatting, but I won't block this effort because of it. -- To view, visit https://review.coreboot.org/c/coreboot/+/70307?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07124cca487f11641c4e107134efb8cfc29c6731 Gerrit-Change-Number: 70307 Gerrit-PatchSet: 17 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Comment-Date: Sun, 02 Mar 2025 18:13:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Maxim Polyakov <max.senia.poliak(a)gmail.com> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

1 0

[M] Change in coreboot[main]: soc/amd/cezanne/acpi: Add ACP MSG0 method
by Matt DeVillier (Code Review) 02 Mar '25

02 Mar '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Matt DeVillier has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/86466?usp=email ) Change subject: soc/amd/cezanne/acpi: Add ACP MSG0 method ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86466/comment/b3c56a4e_2fda62cd?us… : PS4, Line 12: > Paste the generated DSL code as the TEST=? Duncan did that in the past, and I liked it. IMO nobody wants 30+ lines of ASL in the commit msg when it's already in the comments of the code being added. That's the whole point of adding the ASL along with the acpigen. Maybe just a 'TEST=decompiled AML matches expected output' or something? -- To view, visit https://review.coreboot.org/c/coreboot/+/86466?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34f641fbfe40b5df7f0ff2fc173510c5cf2a7f61 Gerrit-Change-Number: 86466 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 02 Mar 2025 13:54:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[S] Change in coreboot[main]: mb/google/geralt: Adjust VSP/VSN voltage for CSOT_PNA957QT1_1 panel
by Yang Wu (Code Review) 02 Mar '25

02 Mar '25

Attention is currently required from: Hung-Te Lin, Paul Menzel, Xinxiong Xu, Yidi Lin, Yu-Ping Wu, cong yang. Yang Wu has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/86640?usp=email ) Change subject: mb/google/geralt: Adjust VSP/VSN voltage for CSOT_PNA957QT1_1 panel ...................................................................... Patch Set 5: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86640/comment/76410a28_320037da?us… : PS3, Line 15: TEST=Boot to firmware screen > To the recovery screen? […] Before modifying the voltage, there may be some screen flickering after the kernel boot. And the kernel driver cannot modify this voltage. File src/mainboard/google/geralt/panel_ciri.c: https://review.coreboot.org/c/coreboot/+/86640/comment/bbfa9495_72d3e46d?us… : PS3, Line 11: val > Maybe more descriptive: voltage_reg_val or so? Done https://review.coreboot.org/c/coreboot/+/86640/comment/ab76b8c2_92f91c54?us… : PS3, Line 30: default > Name it 5_7V or so? Done https://review.coreboot.org/c/coreboot/+/86640/comment/1f86b1ba_7eefb8b3?us… : PS3, Line 32: 0x11 > Please define macros for this. Done https://review.coreboot.org/c/coreboot/+/86640/comment/56ebb2b7_4390ff7b?us… : PS3, Line 35: csot > Name it 6V? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1b69303317f5ef47818f4a6a0c851bf650285e51 Gerrit-Change-Number: 86640 Gerrit-PatchSet: 5 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sun, 02 Mar 2025 11:33:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[XS] Change in coreboot[main]: src/acpigen: support 0-initialized buffer in acpigen_write_byte_buffer
by Paul Menzel (Code Review) 02 Mar '25

02 Mar '25

Attention is currently required from: Cliff Huang, Felix Held, Lance Zhao, Tim Wawrzynczak. Paul Menzel has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/86631?usp=email ) Change subject: src/acpigen: support 0-initialized buffer in acpigen_write_byte_buffer ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86631?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie756489e02f994c38d38907a97fb215d30f4a636 Gerrit-Change-Number: 86631 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 02 Mar 2025 11:28:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: acpi/acpigen: implement acpigen_write_if_lnotequal_*
by Paul Menzel (Code Review) 02 Mar '25

02 Mar '25

Attention is currently required from: Cliff Huang, Felix Held, Lance Zhao, Tim Wawrzynczak. Paul Menzel has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/86464?usp=email ) Change subject: acpi/acpigen: implement acpigen_write_if_lnotequal_* ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86464/comment/e434c4f6_8cc66e9a?us… : PS3, Line 9: the AML One space? -- To view, visit https://review.coreboot.org/c/coreboot/+/86464?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c664bc4d30a49ae990eeb9f0e0776cac37efc57 Gerrit-Change-Number: 86464 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 02 Mar 2025 11:25:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[M] Change in coreboot[main]: soc/amd/cezanne/acpi: Add ACP MSG0 method
by Paul Menzel (Code Review) 02 Mar '25

02 Mar '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Paul Menzel has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/86466?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/amd/cezanne/acpi: Add ACP MSG0 method ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86466/comment/f3e03c2c_b8dd0322?us… : PS4, Line 12: Paste the generated DSL code as the TEST=? Duncan did that in the past, and I liked it. -- To view, visit https://review.coreboot.org/c/coreboot/+/86466?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34f641fbfe40b5df7f0ff2fc173510c5cf2a7f61 Gerrit-Change-Number: 86466 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 02 Mar 2025 11:24:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2025