coreboot-gerrit March 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: drivers/intel/usb4: Add mainboard function to get EC port
by Derek Huang (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Kapil Porwal, Subrata Banik, Tarun. Derek Huang has posted comments on this change by Derek Huang. ( https://review.coreboot.org/c/coreboot/+/86673?usp=email ) Change subject: drivers/intel/usb4: Add mainboard function to get EC port ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/meteorlake/retimer.c: https://review.coreboot.org/c/coreboot/+/86673/comment/994ae86d_38ee948a?us… : PS3, Line 16: int ec_port = 0; : : ec_port = mainboard_retimer_get_index_for_typec(typec_port); : if (ec_port >= 0) { : printk(BIOS_INFO, "USB Type-C %d mapped to EC port %d\n", typec_port, : ec_port); : return ec_port; : } else { : ec_port = 0; : } > ``` […] Updated accordingly. In most cases the function returns -1 because the mapping is sequential and no override function is implemented, so I think we don't need the warning print, we can always check `USB Type-C %d mapped to EC port %d` to see if the mapping correct. -- To view, visit https://review.coreboot.org/c/coreboot/+/86673?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaad2a95d8624564ae012d23e8a7f19f6701db2c Gerrit-Change-Number: 86673 Gerrit-PatchSet: 4 Gerrit-Owner: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Mar 2025 02:18:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: drivers/intel/usb4: Add mainboard function to get EC port
by Derek Huang (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Derek Huang, Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Kapil Porwal, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86673?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/intel/usb4: Add mainboard function to get EC port ...................................................................... drivers/intel/usb4: Add mainboard function to get EC port This patch adds mainboard override function which allows for custom port mapping between CPU physical port and EC port to accommodate the non-sequential mapping. Mainboard code must implement this function if the CPU physical port to EC port mapping is not sequential. BUG=b:399032094 TEST=build and verify TCSS port and EC port mapping Change-Id: Ibaad2a95d8624564ae012d23e8a7f19f6701db2c Signed-off-by: Derek Huang <derekhuang(a)google.com> --- M src/drivers/intel/usb4/retimer/retimer.h M src/soc/intel/meteorlake/retimer.c 2 files changed, 27 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/86673/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86673?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaad2a95d8624564ae012d23e8a7f19f6701db2c Gerrit-Change-Number: 86673 Gerrit-PatchSet: 4 Gerrit-Owner: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[S] Change in coreboot[main]: mb/google/geralt: Adjust VSP/VSN voltage for CSOT_PNA957QT1_1 panel
by Yidi Lin (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Hung-Te Lin, Paul Menzel, Xinxiong Xu, Yang Wu, Yu-Ping Wu, cong yang. Yidi Lin has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/86640?usp=email ) Change subject: mb/google/geralt: Adjust VSP/VSN voltage for CSOT_PNA957QT1_1 panel ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1b69303317f5ef47818f4a6a0c851bf650285e51 Gerrit-Change-Number: 86640 Gerrit-PatchSet: 5 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 03 Mar 2025 02:07:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: drivers/intel/usb4: Add mainboard function to get EC port
by Subrata Banik (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Derek Huang, Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Kapil Porwal, Tarun. Subrata Banik has posted comments on this change by Derek Huang. ( https://review.coreboot.org/c/coreboot/+/86673?usp=email ) Change subject: drivers/intel/usb4: Add mainboard function to get EC port ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/meteorlake/retimer.c: https://review.coreboot.org/c/coreboot/+/86673/comment/c23d24bd_bc9cf16b?us… : PS3, Line 16: int ec_port = 0; : : ec_port = mainboard_retimer_get_index_for_typec(typec_port); : if (ec_port >= 0) { : printk(BIOS_INFO, "USB Type-C %d mapped to EC port %d\n", typec_port, : ec_port); : return ec_port; : } else { : ec_port = 0; : } ``` int ec_port = mainboard_retimer_get_index_for_typec(typec_port); if (ec_port >= 0) { printk(BIOS_INFO, "USB Type-C %d mapped to EC port %d\n", typec_port, ec_port); return ec_port; } else { printk(BIOS_WARN, "USB Type-C %d not mapped to any EC port\n", typec_port); return 0; // Default to 0 when no mapping is found. } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/86673?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaad2a95d8624564ae012d23e8a7f19f6701db2c Gerrit-Change-Number: 86673 Gerrit-PatchSet: 3 Gerrit-Owner: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Mar 2025 01:53:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/alderlake: Don't load HsPhy on ADL-N
by Subrata Banik (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Brandon Weeks, Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by Brandon Weeks. ( https://review.coreboot.org/c/coreboot/+/86684?usp=email ) Change subject: soc/intel/alderlake: Don't load HsPhy on ADL-N ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/chip.c: https://review.coreboot.org/c/coreboot/+/86684/comment/686ae4fc_b780cec5?us… : PS1, Line 202: #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) rather than having preprocessor macro check, how about adding a prerequisites check inside load_and_init_hsphy() API for ``` void load_and_init_hsphy(void) { void *hsphy_buf; uint8_t hsphy_hash[MAX_HASH_SIZE] = { 0 }; uint8_t hash_type; uint32_t buf_size = HSPHY_PAYLOAD_SIZE; pci_devfn_t dev = PCH_DEV_CSE; const uint16_t pci_cmd_bme_mem = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; uint32_t status; if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)) { printk(BIOS_DEBUG, "HSPHY firmware loading not supported for ADL-N chipset hence, skipping\n"); return; } if (!is_devfn_enabled(SA_DEVFN_CPU_PCIE1_0) && !is_devfn_enabled(SA_DEVFN_CPU_PCIE1_1)) { printk(BIOS_DEBUG, "All HSPHY ports disabled, skipping HSPHY loading\n"); return; } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/86684?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaaae0e4ce44f8c34f0948e8a292863bad317e8be Gerrit-Change-Number: 86684 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Weeks <bweeks(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Brandon Weeks <bweeks(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 03 Mar 2025 01:50:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: drivers/intel/usb4: Add mainboard function to get EC port
by Derek Huang (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Kapil Porwal, Subrata Banik, Tarun. Derek Huang has posted comments on this change by Derek Huang. ( https://review.coreboot.org/c/coreboot/+/86673?usp=email ) Change subject: drivers/intel/usb4: Add mainboard function to get EC port ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/meteorlake/retimer.c: https://review.coreboot.org/c/coreboot/+/86673/comment/fb54e6ce_6f576358?us… : PS2, Line 23: } else : ec_port = 0; > use braces as well because `if` is multiline statement Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86673?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaad2a95d8624564ae012d23e8a7f19f6701db2c Gerrit-Change-Number: 86673 Gerrit-PatchSet: 3 Gerrit-Owner: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Mar 2025 01:44:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: drivers/intel/usb4: Add mainboard function to get EC port
by Derek Huang (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Derek Huang, Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Kapil Porwal, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86673?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/intel/usb4: Add mainboard function to get EC port ...................................................................... drivers/intel/usb4: Add mainboard function to get EC port This patch adds mainboard override function which allows for custom port mapping between CPU physical port and EC port to accommodate the non-sequential mapping. Mainboard code must implement this function if the CPU physical port to EC port mapping is not sequential. BUG=b:399032094 TEST=build and verify TCSS port and EC port mapping Change-Id: Ibaad2a95d8624564ae012d23e8a7f19f6701db2c Signed-off-by: Derek Huang <derekhuang(a)google.com> --- M src/drivers/intel/usb4/retimer/retimer.h M src/soc/intel/meteorlake/retimer.c 2 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/86673/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86673?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaad2a95d8624564ae012d23e8a7f19f6701db2c Gerrit-Change-Number: 86673 Gerrit-PatchSet: 3 Gerrit-Owner: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[XS] Change in coreboot[main]: cpu/intel/haswell: Usee boolean for haswell_is_ult()
by Elyes Haouas (Code Review) 03 Mar '25

03 Mar '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84857?usp=email ) Change subject: cpu/intel/haswell: Usee boolean for haswell_is_ult() ...................................................................... cpu/intel/haswell: Usee boolean for haswell_is_ult() haswell_is_ult() returns CONFIG(INTEL_LYNXPOINT_LP) which is a boolean, so use boolean instead of int. Change-Id: I3c98ee819fc937ed6da9ee1340c2af10cec19eb3 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84857 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nicholas Chin: Looks good to me, approved diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 5697d0f..f63b0ef 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -4,6 +4,7 @@ #define _CPU_INTEL_HASWELL_H #include <cpu/cpu.h> +#include <stdbool.h> #include <stdint.h> /* CPU types without stepping */ @@ -181,7 +182,7 @@ return cpuid_eax(1) & 0xf; } -static inline int haswell_is_ult(void) +static inline bool haswell_is_ult(void) { return CONFIG(INTEL_LYNXPOINT_LP); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84857?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c98ee819fc937ed6da9ee1340c2af10cec19eb3 Gerrit-Change-Number: 84857 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/alderlake: Don't load HsPhy on ADL-N
by Brandon Weeks (Code Review) 03 Mar '25

03 Mar '25

Brandon Weeks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86684?usp=email ) Change subject: soc/intel/alderlake: Don't load HsPhy on ADL-N ...................................................................... soc/intel/alderlake: Don't load HsPhy on ADL-N ADL-N does not support PCIe 5. Slim Bootloader only loads the HsPhy on ADL-P and ADL-S boards, so this is an attempt to match that behavior. Change-Id: Iaaae0e4ce44f8c34f0948e8a292863bad317e8be Signed-off-by: Brandon Weeks <bweeks(a)google.com> --- M src/soc/intel/alderlake/Makefile.mk M src/soc/intel/alderlake/chip.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/86684/1 diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk index 55fc83ea..26ada12 100644 --- a/src/soc/intel/alderlake/Makefile.mk +++ b/src/soc/intel/alderlake/Makefile.mk @@ -32,7 +32,9 @@ ramstage-y += finalize.c ramstage-y += fsp_params.c ramstage-y += graphics.c +ifeq ($(SOC_INTEL_ALDERLAKE_PCH_N),n) ramstage-y += hsphy.c +endif ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pcie_rp.c diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 0256de4..adcaddd 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -199,8 +199,10 @@ void soc_init_pre_device(void *chip_info) { +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) /* HSPHY FW needs to be loaded before FSP silicon init */ load_and_init_hsphy(); +#endif /* Perform silicon specific init. */ fsp_silicon_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/86684?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaaae0e4ce44f8c34f0948e8a292863bad317e8be Gerrit-Change-Number: 86684 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Weeks <bweeks(a)google.com>

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[S] Change in coreboot[main]: cpu/x86: Replace LAPIC_DM_* with LAPIC_MT_*
by Maximilian Brune (Code Review) 02 Mar '25

02 Mar '25

Attention is currently required from: Jérémy Compostella. Hello Jérémy Compostella, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86683?usp=email to look at the new patch set (#2). Change subject: cpu/x86: Replace LAPIC_DM_* with LAPIC_MT_* ...................................................................... cpu/x86: Replace LAPIC_DM_* with LAPIC_MT_* AMD64 spec referst to the field as MT (message type), but the IA64 spec refers to it as DM (Delivery Mode). The problem is that there is another field abbreviated as DM (Destination Mode) right next to it. So for better readabillity just stick to the AMD64 terminology. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I25cf69d555fe22526f128ff7ed41f82b71f2acf2 --- M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/x86/lapic/lapic_cpu_stop.c M src/cpu/x86/mp_init.c M src/include/cpu/x86/lapic_def.h 4 files changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/86683/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86683?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I25cf69d555fe22526f128ff7ed41f82b71f2acf2 Gerrit-Change-Number: 86683 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

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