coreboot-gerrit March 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/google/brya/gaelin: Enable RTD3 for SSD
by Eric Lai (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N, Subrata Banik. Eric Lai has posted comments on this change by Pranava Y N. ( https://review.coreboot.org/c/coreboot/+/86647?usp=email ) Change subject: mb/google/brya/gaelin: Enable RTD3 for SSD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86647?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a3f4fbddae3806f548705e9a492379c0b38a415 Gerrit-Change-Number: 86647 Gerrit-PatchSet: 1 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 03 Mar 2025 07:30:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/alderlake: Don't load HsPhy on ADL-N
by Brandon Weeks (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Brandon Weeks, Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Hello Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86684?usp=email to look at the new patch set (#2). Change subject: soc/intel/alderlake: Don't load HsPhy on ADL-N ...................................................................... soc/intel/alderlake: Don't load HsPhy on ADL-N ADL-N does not support PCIe 5. Slim Bootloader only loads the HsPhy on ADL-P and ADL-S boards, so this is an attempt to match that behavior. Change-Id: Iaaae0e4ce44f8c34f0948e8a292863bad317e8be Signed-off-by: Brandon Weeks <bweeks(a)google.com> --- M src/soc/intel/alderlake/hsphy.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/86684/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86684?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaaae0e4ce44f8c34f0948e8a292863bad317e8be Gerrit-Change-Number: 86684 Gerrit-PatchSet: 2 Gerrit-Owner: Brandon Weeks <bweeks(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Brandon Weeks <bweeks(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XS] Change in coreboot[main]: mb/google/brya/vell: Enable RTD3 for SSD to resolve S0ix issue
by Pranava Y N (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Pranava Y N has posted comments on this change by Pranava Y N. ( https://review.coreboot.org/c/coreboot/+/86646?usp=email ) Change subject: mb/google/brya/vell: Enable RTD3 for SSD to resolve S0ix issue ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86646/comment/9aa7deb1_c4aca8e4?us… : PS1, Line 7: Enable RTD3 for SSD > … for S0ix/C10 Acknowledged https://review.coreboot.org/c/coreboot/+/86646/comment/a624251d_d4b459b1?us… : PS1, Line 12: > Please document the schematic name and version, where you got the GPIOs from. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/86646?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9015f992cc797af013e8882630220b3df41dc9b3 Gerrit-Change-Number: 86646 Gerrit-PatchSet: 2 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 03 Mar 2025 06:39:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/brya/vell: Enable RTD3 for SSD to resolve S0ix issue
by Pranava Y N (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86646?usp=email to look at the new patch set (#2). Change subject: mb/google/brya/vell: Enable RTD3 for SSD to resolve S0ix issue ...................................................................... mb/google/brya/vell: Enable RTD3 for SSD to resolve S0ix issue Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. Enable and reset GPIOs are configured as per pin mapping in gpio.c. BUG=b:391612392 TEST=Run suspend_stress_test on vell and verify that the device suspends to S0ix. Change-Id: I9015f992cc797af013e8882630220b3df41dc9b3 Signed-off-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/brya/variants/vell/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/86646/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86646?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9015f992cc797af013e8882630220b3df41dc9b3 Gerrit-Change-Number: 86646 Gerrit-PatchSet: 2 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/google/brya/constitution: Enable RTD3 for SSD to resolve S0ix issue
by Pranava Y N (Code Review) 03 Mar '25

03 Mar '25

Pranava Y N has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86686?usp=email ) Change subject: mb/google/brya/constitution: Enable RTD3 for SSD to resolve S0ix issue ...................................................................... mb/google/brya/constitution: Enable RTD3 for SSD to resolve S0ix issue Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. BUG=b:391612392 TEST=Run suspend_stress_test on constitution device and verify that the device suspends to S0ix. Change-Id: Ia367911d6d55b1f769c1660a6f42118988975621 Signed-off-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/brya/variants/constitution/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/86686/1 diff --git a/src/mainboard/google/brya/variants/constitution/overridetree.cb b/src/mainboard/google/brya/variants/constitution/overridetree.cb index 01e4a15..f6c5380 100644 --- a/src/mainboard/google/brya/variants/constitution/overridetree.cb +++ b/src/mainboard/google/brya/variants/constitution/overridetree.cb @@ -145,6 +145,13 @@ .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end end device ref tcss_dma0 on chip drivers/intel/usb4/retimer -- To view, visit https://review.coreboot.org/c/coreboot/+/86686?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia367911d6d55b1f769c1660a6f42118988975621 Gerrit-Change-Number: 86686 Gerrit-PatchSet: 1 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/google/brya: Enable RTD3 for SSD to resolve S0ix issue
by Pranava Y N (Code Review) 03 Mar '25

03 Mar '25

Pranava Y N has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86685?usp=email ) Change subject: mb/google/brya: Enable RTD3 for SSD to resolve S0ix issue ...................................................................... mb/google/brya: Enable RTD3 for SSD to resolve S0ix issue Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. BUG=b:391612392 TEST=Run suspend_stress_test on brya device and verify that the device suspends to S0ix. Change-Id: Ifc85b85ef57216dc394f9a2e1b25bb7154da658f Signed-off-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/86685/1 diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 6160ebf..3a748ea 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -192,6 +192,13 @@ .clk_req = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "1" + device generic 0 on end + end end #PCIE9-12 SSD device ref uart0 on end device ref gspi1 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/86685?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc85b85ef57216dc394f9a2e1b25bb7154da658f Gerrit-Change-Number: 86685 Gerrit-PatchSet: 1 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: mb/google/trulo/var/uldrenite: Support body detection to DPTF
by John Su (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. John Su has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/86494?usp=email ) Change subject: mb/google/trulo/var/uldrenite: Support body detection to DPTF ...................................................................... Patch Set 4: (1 comment) File src/ec/google/chromeec/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/86494/comment/52b9164c_8ef3087b?us… : PS3, Line 484: Method (_Q21, 0, NotSerialized) > Could you please confirm that the feature is working with the latest changes? Yes, I can confirm this feature is working with the latest changes. I confirm that the patch I provided for our thermal team to verify is correct. However, when I uploaded the code, I made a mistake due to copying and pasting. -- To view, visit https://review.coreboot.org/c/coreboot/+/86494?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e98b9c3fd1b38d10a1aa7c30d5d92e1638449f2 Gerrit-Change-Number: 86494 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Mon, 03 Mar 2025 06:02:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: John Su <john_su(a)compal.corp-partner.google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[S] Change in coreboot[main]: mb/google/trulo/var/uldrenite: Support body detection to DPTF
by Kapil Porwal (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, John Su, Nick Vaccaro, Subrata Banik. Kapil Porwal has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/86494?usp=email ) Change subject: mb/google/trulo/var/uldrenite: Support body detection to DPTF ...................................................................... Patch Set 4: (1 comment) File src/ec/google/chromeec/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/86494/comment/d730147a_94bffdd0?us… : PS3, Line 484: Method (_Q21, 0, NotSerialized) > Sorry, added to the wrong place. Now corrected. Could you please confirm that the feature is working with the latest changes? -- To view, visit https://review.coreboot.org/c/coreboot/+/86494?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e98b9c3fd1b38d10a1aa7c30d5d92e1638449f2 Gerrit-Change-Number: 86494 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Mon, 03 Mar 2025 04:16:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: John Su <john_su(a)compal.corp-partner.google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[S] Change in coreboot[main]: mb/google/trulo/var/uldrenite: Support body detection to DPTF
by John Su (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. John Su has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/86494?usp=email ) Change subject: mb/google/trulo/var/uldrenite: Support body detection to DPTF ...................................................................... Patch Set 4: (1 comment) This change is ready for review. File src/ec/google/chromeec/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/86494/comment/0fec2690_80cc981d?us… : PS3, Line 484: Method (_Q21, 0, NotSerialized) > This method doesn't have any action/commands. […] Sorry, added to the wrong place. Now corrected. -- To view, visit https://review.coreboot.org/c/coreboot/+/86494?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e98b9c3fd1b38d10a1aa7c30d5d92e1638449f2 Gerrit-Change-Number: 86494 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Mon, 03 Mar 2025 03:27:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[S] Change in coreboot[main]: drivers/intel/usb4: Add mainboard function to get EC port
by Subrata Banik (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Derek Huang, Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Kapil Porwal, Tarun. Subrata Banik has posted comments on this change by Derek Huang. ( https://review.coreboot.org/c/coreboot/+/86673?usp=email ) Change subject: drivers/intel/usb4: Add mainboard function to get EC port ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File src/soc/intel/meteorlake/retimer.c: https://review.coreboot.org/c/coreboot/+/86673/comment/e0f41896_897a15a0?us… : PS3, Line 16: int ec_port = 0; : : ec_port = mainboard_retimer_get_index_for_typec(typec_port); : if (ec_port >= 0) { : printk(BIOS_INFO, "USB Type-C %d mapped to EC port %d\n", typec_port, : ec_port); : return ec_port; : } else { : ec_port = 0; : } > Updated accordingly. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/86673?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaad2a95d8624564ae012d23e8a7f19f6701db2c Gerrit-Change-Number: 86673 Gerrit-PatchSet: 4 Gerrit-Owner: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Mar 2025 02:50:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Derek Huang <derekhuang(a)google.com>

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coreboot-gerrit March 2025