coreboot-gerrit March 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Remove useless LVTS controller
by Yidi Lin (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86687?usp=email ) Change subject: soc/mediatek/mt8196: Remove useless LVTS controller ...................................................................... Patch Set 2: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86687/comment/64fd55a9_4a49a2c0?us… : PS2, Line 7: controller controllers https://review.coreboot.org/c/coreboot/+/86687/comment/c2f8924d_1e80899a?us… : PS2, Line 7: useless unused -- To view, visit https://review.coreboot.org/c/coreboot/+/86687?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I69c1e76e7de544fd4e24e8e94e4f676de783e205 Gerrit-Change-Number: 86687 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 03 Mar 2025 11:33:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE
by Filip Lewiński (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Felix Singer, Intel coreboot Reviewers, Jérémy Compostella, Krystian Hebel, Martin Roth, Michał Kopeć, Michał Żygowski, Paul Menzel. Filip Lewiński has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/83730?usp=email ) Change subject: soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/cannonlake/lockdown.c: https://review.coreboot.org/c/coreboot/+/83730/comment/4a8bc3ed_fd857f97?us… : PS8, Line 3: #include <cpu/x86/msr.h> : #include <cpu/intel/msr.h> > I know this is not a formal rule, but implicitly we generally try to keep the header file inclusion […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83730?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ed4382bbe68f03e8eca151245c13928609f434f Gerrit-Change-Number: 83730 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-CC: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 03 Mar 2025 11:31:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE
by Filip Lewiński (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Felix Singer, Filip Lewiński, Intel coreboot Reviewers, Jérémy Compostella, Krystian Hebel, Martin Roth, Michał Kopeć, Michał Żygowski, Paul Menzel. Filip Lewiński has uploaded a new patch set (#9) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/83730?usp=email ) The following approvals got outdated and were removed: Code-Review+1 by Jérémy Compostella, Verified+1 by build bot (Jenkins) Change subject: soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE ...................................................................... soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE Intel TXT requires the debug interface to be disabled. There is no way to program the MSR_IA32_DEBUG_INTERFACE using FSP as needed, so let coreboot handle it. TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled Change-Id: I7ed4382bbe68f03e8eca151245c13928609f434f Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/include/cpu/intel/msr.h M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/lockdown.c 3 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/83730/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/83730?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ed4382bbe68f03e8eca151245c13928609f434f Gerrit-Change-Number: 83730 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-CC: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Save HW protect temperature to SRAM
by Zhaoqing Jiu (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Zhaoqing Jiu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86551?usp=email ) Change subject: soc/mediatek/mt8196: Save HW protect temperature to SRAM ...................................................................... Patch Set 4: (1 comment) File src/soc/mediatek/mt8196/thermal.c: https://review.coreboot.org/c/coreboot/+/86551/comment/41f0c31a_9e6393f6?us… : PS2, Line 606: if (tc_num == LVTS_AP_CONTROLLER0) : tc_index = 0; : else if (tc_num == LVTS_AP_CONTROLLER1) : tc_index = 1; : : if (tc_index != 0xff) { : thermal_write_reboot_msr_sram(tc_index, raw_high); : if (tc_index == 0) : thermal_write_reboot_temp_sram(tc->reboot_temperature); : } > Remove the entries first. patch: 86687 -- To view, visit https://review.coreboot.org/c/coreboot/+/86551?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib714c297871132907e286536c4b3aea1532f3869 Gerrit-Change-Number: 86551 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 03 Mar 2025 11:17:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Remove useless LVTS controller
by Jarried Lin (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, Zhaoqing Jiu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86687?usp=email to look at the new patch set (#2). Change subject: soc/mediatek/mt8196: Remove useless LVTS controller ...................................................................... soc/mediatek/mt8196: Remove useless LVTS controller Controller2 and controller3 are disabled, remove them from source code. BRANCH=rauru BUG=b:389026545 TEST=Boot up to kernel Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Change-Id: I69c1e76e7de544fd4e24e8e94e4f676de783e205 --- M src/soc/mediatek/mt8196/include/soc/thermal_internal.h M src/soc/mediatek/mt8196/thermal.c 2 files changed, 0 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/86687/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86687?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I69c1e76e7de544fd4e24e8e94e4f676de783e205 Gerrit-Change-Number: 86687 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Remove useless LVTS controller
by Jarried Lin (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu, Zhaoqing Jiu. Hello Zhaoqing Jiu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/86687?usp=email to review the following change. Change subject: soc/mediatek/mt8196: Remove useless LVTS controller ...................................................................... soc/mediatek/mt8196: Remove useless LVTS controller Controller2 and controller3 are disabled, remove them from soure code. BRANCH=rauru BUG=b:389026545 TEST=Boot up to kernel Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Change-Id: I69c1e76e7de544fd4e24e8e94e4f676de783e205 --- M src/soc/mediatek/mt8196/include/soc/thermal_internal.h M src/soc/mediatek/mt8196/thermal.c 2 files changed, 0 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/86687/1 diff --git a/src/soc/mediatek/mt8196/include/soc/thermal_internal.h b/src/soc/mediatek/mt8196/include/soc/thermal_internal.h index 55c300d..7ced0b0 100644 --- a/src/soc/mediatek/mt8196/include/soc/thermal_internal.h +++ b/src/soc/mediatek/mt8196/include/soc/thermal_internal.h @@ -23,28 +23,18 @@ L_TS_LVTS12_1, /* LVTS12-1 SOC-BOT */ L_TS_LVTS12_2, /* LVTS12-2 SOC-BOT */ L_TS_LVTS12_3, /* LVTS12-3 SOC-BOT */ - L_TS_LVTS13_0, /* LVTS13-0 MD-AP */ - L_TS_LVTS13_1, /* LVTS13-1 MD-AP */ - L_TS_LVTS13_2, /* LVTS13-2 MD-AP */ - L_TS_LVTS13_3, /* LVTS13-3 MD-AP */ - L_TS_LVTS14_0, /* LVTS14-0 SOC-ADCT */ - L_TS_LVTS14_3, /* LVTS14-3 SOC-ADCT */ L_TS_LVTS_NUM, }; enum lvts_tc { LVTS_AP_CONTROLLER0 = 0, LVTS_AP_CONTROLLER1, - LVTS_AP_CONTROLLER2, - LVTS_AP_CONTROLLER3, LVTS_CONTROLLER_NUM, }; enum lvts_tc_offset { TS_OFFSET_AP_CONTROLLER0 = 0, TS_OFFSET_AP_CONTROLLER1 = 0x100, - TS_OFFSET_AP_CONTROLLER2 = 0x200, - TS_OFFSET_AP_CONTROLLER3 = 0x300, }; enum sensor_switch_status { @@ -80,10 +70,6 @@ mtk_lvts_ap_controller0 = (void *)(THERM_CTRL_BASE + TS_OFFSET_AP_CONTROLLER0); static struct mtk_thermal_controller_regs *const mtk_lvts_ap_controller1 = (void *)(THERM_CTRL_BASE + TS_OFFSET_AP_CONTROLLER1); -static struct mtk_thermal_controller_regs *const - mtk_lvts_ap_controller2 = (void *)(THERM_CTRL_BASE + TS_OFFSET_AP_CONTROLLER2); -static struct mtk_thermal_controller_regs *const - mtk_lvts_ap_controller3 = (void *)(THERM_CTRL_BASE + TS_OFFSET_AP_CONTROLLER3); struct mtk_thermal_controller_regs { u32 lvtsmonctl0_0; diff --git a/src/soc/mediatek/mt8196/thermal.c b/src/soc/mediatek/mt8196/thermal.c index 0e284ce..84cd8d8 100644 --- a/src/soc/mediatek/mt8196/thermal.c +++ b/src/soc/mediatek/mt8196/thermal.c @@ -67,36 +67,6 @@ }, .regs = mtk_lvts_ap_controller1, }, - [LVTS_AP_CONTROLLER2] = { /* MD-AP */ - .ts = {L_TS_LVTS13_0, L_TS_LVTS13_1, L_TS_LVTS13_2, L_TS_LVTS13_3}, - .sensor_on_off = {SEN_ON, SEN_ON, SEN_ON, SEN_ON}, - .ctrl_on_off = CTRL_OFF, - .ts_number = 4, - .reboot_temperature = 118800, - .dominator_ts_idx = 0, - .speed = { - .group_interval_delay = 0x7fff, - .period_unit = 0x001, - .filter_interval_delay = 0x001, - .sensor_interval_delay = 0x001, - }, - .regs = mtk_lvts_ap_controller2, - }, - [LVTS_AP_CONTROLLER3] = { /* SOC-ADCT */ - .ts = {L_TS_LVTS14_0, L_TS_LVTS14_3}, - .sensor_on_off = {SEN_ON, SEN_ON}, - .ctrl_on_off = CTRL_OFF, - .ts_number = 2, - .reboot_temperature = 118800, - .dominator_ts_idx = 0, - .speed = { - .group_interval_delay = 0x7fff, - .period_unit = 0x001, - .filter_interval_delay = 0x001, - .sensor_interval_delay = 0x001, - }, - .regs = mtk_lvts_ap_controller3, - }, }; static uint32_t golden_temp; -- To view, visit https://review.coreboot.org/c/coreboot/+/86687?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I69c1e76e7de544fd4e24e8e94e4f676de783e205 Gerrit-Change-Number: 86687 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Save HW protect temperature to SRAM
by Jarried Lin (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, Zhaoqing Jiu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86551?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Save HW protect temperature to SRAM ...................................................................... soc/mediatek/mt8196: Save HW protect temperature to SRAM It will restore the HW protection settings based on the data saved in the SRAM, after the system suspends and resumes. BRANCH=rauru BUG=b:389026545 TEST=Boot up and check temperature in coreboot log: [INFO ] [LVTS_MSR] ts0 msr_all=141d0, msr_temp=16848, temp=41086 [INFO ] lvts_tscpu_thermal_read_tc_temp order 0 ts_name 0 temp 41086 rg_temp 41073(42059) [INFO ] [LVTS_MSR] ts1 msr_all=141e3, msr_temp=16867, temp=41540 [INFO ] lvts_tscpu_thermal_read_tc_temp order 1 ts_name 1 temp 41540 rg_temp 41526(42523) [INFO ] [LVTS_MSR] ts2 msr_all=14199, msr_temp=16793, temp=39772[0m [INFO ] lvts_tscpu_thermal_read_tc_temp order 2 ts_name 2 temp 39772 rg_temp 39760(40715) [INFO ] [LVTS_MSR] ts3 msr_all=141c2, msr_temp=16834, temp=40751 [INFO ] lvts_tscpu_thermal_read_tc_temp order 3 ts_name 3 temp 40751 rg_temp 40739(41717) [INFO ] [LVTS_MSR] ts4 msr_all=141d0, msr_temp=16848, temp=41086 [INFO ] lvts_tscpu_thermal_read_tc_temp order 0 ts_name 4 temp 41086 rg_temp 41073(42059) [INFO ] [LVTS_MSR] ts5 msr_all=141b3, msr_temp=16819, temp=40393 [INFO ] lvts_tscpu_thermal_read_tc_temp order 1 ts_name 5 temp 40393 rg_temp 40380(41350) [INFO ] [LVTS_MSR] ts6 msr_all=14194, msr_temp=16788, temp=39652 [INFO ] lvts_tscpu_thermal_read_tc_temp order 2 ts_name 6 temp 39652 rg_temp 39641(40593) [INFO ] [LVTS_MSR] ts7 msr_all=14186, msr_temp=16774, temp=39318 [INFO ] lvts_tscpu_thermal_read_tc_temp order 3 ts_name 7 temp 39318 rg_temp 39307(40251) Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Change-Id: Ib714c297871132907e286536c4b3aea1532f3869 --- M src/soc/mediatek/mt8196/include/soc/thermal.h M src/soc/mediatek/mt8196/thermal.c M src/soc/mediatek/mt8196/thermal_sram.c 3 files changed, 27 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/86551/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86551?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib714c297871132907e286536c4b3aea1532f3869 Gerrit-Change-Number: 86551 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in coreboot[main]: mb/google/brya/gaelin: Enable RTD3 for SSD
by Subrata Banik (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N. Subrata Banik has posted comments on this change by Pranava Y N. ( https://review.coreboot.org/c/coreboot/+/86647?usp=email ) Change subject: mb/google/brya/gaelin: Enable RTD3 for SSD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86647?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a3f4fbddae3806f548705e9a492379c0b38a415 Gerrit-Change-Number: 86647 Gerrit-PatchSet: 1 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 03 Mar 2025 10:37:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brya/nova: Enable RTD3 for SSD
by Subrata Banik (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N. Subrata Banik has posted comments on this change by Pranava Y N. ( https://review.coreboot.org/c/coreboot/+/86649?usp=email ) Change subject: mb/google/brya/nova: Enable RTD3 for SSD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86649?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb36285d0a12dcb098282b08ef794256af67b019 Gerrit-Change-Number: 86649 Gerrit-PatchSet: 1 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 03 Mar 2025 10:37:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brya/constitution: Enable RTD3 for SSD to resolve S0ix issue
by Subrata Banik (Code Review) 03 Mar '25

03 Mar '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N. Subrata Banik has posted comments on this change by Pranava Y N. ( https://review.coreboot.org/c/coreboot/+/86686?usp=email ) Change subject: mb/google/brya/constitution: Enable RTD3 for SSD to resolve S0ix issue ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86686?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia367911d6d55b1f769c1660a6f42118988975621 Gerrit-Change-Number: 86686 Gerrit-PatchSet: 1 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 03 Mar 2025 10:37:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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