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Change subject: mb/google/skywalker: Setup USB host in ramstage
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/87022/comment/aa5dbebc_bac6eaa1?us… :
PS1, Line 7: Setup
The verb is spelled with a space: Set up.
https://review.coreboot.org/c/coreboot/+/87022/comment/9e965779_93f9447a?us… :
PS1, Line 13: TEST=build passed.
Tested on the device?
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Change subject: mb/google/nissa/var/dirks: Add romstage early graphics for dirks
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/dirks/gpio.c:
https://review.coreboot.org/c/coreboot/+/87020/comment/423322e3_9d307566?us… :
PS1, Line 170: GPP_H17
> Can we avoid reconfiguration of these GPIOs in ramstage?
Remove reconfiguration of these GPIOs in ramstage, HDMI will not display. Thanks.
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Attention is currently required from: Bora Guvendik, Cliff Huang, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Kyoung Il Kim, Paul Menzel, Pranava Y N, Subrata Banik, Wonkyu Kim.
Hello Bora Guvendik, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Kyoung Il Kim, Pranava Y N, Subrata Banik, Wonkyu Kim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#35).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/pantherlake: Add Touch Controller UPD and SoC config
......................................................................
soc/intel/pantherlake: Add Touch Controller UPD and SoC config
This commit introduces the necessary changes to configure the Touch
Host Controller User Platform Data (UPD) fields such as ThcAssignment,
ThcMode, and ThcWakeOnTouch according to the specific SoC chip
configuration derived from the devicetree.
Key changes include:
- Creation of override functions to supply SoC-specific configurations
for the Touch Host Controller (THC).
- Addition of a new SoC-specific THC header file.
- Inclusion of a motherboard (MB)-specific THC header file.
- Establishment of a build path to allow devicetree to leverage
variant-specific defines.
BUG=none
TEST=Add CONFIG_DRIVERS_INTEL_TOUCH to fatcat board with the devicetree
changes for touchscreen and/or touchpad, as well as proper CBI settings.
Boot the board to OS and check that the THC SoC-specific info is
generated in the SSDT.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I15fb62eaadc03b9a17e94609b97c686518150e2e
---
M src/soc/intel/pantherlake/Makefile.mk
M src/soc/intel/pantherlake/chip.h
M src/soc/intel/pantherlake/fsp_params.c
A src/soc/intel/pantherlake/include/soc/touch.h
A src/soc/intel/pantherlake/touch.c
5 files changed, 134 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/85199/35
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I'd like you to reexamine a change. Please visit
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Change subject: mb/var/uldrenite: Configure descriptor for either MBVR or FIVR
......................................................................
mb/var/uldrenite: Configure descriptor for either MBVR or FIVR
According to the root cause analysis in b/404126972#comment22,
Right now, it is set to FIVR, , which leads to a system reboot issue
due to OVP being triggered (MBVR and FIVR existing simultaneously).
The current build's main source is MBVR, so we want to use fw_config
to dynamically adjust MFIT and MBVR with the current phase devices to
ensure consistency in client devices settings.
CONFIGURE_DESCRIPTOR is a temporary workaround for the current phase.
In the next phase, we will choose a specific setting for implementation.
If there are any concerns, we use the board ID to restrict it.
BUG=b:404126972
TEST=boot to ChromeOS
Change-Id: I337574c8c55889ceb49b9f33625feadb48bd8890
Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/uldrenite/Makefile.mk
M src/mainboard/google/brya/variants/uldrenite/variant.c
3 files changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/87033/4
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Change subject: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING
......................................................................
Patch Set 18:
(1 comment)
File src/mainboard/google/brya/variants/meliks/ramstage.c:
https://review.coreboot.org/c/coreboot/+/86838/comment/8e29a9c7_9ed600b3?us… :
PS17, Line 20: 0xf
> ``` […]
Looks good.
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Change subject: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING
......................................................................
Patch Set 17:
(1 comment)
File src/mainboard/google/brya/variants/meliks/ramstage.c:
https://review.coreboot.org/c/coreboot/+/86838/comment/d4aef2e2_67eb270e?us… :
PS17, Line 20: 0xf
> Doesn't find an available macro in this stage.
```
static uint32_t igd_mem_base(void)
{
uint32_t igd_bar = pci_read_config32(SA_DEVFN_IGD, PCI_BASE_ADDRESS_0);
/* Check if the controller is disabled or not present */
if (igd_bar == 0 || igd_bar == 0xffffffff)
return 0;
return (igd_bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK);
}
static void reset_display_dphy_clock(void)
{
uint32_t igd_base = igd_mem_base();
if (!igd_base)
return;
write32p(igd_base + DPHY_0_CLOCK_LANE_TIMING, RESET_DPHY_0_CLOCK_LANE_TIMING);
}
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
/* Please add a description about the need of this code */
reset_display_dphy_clock();
}
```
WDYT ?
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Change subject: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING
......................................................................
Patch Set 18:
(1 comment)
File src/mainboard/google/brya/variants/meliks/ramstage.c:
https://review.coreboot.org/c/coreboot/+/86838/comment/4146db53_219fed9f?us… :
PS17, Line 20: 0xf
> Doesn't find an available macro in this stage.
Done
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Change subject: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING
......................................................................
mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING
According to the analysis results, resetting the DSI DPHY to default
during a warm boot is needed if 'You are in developer mode' needs to be
displayed on the screen in a system using the MIPI-DSI panel.
DPHY_0_CLOCK_LANE_TIMING -- address:0x162180, size: 32 bits
[31]: CLK_PREPARE Override. 0:HW maintains, 1:SW overrides
[30..28]: CLK_PREPARE
[27]: CLK_ZERO Override. 0:HW maintains, 1:SW overrides
[23..20]: CLK_ZERO
[19]: CLK_PRE Override. 0:HW maintains, 1:SW overrides
[17..16]: CLK_PRE
[15]: CLK_POST Override. 0:HW maintains, 1:SW overrides
[10..8]: CLK_POST
[7]: CLK_TRAIL Override. 0:HW maintains, 1:SW overrides
[2..0]: CLK_TRAIL
BUG=b:397805262
TEST=Able to show 'You are in developer mode'
Change-Id: I7857c4f71fc7d1d0c5069a462bdd70c8dbb78179
Signed-off-by: Gareth Yu <gareth.yu(a)intel.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/meliks/Makefile.mk
A src/mainboard/google/brya/variants/meliks/ramstage.c
2 files changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/86838/18
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Vince Liu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/86997?usp=email )
Change subject: soc/mediatek/mt8189: Add NOR-Flash support
......................................................................
Patch Set 2:
(1 comment)
File src/soc/mediatek/mt8189/spi.c:
https://review.coreboot.org/c/coreboot/+/86997/comment/5faecea7_34b8b792?us… :
PS1, Line 8:
> remove the blank line
Done
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