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Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/mediatek/mt8189: Add NOR-Flash support
......................................................................
soc/mediatek/mt8189: Add NOR-Flash support
Add NOR-Flash drivers for flash read/write.
BUG=b:379008996
BRANCH=none
TEST=Read NOR flash data successfully.
Signed-off-by: Noah Shen <noah.shen(a)mediatek.corp-partner.google.com>
Change-Id: I3a5b7682e4093f9eddf825bc57267b0180cf8b3c
---
M src/soc/mediatek/mt8189/Kconfig
M src/soc/mediatek/mt8189/Makefile.mk
M src/soc/mediatek/mt8189/include/soc/spi.h
M src/soc/mediatek/mt8189/spi.c
4 files changed, 24 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/86997/2
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Change subject: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING
......................................................................
Patch Set 17:
(1 comment)
File src/mainboard/google/brya/variants/meliks/ramstage.c:
https://review.coreboot.org/c/coreboot/+/86838/comment/9af8fab2_06ac9a09?us… :
PS17, Line 20: 0xf
Doesn't find an available macro in this stage.
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Change subject: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING
......................................................................
mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING
According to the analysis results, resetting the DSI DPHY to default
during a warm boot is needed if 'You are in developer mode' needs to be
displayed on the screen in a system using the MIPI-DSI panel.
DPHY_CLK_TIMING_PARAM_0 -- address:0x162180, size: 32 bits
[31]: CLK_PREPARE Override. 0:HW maintains, 1:SW overrides
[30..28]: CLK_PREPARE
[27]: CLK_ZERO Override. 0:HW maintains, 1:SW overrides
[23..20]: CLK_ZERO
[19]: CLK_PRE Override. 0:HW maintains, 1:SW overrides
[17..16]: CLK_PRE
[15]: CLK_POST Override. 0:HW maintains, 1:SW overrides
[10..8]: CLK_POST
[7]: CLK_TRAIL Override. 0:HW maintains, 1:SW overrides
[2..0]: CLK_TRAIL
BUG=b:397805262
TEST=Able to show 'You are in developer mode'
Change-Id: I7857c4f71fc7d1d0c5069a462bdd70c8dbb78179
Signed-off-by: Gareth Yu <gareth.yu(a)intel.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/meliks/Makefile.mk
A src/mainboard/google/brya/variants/meliks/ramstage.c
2 files changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/86838/17
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Change subject: soc/mediatek/mt8189: Add usb host support
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/87021/comment/3fc0da76_009a10b3?us… :
PS1, Line 7: usb
USB
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Change subject: soc/mediatek/mt8189: Add NOR-Flash support
......................................................................
Patch Set 1:
(1 comment)
File src/soc/mediatek/mt8189/spi.c:
https://review.coreboot.org/c/coreboot/+/86997/comment/e9370a0b_3a1acb6a?us… :
PS1, Line 8:
remove the blank line
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Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:
https://review.coreboot.org/c/coreboot/+/85413/comment/1ff67ee4_f0eb851f?us… :
PS7, Line 104: 0x40
> I have been looking at the magic values of 0x20/0x40/0x70, but after digging through vendor BIOS, looks like the actual values I need are 0x00/0x20/0x70.
I guess that these values are obtained on p8z77-v_le_plus. If so, they may not apply to p8z77-v.
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Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
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Patch Set 7:
(1 comment)
File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:
https://review.coreboot.org/c/coreboot/+/85413/comment/1b581b70_c4582578?us… :
PS7, Line 104: 0x40
> Sorry for the inaccuracy again. gpio5 |= 0x40 works well. […]
gpio5 |= 0x00 when when a card is present at PCIEX1_2 hardly makes any difference.
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Change subject: mb/google/nissa/var/meliks: Replace SPD for RAMID 2 with Samsung K3KL8L80CM-MGCT
......................................................................
Patch Set 1: Code-Review+2
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Change subject: security/vboot: Add option for enabling ADB over network via GBB flag
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> > Thoughts?
>
> I think we should not land any designs on the main branch before they are final. That's what we have the separate bring-up branch for.
>
> I don't know what the exact situation on Fatcat is right now, but if you want to boot AL there you should still be using the bringup branch anyway(?),
ALOS FW branch clone coreboot from mainline and no local changes resides in that branch in terms of coreboot.
> and if you don't then you shouldn't need this flag. (Also, all this does is configure the default that coreboot builds the image with, you can still always manually change the image with gbb_utility afterwards.)
That is the case today, everyone requires to set GBB to enable bit 31 for ADB after downloading AL FW image. Often folks missed to do so and raise concern that ADB is not working. I'm trying to keep ADB enabled in the AP FW image so when they flash AP FW from CPFE/AL bucket they see ADB is default enabled.
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