coreboot-gerrit March 2025

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[S] Change in coreboot[main]: soc/mediatek/mt8189: Reserve DRAM buffers for HW TX TRACKING
by Vince Liu (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Vince Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87039?usp=email ) Change subject: soc/mediatek/mt8189: Reserve DRAM buffers for HW TX TRACKING ...................................................................... soc/mediatek/mt8189: Reserve DRAM buffers for HW TX TRACKING HW TX tracking works by writing a pattern to the designated DRAM buffer and then reading it back automatically to calculate the appropriate TX time delay. To avoid writing the pattern to system-used memory, we need to permanently reserve last 64KB memory on each rank for the HW TX tracking feature. BUG=b:379008996 BRANCH=none TEST=Reserve memory ok Firmware shows the following log : 000000013fff0000-000000013fffffff: RESERVED 000000023fff0000-000000023fffffff: RESERVED Signed-off-by: Mike Lin <mike.lin(a)mediatek.corp-partner.google.com> Change-Id: I2ecfe42dc9f1882163d03f50cf9b5ff8e98c2972 --- M src/soc/mediatek/mt8189/Makefile.mk M src/soc/mediatek/mt8189/soc.c 2 files changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/87039/1 diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk index bdee1fb..7631bc6 100644 --- a/src/soc/mediatek/mt8189/Makefile.mk +++ b/src/soc/mediatek/mt8189/Makefile.mk @@ -19,6 +19,7 @@ romstage-y += ../common/memory.c ../common/memory_test.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +ramstage-y += ../common/dramc_info.c ramstage-y += ../common/emi.c ramstage-y += ../common/memory.c ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c diff --git a/src/soc/mediatek/mt8189/soc.c b/src/soc/mediatek/mt8189/soc.c index e4dfc23..ea89b51 100644 --- a/src/soc/mediatek/mt8189/soc.c +++ b/src/soc/mediatek/mt8189/soc.c @@ -1,9 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +#include <bootmem.h> #include <device/device.h> -#include <soc/emi.h> #include <symbols.h> +#include <soc/dramc_info.h> +#include <soc/emi.h> + +void bootmem_platform_add_ranges(void) +{ + reserve_buffer_for_dramc(); +} + static void soc_read_resources(struct device *dev) { ram_range(dev, 0, (uintptr_t)_dram, sdram_size()); -- To view, visit https://review.coreboot.org/c/coreboot/+/87039?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2ecfe42dc9f1882163d03f50cf9b5ff8e98c2972 Gerrit-Change-Number: 87039 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: mb/google/skywalker: Add DRAM calibration init entry
by Vince Liu (Code Review) 28 Mar '25

28 Mar '25

Vince Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87038?usp=email ) Change subject: mb/google/skywalker: Add DRAM calibration init entry ...................................................................... mb/google/skywalker: Add DRAM calibration init entry Add DRAM calibration entry in romstage. BUG=b:379008996 BRANCH=none TEST=Boot up pass 3200 LPDDR5 chan0(x16) rank0: memory test pass 3200 LPDDR5 chan0(x16) rank1: memory test pass 3200 LPDDR5 chan1(x16) rank0: memory test pass 3200 LPDDR5 chan1(x16) rank1: memory test pass Signed-off-by: Mike Lin <mike.lin(a)mediatek.corp-partner.google.com> Change-Id: Iabdcabefc77a262c548019e801daf5b269eaa97a --- M src/mainboard/google/skywalker/romstage.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/87038/1 diff --git a/src/mainboard/google/skywalker/romstage.c b/src/mainboard/google/skywalker/romstage.c index 7758dfa..3becd91 100644 --- a/src/mainboard/google/skywalker/romstage.c +++ b/src/mainboard/google/skywalker/romstage.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ #include <arch/stages.h> +#include <soc/emi.h> void platform_romstage_main(void) { /* TODO: add romstage main function */ + mtk_dram_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/87038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabdcabefc77a262c548019e801daf5b269eaa97a Gerrit-Change-Number: 87038 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8189: Add DRAM calibration support
by Vince Liu (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Vince Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87037?usp=email ) Change subject: soc/mediatek/mt8189: Add DRAM calibration support ...................................................................... soc/mediatek/mt8189: Add DRAM calibration support Add DRAM calibration support for mt8189. DRAM parameters and related constants are added in dramc_param.h and dramc_soc.h. The common emi.c can be reused for MT8189 as well, so remove the duplicate mt8189/emi.{c,h}. Enable MEDIATEK_DRAM_BLOB_FAST_INIT to allow running DRAM fast calibration via the DRAM blob. BUG=b:379008996 BRANCH=none TEST=Boot up pass and see log 3200 LPDDR5 chan0(x16) rank0: memory test pass 3200 LPDDR5 chan0(x16) rank1: memory test pass 3200 LPDDR5 chan1(x16) rank0: memory test pass 3200 LPDDR5 chan1(x16) rank1: memory test pass Signed-off-by: Mike Lin <mike.lin(a)mediatek.corp-partner.google.com> Change-Id: Ia6f6e5afc1f4a2e919243bda0799712cd7b4d01f --- M src/soc/mediatek/mt8189/Kconfig M src/soc/mediatek/mt8189/Makefile.mk D src/soc/mediatek/mt8189/emi.c A src/soc/mediatek/mt8189/include/soc/dramc_param.h A src/soc/mediatek/mt8189/include/soc/dramc_soc.h D src/soc/mediatek/mt8189/include/soc/emi.h 6 files changed, 202 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/87037/1 diff --git a/src/soc/mediatek/mt8189/Kconfig b/src/soc/mediatek/mt8189/Kconfig index 512ae54..bf55327 100644 --- a/src/soc/mediatek/mt8189/Kconfig +++ b/src/soc/mediatek/mt8189/Kconfig @@ -8,6 +8,9 @@ select ARCH_ROMSTAGE_ARMV8_64 select ARCH_RAMSTAGE_ARMV8_64 select HAVE_UART_SPECIAL + select CACHE_MRC_SETTINGS + select MEDIATEK_DRAM_BLOB_FAST_INIT + select USE_CBMEM_DRAM_INFO select SOC_MEDIATEK_COMMON select FLASH_DUAL_IO_READ select ARM64_USE_ARCH_TIMER diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk index 6774f52..bdee1fb 100644 --- a/src/soc/mediatek/mt8189/Makefile.mk +++ b/src/soc/mediatek/mt8189/Makefile.mk @@ -13,15 +13,30 @@ bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c romstage-y += ../common/cbmem.c -romstage-y += emi.c +romstage-y += ../common/dram_init.c +romstage-y += ../common/dramc_param.c +romstage-y += ../common/emi.c +romstage-y += ../common/memory.c ../common/memory_test.c +romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c -ramstage-y += emi.c +ramstage-y += ../common/emi.c +ramstage-y += ../common/memory.c +ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-y += soc.c ramstage-y += ../common/usb.c usb.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8189/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include +MT8189_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8189 + +DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram +$(DRAM_CBFS)-file := $(MT8189_BLOB_DIR)/dram.elf +$(DRAM_CBFS)-type := stage +$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +ifneq ($(wildcard $($(DRAM_CBFS)-file)),) + cbfs-files-y += $(DRAM_CBFS) +endif $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin ./util/mtkheader/gen-bl-img.py mt8189 sf $< $@ diff --git a/src/soc/mediatek/mt8189/emi.c b/src/soc/mediatek/mt8189/emi.c deleted file mode 100644 index 8b933e8..0000000 --- a/src/soc/mediatek/mt8189/emi.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ - -#include <soc/emi.h> - -size_t sdram_size(void) -{ - return (size_t)4 * GiB; -} diff --git a/src/soc/mediatek/mt8189/include/soc/dramc_param.h b/src/soc/mediatek/mt8189/include/soc/dramc_param.h new file mode 100644 index 0000000..916b037 --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/dramc_param.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8189_DRAMC_PARAM_H__ +#define __SOC_MEDIATEK_MT8189_DRAMC_PARAM_H__ + +/* + * NOTE: This file is shared between coreboot and dram blob. Any change in this + * file should be synced to the other repository. + */ + +#include <soc/dramc_param_common.h> +#include <soc/dramc_soc.h> +#include <stdint.h> +#include <sys/types.h> + +#define DRAMC_PARAM_HEADER_VERSION 1 +#define CATRAINING_NUM_LP5 7 + +struct sdram_params { + /* rank, cbt */ + u32 rank_num; + u32 dram_cbt_mode; + + u16 delay_cell_timex100; + u8 u18ph_dly[CHANNEL_MAX]; + + /* duty */ + s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX]; + s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP5]; + s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP5]; + s8 duty_mck16x_delay[CHANNEL_MAX][DQS_NUMBER_LP5 + 1]; + s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP5]; + s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP5]; + + /* cbt */ + u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX]; + u8 cbt_final_range[CHANNEL_MAX][RANK_MAX]; + s16 s2CBTCAWindow_first_pass_Save[CHANNEL_MAX][RANK_MAX][CATRAINING_NUM_LP5]; + s16 s2CBTCAWindow_last_pass_Save[CHANNEL_MAX][RANK_MAX][CATRAINING_NUM_LP5]; + s16 cbt_cmd_dly[CHANNEL_MAX]; + u16 cbt_cs_dly[CHANNEL_MAX]; + u8 cbt_ca_prebit_dly[CHANNEL_MAX][DQS_BIT_NUMBER]; + + /* write leveling */ + u8 wr_level_pi[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 wr_level_dly[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + + /* gating */ + u8 gating_UI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 gating_PI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 wck2dqo_cnt[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + + /* rx input buffer */ + s8 dq_offc[CHANNEL_MAX][DQ_DATA_WIDTH_LP5]; + s8 dqm_offc[CHANNEL_MAX][DQS_NUMBER_LP5]; + + /* tx perbit */ + u16 tx_window_vref[CHANNEL_MAX][RANK_MAX]; + u16 tx_window_vref_range[CHANNEL_MAX][RANK_MAX]; + s16 u1Txfirst_pass_Save[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + s16 u1Txlast_pass_Save[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + u16 tx_dq[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 tx_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 tx_dqm_only[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 tx_perbit_dlyline[CHANNEL_MAX][RANK_MAX][EXT_DQ_DATA_WIDTH]; + u16 wck2dqi_cnt0[CHANNEL_MAX][RANK_MAX]; + u16 wck2dqi_cnt1[CHANNEL_MAX][RANK_MAX]; + + /* rx datlat */ + u8 rx_datlat[CHANNEL_MAX]; + + /* rx perbit */ + u8 rx_best_vref_perbyte[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + //u8 rx_best_vref_perbit[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + s16 u1Rxfirst_pass_Save[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + s16 u1Rxlast_pass_Save[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + u16 rx_perbit_dqs[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 rx_perbit_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 rx_perbit_dq[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + s16 rx_perbit_begin; + + /* dvs */ + u8 dvs_delay[CHANNEL_MAX][DQS_NUMBER_LP5]; + + u8 perbit_dcc[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + + /* dcm */ + u8 best_u[CHANNEL_MAX][RANK_MAX]; + u8 best_l[CHANNEL_MAX][RANK_MAX]; + + /* Read DCA */ + s8 rdca_u[CHANNEL_MAX][RANK_MAX]; + s8 rdca_l[CHANNEL_MAX][RANK_MAX]; + + /* RDCC */ + s8 rdcc[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + + /* tx oe */ + u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 tx_oe_offset[CHANNEL_MAX][RANK_MAX]; +}; + +struct dramc_data { + struct ddr_base_info ddr_info; + struct sdram_params freq_params[DRAM_DFS_SHU_MAX]; +}; + +struct dramc_param { + struct dramc_param_header header; + void (*do_putc)(unsigned char c); + struct dramc_data dramc_datas; +}; + +struct dramc_param *get_dramc_param_from_blob(void *blob); +void dump_param_header(const void *blob); +int validate_dramc_param(const void *blob); +int is_valid_dramc_param(const void *blob); +int initialize_dramc_param(void *blob); + +#endif /* __SOC_MEDIATEK_MT8189_DRAMC_PARAM_H__ */ diff --git a/src/soc/mediatek/mt8189/include/soc/dramc_soc.h b/src/soc/mediatek/mt8189/include/soc/dramc_soc.h new file mode 100644 index 0000000..0035a90 --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/dramc_soc.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DRAMC_SOC_H__ +#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DRAMC_SOC_H__ + +#include <soc/dramc_soc_common.h> +#include <stdint.h> + +typedef enum { + CHANNEL_A = 0, + CHANNEL_B, + CHANNEL_MAX, +} DRAM_CHANNEL_T; + +typedef enum { + RANK_0 = 0, + RANK_1, + RANK_MAX, +} DRAM_RANK_T; + +typedef enum { + SRAM_SHU0 = 0, + SRAM_SHU1, + SRAM_SHU2, + SRAM_SHU3, + SRAM_SHU4, + DRAM_DFS_SRAM_MAX +} DRAM_DFS_SRAM_SHU_T; /* DRAM SRAM RG type */ + +typedef enum { + DRVP = 0, + DRVN, + ODTN, + IMP_DRV_MAX, +} DRAM_IMP_DRV_T; + +typedef enum { + TYPE_INVALID = 0, + TYPE_DDR1, + TYPE_DDR2, + TYPE_DDR3, + TYPE_DDR4, + TYPE_DDR5, + TYPE_LPDDR2, + TYPE_LPDDR3, + TYPE_PCDDR3, + TYPE_LPDDR4, + TYPE_LPDDR4X, + TYPE_LPDDR4P, + TYPE_LPDDR5, + TYPE_LPDDR5X, + TYPE_MAX, +} DRAM_DRAM_TYPE_T; + +#define DRAM_DFS_SHU_MAX DRAM_DFS_SRAM_MAX +#define DQS_NUMBER_LP5 2 +#define DQ_DATA_WIDTH_LP5 16 +#define EXT_DQ_DATA_WIDTH 18 + +#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DRAMC_SOC_H__ */ diff --git a/src/soc/mediatek/mt8189/include/soc/emi.h b/src/soc/mediatek/mt8189/include/soc/emi.h deleted file mode 100644 index 9f66a7f..0000000 --- a/src/soc/mediatek/mt8189/include/soc/emi.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ - -#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EMI_H__ -#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EMI_H__ - -#include <stddef.h> - -size_t sdram_size(void); - -#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EMI_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87037?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6f6e5afc1f4a2e919243bda0799712cd7b4d01f Gerrit-Change-Number: 87037 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Move TX TRACKING from MT8196 to common folder
by Vince Liu (Code Review) 28 Mar '25

28 Mar '25

Vince Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87036?usp=email ) Change subject: soc/mediatek/mt8196: Move TX TRACKING from MT8196 to common folder ...................................................................... soc/mediatek/mt8196: Move TX TRACKING from MT8196 to common folder The configuration method of the served DRAM buffer used for HW TX TRACING on MT8196 is also applicable to other SoCs, such as MT8189. To facilitate reuse, we have moved the relevant files to the common directory. BUG=b:379008996 BRANCH=none TEST=Reserve memory ok Firmware shows the following log with 12GB DDR board: 00000001ffff0000-00000001ffffffff: RESERVED 000000037fff0000-000000037fffffff: RESERVED Change-Id: I3fdd9d2f7ab1bbdcc097510556929da2134f7d95 Signed-off-by: Mike Lin <mike.lin(a)mediatek.corp-partner.google.com> --- R src/soc/mediatek/common/dramc_info.c A src/soc/mediatek/common/include/soc/dramc_info.h M src/soc/mediatek/mt8196/Makefile.mk D src/soc/mediatek/mt8196/include/soc/dramc_info.h 4 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/87036/1 diff --git a/src/soc/mediatek/mt8196/dramc_info.c b/src/soc/mediatek/common/dramc_info.c similarity index 100% rename from src/soc/mediatek/mt8196/dramc_info.c rename to src/soc/mediatek/common/dramc_info.c diff --git a/src/soc/mediatek/common/include/soc/dramc_info.h b/src/soc/mediatek/common/include/soc/dramc_info.h new file mode 100644 index 0000000..a0be640 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/dramc_info.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_COMMON_DRAMC_INFO_H__ +#define __SOC_MEDIATEK_COMMON_DRAMC_INFO_H__ + +void reserve_buffer_for_dramc(void); + +#endif /* __SOC_MEDIATEK_COMMON_DRAMC_INFO_H__ */ diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 1793104..fa0e3fe 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -60,7 +60,7 @@ ramstage-y += ../common/dpm_v2.c ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_hal_common.c ramstage-y += dptx.c dptx_hal.c dp_intf.c -ramstage-y += dramc_info.c +ramstage-y += ../common/dramc_info.c ramstage-y += ../common/early_init.c ramstage-y += ../common/emi.c ramstage-y += gpueb.c diff --git a/src/soc/mediatek/mt8196/include/soc/dramc_info.h b/src/soc/mediatek/mt8196/include/soc/dramc_info.h deleted file mode 100644 index ccc7ff9..0000000 --- a/src/soc/mediatek/mt8196/include/soc/dramc_info.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __SOC_MEDIATEK_MT8196_DRAMC_INFO_H__ -#define __SOC_MEDIATEK_MT8196_DRAMC_INFO_H__ - -void reserve_buffer_for_dramc(void); - -#endif /* __SOC_MEDIATEK_MT8196_DRAMC_INFO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87036?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fdd9d2f7ab1bbdcc097510556929da2134f7d95 Gerrit-Change-Number: 87036 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com>

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[M] Change in coreboot[main]: mb/google/fatcat: Rationalize Wi-Fi and Bluetooth combinations
by Jayvik Desai (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Cliff Huang, Jérémy Compostella, Pranava Y N, Wonkyu Kim. Jayvik Desai has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85662?usp=email ) Change subject: mb/google/fatcat: Rationalize Wi-Fi and Bluetooth combinations ...................................................................... Patch Set 18: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85662?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida95d1898d24898880de567db7c0ac8ac053eeaa Gerrit-Change-Number: 85662 Gerrit-PatchSet: 18 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Ben Kao <ben.kao(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 28 Mar 2025 06:21:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/brya: Enable use_gpio_for_status for touchscreen
by Momoko Hattori (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Momoko Hattori, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Sam McNally, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86876?usp=email to look at the new patch set (#5). Change subject: mb/google/brya: Enable use_gpio_for_status for touchscreen ...................................................................... mb/google/brya: Enable use_gpio_for_status for touchscreen The _STA method of touchscreen's power resource currently always returns true. This causes the touchscreen to be powered on by the kernel in a boot critical path (in acpi_bus_init_power) and block the boot for a while due to the long (~300ms depending on variants) sleeps in the _ON method of the power resource. To prevent it, enable use_gpio_for_status so that the implementation of _STA returns the touchscreen's actual power state and the kernel powers it on in another place that doesn't block boot. The similar change has already been made to mb/google/brya/var/redrix in commit d0367e38a9e5 ("mb/google/brya/var/redrix: Enable use_gpio_for_status for touchscreen") (CB:86749). This change applies it to all the other non-4es brya variants with touchscreen. BUG=b:397355818 TEST=Dump SSDT and check that the _STA method of touchscreen (i2c3) PowerResource doesn't always return true. TEST=Check that touchscreen works with the change. TEST=Check that kernel sleep during ACPI initialization is removed by checking the timestamps of 'New power resource' logs from ACPI in /var/log/messages. TEST=(Tested above on crota) Change-Id: I068faa97089ce0011727325ffc868450572bdf58 Signed-off-by: Momoko Hattori <momohatt(a)google.com> --- M src/mainboard/google/brya/variants/anahera/overridetree.cb M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/crota/overridetree.cb M src/mainboard/google/brya/variants/dochi/overridetree.cb M src/mainboard/google/brya/variants/felwinter/overridetree.cb M src/mainboard/google/brya/variants/gaelin/overridetree.cb M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/kano/overridetree.cb M src/mainboard/google/brya/variants/marasov/overridetree.cb M src/mainboard/google/brya/variants/mithrax/overridetree.cb M src/mainboard/google/brya/variants/nova/overridetree.cb M src/mainboard/google/brya/variants/omnigul/overridetree.cb M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/skolas/overridetree.cb M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taniks/overridetree.cb M src/mainboard/google/brya/variants/vell/overridetree.cb M src/mainboard/google/brya/variants/volmar/overridetree.cb M src/mainboard/google/brya/variants/zydron/overridetree.cb 19 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/86876/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/86876?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I068faa97089ce0011727325ffc868450572bdf58 Gerrit-Change-Number: 86876 Gerrit-PatchSet: 5 Gerrit-Owner: Momoko Hattori <momohatt(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Momoko Hattori <momohatt(a)google.com>

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Bill XIE (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Angel Pons, Keith Hui, Nicholas Chin. Bill XIE has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 7: (1 comment) File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c: https://review.coreboot.org/c/coreboot/+/85413/comment/9eda63b8_9a833949?us… : PS7, Line 104: 0x40 > Sorry for the inaccuracy. […] Sorry for the inaccuracy again. gpio5 |= 0x40 works well. The malfunction above applies to gpio5 |= 0x20 when (force_asm1061 || (detect_pcie & PCIEX1_2_NOT_PRESENT)). -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 7 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Mar 2025 06:16:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[M] Change in coreboot[main]: mb/google/nissa: Enable use_gpio_for_status for touchscreen
by Momoko Hattori (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Dinesh Gehlot, Momoko Hattori, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Sam McNally, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86877?usp=email to look at the new patch set (#8). Change subject: mb/google/nissa: Enable use_gpio_for_status for touchscreen ...................................................................... mb/google/nissa: Enable use_gpio_for_status for touchscreen The _STA method of touchscreen's power resource currently always returns true. This causes the touchscreen to be powered on by the kernel in a boot critical path (in acpi_bus_init_power) and block the boot for a while due to the long (~300ms depending on variants) sleeps in the _ON method of the power resource. To prevent it, enable use_gpio_for_status so that the implementation of _STA returns the touchscreen's actual power state and the kernel powers it on in another place that doesn't block boot. The similar change has already been made to mb/google/brya/var/redrix in commit d0367e38a9e5 ("mb/google/brya/var/redrix: Enable use_gpio_for_status for touchscreen") (CB:86749). This change applies it to all nissa variants with touchscreen except for pujjoniru, whose touchscreen does not have has_power_resource option enabled. BUG=b:397355818 TEST=Dump SSDT and check that the _STA method of touchscreen (i2c1) PowerResource doesn't always return true. TEST=Check that touchscreen works with the change. TEST=Check that kernel sleep during ACPI initialization is removed by checking the timestamps of 'New power resource' logs from ACPI in /var/log/messages and/or getting perfetto boot-time trace. TEST=(Tested the above on gothrax and riven) Change-Id: I126e0b2cece6b3fb9a750a908e6cc9663b7f37c9 Signed-off-by: Momoko Hattori <momohatt(a)google.com> --- M src/mainboard/google/brya/variants/anraggar/overridetree.cb M src/mainboard/google/brya/variants/craask/overridetree.cb M src/mainboard/google/brya/variants/craaskov/overridetree.cb M src/mainboard/google/brya/variants/glassway/overridetree.cb M src/mainboard/google/brya/variants/gothrax/overridetree.cb M src/mainboard/google/brya/variants/guren/overridetree.cb M src/mainboard/google/brya/variants/joxer/overridetree.cb M src/mainboard/google/brya/variants/meliks/overridetree.cb M src/mainboard/google/brya/variants/nereid/overridetree.cb M src/mainboard/google/brya/variants/nivviks/overridetree.cb M src/mainboard/google/brya/variants/orisa/overridetree.cb M src/mainboard/google/brya/variants/pirrha/overridetree.cb M src/mainboard/google/brya/variants/pujjo/overridetree.cb M src/mainboard/google/brya/variants/pujjoga/overridetree.cb M src/mainboard/google/brya/variants/quandiso/overridetree.cb M src/mainboard/google/brya/variants/riven/overridetree.cb M src/mainboard/google/brya/variants/rull/overridetree.cb M src/mainboard/google/brya/variants/sundance/overridetree.cb M src/mainboard/google/brya/variants/teliks/overridetree.cb M src/mainboard/google/brya/variants/telith/overridetree.cb M src/mainboard/google/brya/variants/uldren/overridetree.cb M src/mainboard/google/brya/variants/xivu/overridetree.cb M src/mainboard/google/brya/variants/yaviks/overridetree.cb M src/mainboard/google/brya/variants/yavilla/overridetree.cb 24 files changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/86877/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/86877?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I126e0b2cece6b3fb9a750a908e6cc9663b7f37c9 Gerrit-Change-Number: 86877 Gerrit-PatchSet: 8 Gerrit-Owner: Momoko Hattori <momohatt(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Momoko Hattori <momohatt(a)google.com>

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[XS] Change in coreboot[main]: mb/google/rex: Enable use_gpio_for_status for touchscreen
by Momoko Hattori (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub "Kuba" Czapiga, Momoko Hattori, Paul Menzel, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Jakub "Kuba" Czapiga, Kapil Porwal, Sam McNally, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87001?usp=email to look at the new patch set (#7). Change subject: mb/google/rex: Enable use_gpio_for_status for touchscreen ...................................................................... mb/google/rex: Enable use_gpio_for_status for touchscreen The _STA method of touchscreen's power resource currently always returns true. This causes the touchscreen to be powered on by the kernel in a boot critical path (in acpi_bus_init_power) and block the boot for a while due to the long (~300ms depending on variants) sleeps in the _ON method of the power resource. To prevent it, enable use_gpio_for_status so that the implementation of _STA returns the touchscreen's actual power state and the kernel powers it on in another place that doesn't block boot. The similar change has already been made to mb/google/brya/var/redrix in commit d0367e38a9e5 ("mb/google/brya/var/redrix: Enable use_gpio_for_status for touchscreen") (CB:86749). This change applies it to all rex variants with touchscreen. BUG=b:397355818 TEST=Dump SSDT and check that the _STA method of touchscreen (i2c1) PowerResource doesn't always return true. TEST=Check that touchscreen works with the change. TEST=Check that kernel sleep during ACPI initialization is removed by checking the timestamps of 'New power resource' logs from ACPI in /var/log/messages. TEST=(Tested above on karis) Change-Id: Ibe7681884dc3edfb98c7c179b1af2063e35c4b46 Signed-off-by: Momoko Hattori <momohatt(a)google.com> --- M src/mainboard/google/rex/variants/kanix/overridetree.cb M src/mainboard/google/rex/variants/karis/overridetree.cb M src/mainboard/google/rex/variants/rex0/overridetree.cb M src/mainboard/google/rex/variants/screebo/overridetree.cb 4 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/87001/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/87001?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibe7681884dc3edfb98c7c179b1af2063e35c4b46 Gerrit-Change-Number: 87001 Gerrit-PatchSet: 7 Gerrit-Owner: Momoko Hattori <momohatt(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Momoko Hattori <momohatt(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[XS] Change in coreboot[main]: mb/google/fatcat/var/francka: Update HDA verb tables
by Jayvik Desai (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Ian Feng, Kapil Porwal. Jayvik Desai has posted comments on this change by Ian Feng. ( https://review.coreboot.org/c/coreboot/+/87034?usp=email ) Change subject: mb/google/fatcat/var/francka: Update HDA verb tables ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2b9fbd3d95cac145a4c64d9f07001d81880a0e5 Gerrit-Change-Number: 87034 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Terry Cheong <htcheong(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Fri, 28 Mar 2025 06:14:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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