coreboot-gerrit March 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING
by Gareth Yu (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Gareth Yu, Jayvik Desai, Kapil Porwal, Lawrence Chang, Nick Vaccaro, Paul Menzel, SH Kim, Simon Yang, Subrata Banik. Gareth Yu has posted comments on this change by Lawrence Chang. ( https://review.coreboot.org/c/coreboot/+/86838?usp=email ) Change subject: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING ...................................................................... Patch Set 18: (1 comment) File src/mainboard/google/brya/variants/meliks/ramstage.c: https://review.coreboot.org/c/coreboot/+/86838/comment/859ebf33_3ea5fe76?us… : PS17, Line 20: 0xf > > Unfortunately, ```mainboard_silicon_init_params``` is too early to use igd bar. […] Yes, hardcoding the MMIO address is possible. The reason is we need to clear the same system memory which is used by GFX before warm boot. However, I have found 2 possible addresses are used for TWL, 0x81000000 or 0xAF000000. It means that the address can be changed according to different PCI devices. Even only for this project, I can't say the PCI devices are consistent until its EOL. Thought? -- To view, visit https://review.coreboot.org/c/coreboot/+/86838?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7857c4f71fc7d1d0c5069a462bdd70c8dbb78179 Gerrit-Change-Number: 86838 Gerrit-PatchSet: 18 Gerrit-Owner: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Gareth Yu <gareth.yu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Gareth Yu <gareth.yu(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Gareth Yu <gareth.yu(a)intel.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 28 Mar 2025 12:15:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Gareth Yu <gareth.yu(a)intel.com>

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[S] Change in coreboot[main]: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING
by Subrata Banik (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Gareth Yu, Gareth Yu, Jayvik Desai, Kapil Porwal, Lawrence Chang, Nick Vaccaro, Paul Menzel, SH Kim, Simon Yang. Subrata Banik has posted comments on this change by Lawrence Chang. ( https://review.coreboot.org/c/coreboot/+/86838?usp=email ) Change subject: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING ...................................................................... Patch Set 18: (1 comment) File src/mainboard/google/brya/variants/meliks/ramstage.c: https://review.coreboot.org/c/coreboot/+/86838/comment/b2018d60_dd7768eb?us… : PS17, Line 20: 0xf > Unfortunately, ```mainboard_silicon_init_params``` is too early to use igd bar. Hence we need to back to patch 18. unable to follow, you can always assign some temp bar to program a register -- To view, visit https://review.coreboot.org/c/coreboot/+/86838?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7857c4f71fc7d1d0c5069a462bdd70c8dbb78179 Gerrit-Change-Number: 86838 Gerrit-PatchSet: 18 Gerrit-Owner: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Gareth Yu <gareth.yu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Gareth Yu <gareth.yu(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Gareth Yu <gareth.yu(a)intel.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Gareth Yu <gareth.yu(a)intel.com> Gerrit-Attention: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 28 Mar 2025 11:44:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Gareth Yu <gareth.yu(a)intel.com>

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[S] Change in coreboot[main]: arch/x86/cpu: Add helper function to compute cache
by Naresh Solanki (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Andy Ebrahiem, Angel Pons, Felix Held, Jincheng Li, Jérémy Compostella, Maximilian Brune, Patrick Rudolph, Shuo Liu. Naresh Solanki has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85638?usp=email ) Change subject: arch/x86/cpu: Add helper function to compute cache ...................................................................... Patch Set 6: (1 comment) File src/arch/x86/cpu_common.c: https://review.coreboot.org/c/coreboot/+/85638/comment/1b972ba3_99204f10?us… : PS6, Line 240: bool fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info) : { : if (!info) : return false; : : // Check if SoC specific implementation provides cache info. : bool ret = soc_fill_cpu_cache_info(level, info); : if (ret) : return ret; : : return x86_get_cpu_cache_info(level, info); : } > Hmmm, true. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449 Gerrit-Change-Number: 85638 Gerrit-PatchSet: 6 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Mar 2025 11:43:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com>

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[S] Change in coreboot[main]: arch/x86/cpu: Add helper function to compute cache
by Naresh Solanki (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Andy Ebrahiem, Angel Pons, Felix Held, Jincheng Li, Jérémy Compostella, Maximilian Brune, Naresh Solanki, Patrick Rudolph, Shuo Liu. Hello Angel Pons, Felix Held, Jincheng Li, Jérémy Compostella, Maximilian Brune, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85638?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins) Change subject: arch/x86/cpu: Add helper function to compute cache ...................................................................... arch/x86/cpu: Add helper function to compute cache Consider special requirements for computing cache size in certain SoCs, such as `soc/amd/glinda`. Use the helper function to implement SoC-specific logic for computing cache size. Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/arch/x86/cpu_common.c M src/arch/x86/include/arch/cpu.h 2 files changed, 24 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/85638/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449 Gerrit-Change-Number: 85638 Gerrit-PatchSet: 7 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: soc/amd/glinda/cpu: Compute total L3 cache size
by Naresh Solanki (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Angel Pons, Naresh Solanki. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85640?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins) Change subject: soc/amd/glinda/cpu: Compute total L3 cache size ...................................................................... soc/amd/glinda/cpu: Compute total L3 cache size Glinda SoC has multiple L3 caches, each identified by a unique cache UID. Each core is associated with a specific L3 cache, which can be determined based on the CPU core ID. The default implementation (x86_get_cpu_cache_info) retrieves cache information only for the current core and assumes that the same L3 cache is shared across all cores. To accurately determine the total L3 cache size, this update: 1. Retrieves L3 cache information for each CPU core. 2. Identifies the unique cache ID associated with each core. 3. Aggregates cache sizes for all unique cache IDs to compute the total L3 cache size. TEST=Build for Glinda SoC, with L3 cache = 16MB + 8MB. Ran command 'dmidecode -t 7' & verified L3 cache is 24MB. Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/soc/amd/glinda/cpu.c 1 file changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/85640/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 9 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com>

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[S] Change in coreboot[main]: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING
by Gareth Yu (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Gareth Yu, Jayvik Desai, Kapil Porwal, Lawrence Chang, Nick Vaccaro, Paul Menzel, SH Kim, Simon Yang, Subrata Banik. Gareth Yu has posted comments on this change by Lawrence Chang. ( https://review.coreboot.org/c/coreboot/+/86838?usp=email ) Change subject: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING ...................................................................... Patch Set 18: (1 comment) File src/mainboard/google/brya/variants/meliks/ramstage.c: https://review.coreboot.org/c/coreboot/+/86838/comment/429581aa_337c7c6d?us… : PS17, Line 20: 0xf > Looks good. Unfortunately, ```mainboard_silicon_init_params``` is too early to use igd bar. Hence we need to back to patch 18. -- To view, visit https://review.coreboot.org/c/coreboot/+/86838?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7857c4f71fc7d1d0c5069a462bdd70c8dbb78179 Gerrit-Change-Number: 86838 Gerrit-PatchSet: 18 Gerrit-Owner: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Gareth Yu <gareth.yu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Gareth Yu <gareth.yu(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Gareth Yu <gareth.yu(a)intel.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 28 Mar 2025 10:37:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Gareth Yu <gareth.yu(a)intel.com>

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[M] Change in coreboot[main]: mb/google/brya: Create epic variant
by Yunlong Jia (Code Review) 28 Mar '25

28 Mar '25

Yunlong Jia has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87041?usp=email ) Change subject: mb/google/brya: Create epic variant ...................................................................... mb/google/brya: Create epic variant Create the epic variant of the nissa reference board by copying the template files to a new directory named for the variant. This variant is a Nirul project,support TWL devices and select BOARD_GOOGLE_BASEBOARD_NISSA. BUG=404301972 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_EPIC Signed-off-by: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Change-Id: I09e5f3c28b95ae8ef318b7af1dd8634279345ce0 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/epic/include/variant/ec.h A src/mainboard/google/brya/variants/epic/include/variant/gpio.h A src/mainboard/google/brya/variants/epic/memory/Makefile.mk A src/mainboard/google/brya/variants/epic/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/epic/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/epic/overridetree.cb 8 files changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/87041/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 9808a32..c22c4eb 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -748,6 +748,14 @@ select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_RAPTORLAKE +config BOARD_GOOGLE_EPIC + select BOARD_GOOGLE_BASEBOARD_NISSA + select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_GENESYSLOGIC_GL9750 + select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER + select HAVE_WWAN_POWER_SEQUENCE + if BOARD_GOOGLE_BRYA_COMMON config BASEBOARD_DIR @@ -846,6 +854,7 @@ default 0x0 if BOARD_GOOGLE_TELITH default 0x0 if BOARD_GOOGLE_PUJJOGATWIN default 0x0 if BOARD_GOOGLE_MELIKS + default 0x0 if BOARD_GOOGLE_EPIC config DRIVER_TPM_I2C_ADDR hex @@ -930,6 +939,7 @@ default 13 if BOARD_GOOGLE_TELITH default 13 if BOARD_GOOGLE_PUJJOGATWIN default 13 if BOARD_GOOGLE_MELIKS + default 13 if BOARD_GOOGLE_EPIC config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree_pujjogatwin.cb" if BOARD_GOOGLE_PUJJOGATWIN @@ -1022,6 +1032,7 @@ default "Telith" if BOARD_GOOGLE_TELITH default "Pujjogatwin" if BOARD_GOOGLE_PUJJOGATWIN default "Meliks" if BOARD_GOOGLE_MELIKS + default "Epic" if BOARD_GOOGLE_EPIC config VARIANT_DIR default "agah" if BOARD_GOOGLE_AGAH @@ -1099,6 +1110,7 @@ default "telith" if BOARD_GOOGLE_TELITH default "pujjoga" if BOARD_GOOGLE_PUJJOGATWIN default "meliks" if BOARD_GOOGLE_MELIKS + default "epic" if BOARD_GOOGLE_EPIC config VBOOT select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO) diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index ac4c262..5431cba 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -226,3 +226,6 @@ config BOARD_GOOGLE_MELIKS bool "-> Meliks" + +config BOARD_GOOGLE_EPIC + bool "-> Epic" diff --git a/src/mainboard/google/brya/variants/epic/include/variant/ec.h b/src/mainboard/google/brya/variants/epic/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/epic/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/epic/include/variant/gpio.h b/src/mainboard/google/brya/variants/epic/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/epic/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/epic/memory/Makefile.mk b/src/mainboard/google/brya/variants/epic/memory/Makefile.mk new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/brya/variants/epic/memory/Makefile.mk @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/epic/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/epic/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/epic/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/epic/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/epic/memory/mem_parts_used.txt new file mode 100644 index 0000000..2499005 --- /dev/null +++ b/src/mainboard/google/brya/variants/epic/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/epic/overridetree.cb b/src/mainboard/google/brya/variants/epic/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/epic/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/87041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09e5f3c28b95ae8ef318b7af1dd8634279345ce0 Gerrit-Change-Number: 87041 Gerrit-PatchSet: 1 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8189: Add usb host support
by Yidi Lin (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Hung-Te Lin, Liu Liu, Paul Menzel, Vince Liu, Yu-Ping Wu. Yidi Lin has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87021?usp=email ) Change subject: soc/mediatek/mt8189: Add usb host support ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/mt8189/include/soc/usb.h: https://review.coreboot.org/c/coreboot/+/87021/comment/312d406e_68289a6f?us… : PS1, Line 22: check_member(ssusb_sif_port, u3phyd, 0x600); : check_member(ssusb_sif_port, u3phya, 0x800); : check_member(ssusb_sif_port, u3phya_da, 0x900); : check_member(ssusb_sif_port, reserved2, 0xa00); > Should macros be defined for the values? Those are offset value. I don't think it makes sense to define those values. -- To view, visit https://review.coreboot.org/c/coreboot/+/87021?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f1b4b3eb178cb9a110b97a2763c8cff5cdf0ddd Gerrit-Change-Number: 87021 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Liu Liu <ot_liu.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liu Liu <ot_liu.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 28 Mar 2025 08:56:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: soc/mediatek/mt8189: Add usb host support
by Paul Menzel (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Hung-Te Lin, Liu Liu, Vince Liu, Yu-Ping Wu. Paul Menzel has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87021?usp=email ) Change subject: soc/mediatek/mt8189: Add usb host support ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/87021/comment/5f403f76_1afd9471?us… : PS1, Line 9: Add usb host function support. Please elaborate, what needs to be done for it. -- To view, visit https://review.coreboot.org/c/coreboot/+/87021?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f1b4b3eb178cb9a110b97a2763c8cff5cdf0ddd Gerrit-Change-Number: 87021 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Liu Liu <ot_liu.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liu Liu <ot_liu.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 28 Mar 2025 08:33:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[M] Change in coreboot[main]: soc/mediatek/mt8189: Add usb host support
by Paul Menzel (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Hung-Te Lin, Liu Liu, Vince Liu, Yu-Ping Wu. Paul Menzel has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87021?usp=email ) Change subject: soc/mediatek/mt8189: Add usb host support ...................................................................... Patch Set 1: (2 comments) File src/soc/mediatek/mt8189/include/soc/addressmap.h: https://review.coreboot.org/c/coreboot/+/87021/comment/abcd8dd8_332c9465?us… : PS1, Line 35: SSUSB_SIF_BASE = IO_PHYS + 0x01B00300, Please note in the commit message, why these values were changed. File src/soc/mediatek/mt8189/include/soc/usb.h: https://review.coreboot.org/c/coreboot/+/87021/comment/03c1e764_150a9fcd?us… : PS1, Line 22: check_member(ssusb_sif_port, u3phyd, 0x600); : check_member(ssusb_sif_port, u3phya, 0x800); : check_member(ssusb_sif_port, u3phya_da, 0x900); : check_member(ssusb_sif_port, reserved2, 0xa00); Should macros be defined for the values? -- To view, visit https://review.coreboot.org/c/coreboot/+/87021?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f1b4b3eb178cb9a110b97a2763c8cff5cdf0ddd Gerrit-Change-Number: 87021 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Liu Liu <ot_liu.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liu Liu <ot_liu.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 28 Mar 2025 08:32:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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