coreboot-gerrit March 2025

coreboot-gerrit@coreboot.org

1 participants
2811 discussions

[M] Change in coreboot[main]: Documentation/mainboard/lenovo: Add ThinkCentre M700/M900 Tiny
by Michał Kopeć (Code Review) 29 Mar '25

29 Mar '25

Attention is currently required from: Krystian Hebel, Maciej Pijanowski, Michał Żygowski. Hello Krystian Hebel, Maciej Pijanowski, Michał Żygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87044?usp=email to look at the new patch set (#2). Change subject: Documentation/mainboard/lenovo: Add ThinkCentre M700/M900 Tiny ...................................................................... Documentation/mainboard/lenovo: Add ThinkCentre M700/M900 Tiny Heavily based on M710s documentation. Change-Id: I8c3860ba6254919769082c9ed749f8bb287a5f5e Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/thinkcentre_m900_tiny.md A Documentation/mainboard/lenovo/thinkcentre_m900_tiny_spi_location.jpg 3 files changed, 90 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/87044/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c3860ba6254919769082c9ed749f8bb287a5f5e Gerrit-Change-Number: 87044 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com>

1 0

[M] Change in coreboot[main]: Documentation/mainboard/lenovo: Add ThinkCentre M700/M900 Tiny
by Michał Kopeć (Code Review) 29 Mar '25

29 Mar '25

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87044?usp=email ) Change subject: Documentation/mainboard/lenovo: Add ThinkCentre M700/M900 Tiny ...................................................................... Documentation/mainboard/lenovo: Add ThinkCentre M700/M900 Tiny Heavily based on M710s documentation. Change-Id: I8c3860ba6254919769082c9ed749f8bb287a5f5e Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/thinkcentre_m900_tiny.md A Documentation/mainboard/lenovo/thinkcentre_m900_tiny_spi_location.jpg 3 files changed, 90 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/87044/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 870f0c6..00c5e4d 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -186,6 +186,7 @@ Hardware Maintenance Manual of ThinkPads <lenovo/thinkpad_hmm.md> R60 <lenovo/r60.md> ThinkCentre M710s <lenovo/thinkcentre_m710s.md> +ThinkCentre M900 Tiny <lenovo/thinkcentre_m900_tiny.md> T4xx common <lenovo/t4xx_series.md> X2xx common <lenovo/x2xx_series.md> M920 Tiny <lenovo/m920q.md> diff --git a/Documentation/mainboard/lenovo/thinkcentre_m900_tiny.md b/Documentation/mainboard/lenovo/thinkcentre_m900_tiny.md new file mode 100644 index 0000000..bd7c72b --- /dev/null +++ b/Documentation/mainboard/lenovo/thinkcentre_m900_tiny.md @@ -0,0 +1,89 @@ +# Lenovo ThinkCentre M700 / M900 Tiny + +This page provides technical documentation on [Lenovo ThinkCentre M700 / M900 Tiny]. + +M700 Tiny and M900 Tiny are twin designs using the same exact mainboard, with +the following differences: + +```{eval-rst} ++------------------------+------+------+ +| Feature | M700 | M900 | ++========================+======+======+ +| Chipset | B150 | Q170 | ++------------------------+------+------+ +| Intel AMT | No | Yes | ++------------------------+------+------+ +| Intel TXT | No | Yes | ++------------------------+------+------+ +| PCIe lanes in M.2 slot | No | Yes | ++------------------------+------+------+ +``` + +## Flash chip + +```{eval-rst} ++----------+-----------+ +| Type | Value | ++==========+===========+ +| Socketed | no | ++----------+-----------+ +| Model | W25Q128.V | +| | 25L12873F | ++----------+-----------+ +| Size | 16MiB | ++----------+-----------+ +| Package | SOIC-8 | ++----------+-----------+ +``` + +The flash chip is divided into the following regions. + + 00000000:00000fff fd + 00001000:00002fff gbe + 00003000:007fffff me + 00800000:00ffffff bios + +## Flashing + +The flash chip cannot be flashed internally when running vendor firmware, and must +be flashed externally using a programmer of your choice. + +Steps on how to open the chassis and get access to the mainboard are described +in the [hardware maintenance manual]. Follow the steps shown from +"[Removing the computer cover]" until "[Replacing the M.2 storage drive]". + +The SPI flash should be easy to identify and the location is shown in the image +below. See the [datasheet] and [flashing firmware tutorial] for more information. + +![](thinkcentre_m900_tiny_spi_location.jpg) + +## Status + +### Working + + * Debian 12 (Linux 6.1.0) using MrChromebox' EDK II fork + * M.2 SATA + NVMe slot + * M.2 Wi-Fi slot + * Display ports + * USB + * Audio + * LAN + * CPU fan + * Discrete TPM 1.2 + * Internal flashing (from coreboot) + * COM1 header + * DisplayPort header + * Power LED + * S3 Suspend + +### Untested + + * PS/2 header + * PCIe + SATA "2L" expansion header + +[Lenovo ThinkCentre M700 / M900 Tiny]: https://psref.lenovo.com/syspool/Sys/PDF/ThinkCentre/ThinkCentre_M900_Tiny/… +[hardware maintenance manual]: https://download.lenovo.com/pccbbs/thinkcentre_pdf/m700_m900_m900x_tiny_hmm… +[Removing the computer cover]: https://download.lenovo.com/pccbbs/thinkcentre_pdf/m700_m900_m900x_tiny_hmm… +[Replacing the M.2 storage drive]: https://download.lenovo.com/pccbbs/thinkcentre_pdf/m700_m900_m900x_tiny_hmm… +[datasheet]: https://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-fla… +[flashing firmware tutorial]: ../../tutorial/flashing_firmware/index.md diff --git a/Documentation/mainboard/lenovo/thinkcentre_m900_tiny_spi_location.jpg b/Documentation/mainboard/lenovo/thinkcentre_m900_tiny_spi_location.jpg new file mode 100644 index 0000000..65fdaaa --- /dev/null +++ b/Documentation/mainboard/lenovo/thinkcentre_m900_tiny_spi_location.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/87044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c3860ba6254919769082c9ed749f8bb287a5f5e Gerrit-Change-Number: 87044 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com>

1 0

[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Keith Hui (Code Review) 29 Mar '25

29 Mar '25

Attention is currently required from: Angel Pons, Bill XIE, Nicholas Chin. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 7: (1 comment) File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c: https://review.coreboot.org/c/coreboot/+/85413/comment/a1aff95b_30651730?us… : PS7, Line 104: 0x40 > > I have been looking at the magic values of 0x20/0x40/0x70, but after digging through vendor BIOS, […] No, those values are from digging through p8z77-v vendor bios, module PcieLaneDxe, with Ghidra. Remember I said on my _le_plus there's only two options via one PCH GPIO. And from that work, I see three possible configs: (8 bits MSB-LSB being GP57-50) x111xx00 (x4) x010xx00 (x1 with PCIEX1_2) xxxxxx00 (?) So, 0x70 and 0x20 are known to be correct. The third setting changing all of GP54-GP56 to input means deferring to on board straps, that if I read my boardview right, is effectively x101xx00 or 0x50. Maybe try that and see what happens. This is sus because it diverts lane 2 away from PCIEX1_1 and effectively disables it, but since it will be going to PCIEX16_3 instead, it seems to allow a new config: PCIEX16_3 as x2. The only PCIe device I have on hand for testing is an Intel Optane nvme that seems to be x2 only itself, so... Fixing _le_plus is for later, because I first need to develop some infrastructure first, seeing there are at least 3 boards in the family with the need. And, that module being a DXE means all this is actually best done in ramstage, so expect some major rework here as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 7 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sat, 29 Mar 2025 14:16:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

1 0

[M] Change in coreboot[main]: mb/lenovo/m900_tiny: Enable Vboot
by Michał Kopeć (Code Review) 29 Mar '25

29 Mar '25

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87043?usp=email ) Change subject: mb/lenovo/m900_tiny: Enable Vboot ...................................................................... mb/lenovo/m900_tiny: Enable Vboot Add Vboot configuration (Kconfig and FMDs for RO only and RW_A layouts). TEST=Build with UEFIPayload and boot to payload. Verify in cbmem logs that verstage has executed and selected Slot A in the case of RW_A layout. Change-Id: Ide2a3a4b59be5b27bf7315690520c9392a98d044 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/mainboard/lenovo/m900_tiny/Kconfig A src/mainboard/lenovo/m900_tiny/vboot-ro.fmd A src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd 3 files changed, 77 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/87043/1 diff --git a/src/mainboard/lenovo/m900_tiny/Kconfig b/src/mainboard/lenovo/m900_tiny/Kconfig index 8ad36e0..3349575 100644 --- a/src/mainboard/lenovo/m900_tiny/Kconfig +++ b/src/mainboard/lenovo/m900_tiny/Kconfig @@ -38,4 +38,15 @@ config DIMM_SPD_SIZE default 512 #DDR4 +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select HAS_RECOVERY_MRC_CACHE + select VBOOT_VBNV_FLASH + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT + endif diff --git a/src/mainboard/lenovo/m900_tiny/vboot-ro.fmd b/src/mainboard/lenovo/m900_tiny/vboot-ro.fmd new file mode 100644 index 0000000..40855e7 --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/vboot-ro.fmd @@ -0,0 +1,30 @@ +FLASH 16M { + SI_ALL 8M { + SI_DESC 4K + SI_GBE 8K + SI_ME + } + SI_BIOS 8M { + RW_MISC 2M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_NVRAM(PRESERVE) 24K + } + + WP_RO { + FMAP 2K + RO_FRID 128 + RO_PADDING 1920 + GBB 120K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd b/src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd new file mode 100644 index 0000000..df3bfdb --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd @@ -0,0 +1,36 @@ +FLASH 16M { + SI_ALL 8M { + SI_DESC 4K + SI_GBE 8K + SI_ME + } + SI_BIOS 8M { + RW_MISC 2M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_NVRAM(PRESERVE) 24K + } + + RW_SECTION_A 3M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 128 + } + + WP_RO 3M { + FMAP 2K + RO_FRID 128 + RO_PADDING 1920 + GBB 120K + COREBOOT(CBFS) + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/87043?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide2a3a4b59be5b27bf7315690520c9392a98d044 Gerrit-Change-Number: 87043 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com>

1 0

[XS] Change in coreboot[main]: arch/x86/postcar_loader: Add comment line for reloc_params assignment
by NyeonWoo Kim (Code Review) 29 Mar '25

29 Mar '25

Attention is currently required from: Jérémy Compostella, Paul Menzel, Shuo Liu. NyeonWoo Kim has posted comments on this change by NyeonWoo Kim. ( https://review.coreboot.org/c/coreboot/+/86866?usp=email ) Change subject: arch/x86/postcar_loader: Add comment line for reloc_params assignment ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86866/comment/af58c97c_fd8b5c41?us… : PS6, Line 9: Add comment line to just give information to code. > During finalize_load(), cpu/x86/mtrr/earlymtrr. […] Thx for your suggestion. 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/86866?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7d3f9cf514ce5a8efc2af9e78992cb39a91e537 Gerrit-Change-Number: 86866 Gerrit-PatchSet: 6 Gerrit-Owner: NyeonWoo Kim Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Sat, 29 Mar 2025 12:01:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

1 0

[XS] Change in coreboot[main]: arch/x86/postcar_loader: Add comment line for reloc_params assignment
by NyeonWoo Kim (Code Review) 29 Mar '25

29 Mar '25

Attention is currently required from: Jérémy Compostella, NyeonWoo Kim, Paul Menzel. Hello Jérémy Compostella, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86866?usp=email to look at the new patch set (#7). Change subject: arch/x86/postcar_loader: Add comment line for reloc_params assignment ...................................................................... arch/x86/postcar_loader: Add comment line for reloc_params assignment During finalize_load(), cpu/x86/mtrr/earlymtrr.c:postcar_mtrr is signaled to be loaded as reloc_params, e.g. with its cache flushed. Add a comment line to specify the relationship to improve the readability. I didn't see code to set up parameter at first time. So, I just guess that adding a comment would be helpful. :) Change-Id: Ic7d3f9cf514ce5a8efc2af9e78992cb39a91e537 Signed-off-by: NyeonWoo Kim <knw0507(a)naver.com> --- M src/arch/x86/postcar_loader.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/86866/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/86866?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7d3f9cf514ce5a8efc2af9e78992cb39a91e537 Gerrit-Change-Number: 86866 Gerrit-PatchSet: 7 Gerrit-Owner: NyeonWoo Kim Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: NyeonWoo Kim

1 0

[S] Change in coreboot[main]: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING
by Gareth Yu (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Gareth Yu, Jayvik Desai, Kapil Porwal, Lawrence Chang, Nick Vaccaro, Paul Menzel, SH Kim, Simon Yang, Subrata Banik. Gareth Yu has posted comments on this change by Lawrence Chang. ( https://review.coreboot.org/c/coreboot/+/86838?usp=email ) Change subject: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING ...................................................................... Patch Set 18: (1 comment) File src/mainboard/google/brya/variants/meliks/ramstage.c: https://review.coreboot.org/c/coreboot/+/86838/comment/051bf0fe_cbabfdf9?us… : PS17, Line 20: 0xf > > Yes, hardcoding the MMIO address is possible. […] Will do. -- To view, visit https://review.coreboot.org/c/coreboot/+/86838?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7857c4f71fc7d1d0c5069a462bdd70c8dbb78179 Gerrit-Change-Number: 86838 Gerrit-PatchSet: 18 Gerrit-Owner: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Gareth Yu <gareth.yu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Gareth Yu <gareth.yu(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Gareth Yu <gareth.yu(a)intel.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 28 Mar 2025 23:54:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Gareth Yu <gareth.yu(a)intel.com>

1 0

[L] Change in coreboot[main]: Docs: Update 25.03 release notes
by Martin L Roth (Code Review) 28 Mar '25

28 Mar '25

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87042?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: Docs: Update 25.03 release notes ...................................................................... Docs: Update 25.03 release notes These are the release notes for the 25.03 release. We will update again after the release is done with the final statistics and information. Change-Id: I4a3894fd617e95b8014c3cf1afe6472994e3fb16 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87042 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M Documentation/releases/coreboot-25.03-relnotes.md 1 file changed, 285 insertions(+), 36 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/Documentation/releases/coreboot-25.03-relnotes.md b/Documentation/releases/coreboot-25.03-relnotes.md index 4b579fe..125437b 100644 --- a/Documentation/releases/coreboot-25.03-relnotes.md +++ b/Documentation/releases/coreboot-25.03-relnotes.md @@ -1,37 +1,172 @@ Upcoming release - coreboot 25.03 ======================================================================== -The 25.03 release is scheduled for the end of March, 2025 +The coreboot project is pleased to announce the release of coreboot +25.03, marking another milestone in our ongoing work to delivering +open-source firmware. This release brings important improvements to +display handling, USB debugging capabilities, and CPU topology +management, along with various other enhancements that further improve +the reliability and performance of coreboot across supported platforms. - -Update this document with changes that should be in the release notes. - -* Please use Markdown. -* See the past few release notes for the general format. -* The chip and board additions and removals will be updated right - before the release, so those do not need to be added. -* Note that all changes before the release are done are marked upcoming. - A final version of the notes are done after the release. +We extend our sincere thanks to all contributors who have made this +release possible. Your expertise and collaborative efforts continue to +propel the coreboot project forward. As always, we value the +participation of everyone in the community, from long-time developers to +those new to the project. The next coreboot release, 25.06, is scheduled +for the end of June 2025. Significant or interesting changes ---------------------------------- -* Add changes that need a full description here +### drivers/intel/fsp2_0: Enable panel-orientation aware bitmap rotation -* This section should have full descriptions and can or should have - a link to the referenced commits. +Implement logo bitmap rotation within fsp_convert_bmp_to_gop_blt() to +support devices with portrait-oriented displays. The rotation is driven +by the panel framebuffer orientation, allowing the logo to be displayed +correctly regardless of physical panel orientation. + +This resolves issues where the logo was displayed incorrectly on +portrait-oriented displays. + +Additionally, discard the display orientation change if the LID is +closed aka built-in display is not active. This will ensure that display +orientation is proper when extended display is attached w/o any display +rotation. + + +### util/find_usbdebug: Fix lsusb -t parsing for usbutils v016 and newer + +Commit e24294ff9ade ("lsusb -t: print ports and buses and devices with +same width") [1] in the usbutils repository changed the format of the +lsusb -t output, breaking the find_usbdebug.sh script. This commit is +present in usbutils version 016 and later. + +Use the output of lsusb -V to set the parsing patterns based on the +version in order to maintain compatibility with older versions of +usbutils. A simple integer comparison of the version number is used for +this, which will not work with versions older than v001 as those use a +0.nn version number format. However, since v001 was released in late +2010, it is probably safe to assume that no one will be using a version +of usbutils older than that. Usbutils v016 was released in late 2023 so +there could still conceivably be systems using older versions, such as +Ubuntu 22.04 LTS which is on v014. + +[1] https://github.com/gregkh/usbutils/commit/e24294ff9ade6dafcd1909763e888d97b… + + +### cpu/x86/topology: Fix FSP-S crash caused by shared core ID + +This resolves a crash issue observed on Meteor Lake and introduced by +commit 70bdd2e1fad9fe89835aab240ed4b41a02f15078 ("cpu/x86/topology: +Simplify CPU topology initialization"). This commit simplifies the code +and provides more detailed CPU topology information by generalizing the +use of the Extended Topology Enumeration Leaves 0x1f. As a result, the +coreboot APIC core_id field does not provide the fully detailed path +information. + +It turns out that the topology core identifier is used by the coreboot +MP service mp_get_processor_info() implementation. But the MP Service +EFI_CPU_PHYSICAL_LOCATION data structure only captures information about +the package, core, and thread. The core identifier returned to the MP +service caller must incorporate the full hierarchical path (die group, +die, module, tile, module and core). + +This commit adds a new field to the cpu topology structure to represent +the core ID within the package. + +For reference, here is that signature of the crash: + + LAPIC 0x40 in X2APIC mode. + CPU Index 2 - APIC 64 Unexpected Exception:13 @ 10:69f3d1e4 - Halting + Code: 0 eflags: 00010046 cr2: 00000000 + eax: 00000001 ebx: 69f313e8 ecx: 0000004e edx: 00000000 + edi: 69f38018 esi: 00000029 ebp: 69aeee0c esp: 69aeedc0 + [...] + +The crash occurred when FSP attempted to lock the Protected +Processor Inventory Number Enable Control MSR (IA32_PPIN_CTL +0x4e). + + 69f3d1d3: 8b 43 f4 mov -0xc(%ebx),%eax + 69f3d1d6: 89 4d c4 mov %ecx,-0x3c(%ebp) + 69f3d1d9: 89 45 dc mov %eax,-0x24(%ebp) + 69f3d1dc: 8b 55 c4 mov -0x3c(%ebp),%edx + 69f3d1df: 8b 45 c0 mov -0x40(%ebp),%eax + 69f3d1e2: 8b 4d dc mov -0x24(%ebp),%ecx + 69f3d1e5: 0f 30 wrmsr + 69f3d1e7: e9 ee fd ff ff jmp 0xfffffe39 + +FSP experiences issues due to attempting to lock the same register +multiple times for a single core. This is caused by an inconsistency in +the processor information data structure, where multiple cores share the +same identifier. This is not permitted and triggers a General Protection +Fault Exception. + + +### {drivers, lib}: Move low-battery user notification logic outside FSP + +This patch refactors low-battery user notification logic (Kconfig, APIs +to check if low-battery rendering is required, low-battery shutdown is +required) outside FSP driver code to ensure in future non-FSP platforms +might still be able to leverage this feature/logics to render the +low-battery indicator icon during boot. + +Specifically, it: + +- Moves Kconfig options related to low-battery notifications from + drivers/intel/fsp to lib/ +- Relocates the low-battery check and shutdown APIs drivers/intel/fsp + to bootsplash.h +* Adjusts the vendor driver to utilize the new APIs for low-battery + rendering decisions. +* Drop the unwanted header file "fsp/api.h" from bmp_logo.c + +This change avoids tight coupling of low-battery functionality to FSP, +promoting code reusability across platforms. + + +### soc/intel/cannonlake: Use common ACPI code for SRAM and HECI + +Use the newly-created ACPI devices in common/acpi, and adjust the SoC +ACPI name for the CSE/HECI device to match. + + +### lib: Introduce early power off support Kconfig option + +This commit introduces the `HAVE_EARLY_POWEROFF_SUPPORT` Kconfig option +and the `platform_do_early_poweroff()` API. + +The Kconfig option enables platform-specific early power off support, +which is often required on Intel platforms. The corresponding API allows +platforms to implement the necessary hardware operations for early power +off, typically before memory initialization. Additional coreboot changes --------------------------- -The following are changes across a number of patches, or changes worth -noting, but not needing a full description. - -* Changes that only need a line or two of description go here. +* Numerous changes to Haswell open source ram init +* Numerous additions to intelp2m tool +* Enhanced power management and thermal control across multiple platforms +* Improved USB Type-C and Thunderbolt support +* Added support for early power off and low battery detection +* Enhanced display and graphics support across multiple platforms +* Improved memory initialization and training +* Added support for various new memory parts and configurations +* Enhanced ACPI support and device handling +* Improved security features and TPM support +* Enhanced EC (Embedded Controller) support across platforms +* Added support for various new touch panels and input devices +* Refactored and improved code organization across multiple subsystems +* Enhanced build system and toolchain support +* Improved documentation and testing infrastructure +* Added support for RISC-V architecture improvements +* Enhanced debugging and logging capabilities +* Improved error handling and recovery mechanisms +* Added 7500 MT/s support for DDR5 @@ -40,12 +175,17 @@ ### Toolchain updates +* Update CMake from 3.30.2 to 3.31.3 +* Update ACPICA from 20230628 to 20241212 ### Git submodule pointers - -### External payloads +* arm-trusted-firmware: Update from commit id 15e5c6c91d to e5a1f4abee (608 commits) +* blobs: Update from commit id 14f8fcc1b4 to a0726508b8 (10 commits) +* fsp: Update from commit id 851f7105d8 to 86c9111639 (30 commits) +* intel-microcode: Update from commit id 8ac9378a84 to 8a62de41c0 (1 commits) +* vboot: Update from commit id f1f70f46dc to 3f94e2c7ed (49 commits) @@ -53,35 +193,143 @@ ---------------- ### Added mainboards: -* To be filled in immediately before the release by the release team - - -### Removed Mainboards -* To be filled in immediately before the release by the release team - +* AMD Crater for Renoir SoC +* ASROCK Z87 Extreme3 +* ASROCK Z87 Extreme4 +* ASROCK Z87M Extreme4 +* ASROCK Z87 Pro4 +* ASUS P8H67-I DELUXE +* Google Dirks +* Google Guren +* Google Meliks +* Google Moxie +* Google Ocelot +* Google Pujjoniru +* Google Quandiso2 +* Google Wyrdeer +* HP Pro 3400 Series +* Intel Ptlrvp +* Lenovo ThinkCentre M900 +* NovaCustom V540TU (14") +* NovaCustom V560TU (16") +* StarLabs StarLite Mk V Smart Battery (N200) +* StarLabs StarBook Mk VII (165H) +* StarLabs StarBook Mk VII (N200) ### Updated SoCs -* To be filled in immediately before the release by the release team - - - -Plans to move platform support to a branch ------------------------------------------- -* To be filled in immediately before the release by the release team +* Added src/soc/xilinx/zynq7000 Statistics from the 24.12 to the 25.03 release --------------------------------------------- -* To be filled in immediately before the release by the release team +---------------------------------------------- + +* Total Commits: 992 +* Average Commits per day: 10.09 +* Total lines added: 87471 +* Average lines added per commit: 88.18 +* Number of patches adding more than 100 lines: 95 +* Average lines added per small commit: 40.50 +* Total lines removed: 22845 +* Average lines removed per commit: 23.03 +* Total difference between added and removed: 64626 +* Total authors: 129 +* New authors: 28 Significant Known and Open Issues --------------------------------- -Issues from the coreboot bugtracker: <https://ticket.coreboot.org/> -* To be filled in immediately before the release by the release team +### coreboot-wide or architecture-wide issues + ++-----+-----------------------------------------------------------------+ +| # | Subject | ++=====+=================================================================+ +| 519 | make gconfig - could not find glade file | ++-----+-----------------------------------------------------------------+ +| 518 | make xconfig - g++: fatal error: no input files | ++-----+-----------------------------------------------------------------+ + + +### Payload-specific issues + ++-----+-----------------------------------------------------------------+ +| # | Subject | ++=====+=================================================================+ +| 577 | SeaBIOS/EDK2 Windows 10 BSOD "UNSUPPORTED PROCESSOR" | ++-----+-----------------------------------------------------------------+ +| 552 | X201 not booting with edk2 payload | ++-----+-----------------------------------------------------------------+ +| 549 | SeaBIOS Windows 10/11 BSOD "ACPI BIOS ERROR" (Thinkpad W530) | ++-----+-----------------------------------------------------------------+ +| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled | ++-----+-----------------------------------------------------------------+ +| 496 | Missing malloc check in libpayload | ++-----+-----------------------------------------------------------------+ +| 484 | No USB keyboard support with secondary payloads | ++-----+-----------------------------------------------------------------+ +| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT | ++-----+-----------------------------------------------------------------+ + + +### Platform-specific issues + ++-----+-----------------------------------------------------------------+ +| # | Subject | ++=====+=================================================================+ +| 579 | MAC address set by coreboot to RTL8111F does not persist | ++-----+-----------------------------------------------------------------+ +| 565 | Wifi card not recognized on Lenovo M700 tiny | ++-----+-----------------------------------------------------------------+ +| 563 | tty doesn't show on external display using edk2 on W530 | ++-----+-----------------------------------------------------------------+ +| 548 | Lenovo X201 Fails To Recognize Upgraded WiFi Card | ++-----+-----------------------------------------------------------------+ +| 538 | x230: Dock Causes Internal Display to "Permanently" Malfunction | ++-----+-----------------------------------------------------------------+ +| 535 | T420: Power light stays off after reboot | ++-----+-----------------------------------------------------------------+ +| 528 | Building qemu-i440fx with CONFIG_CBFS_VERIFICATION fails | ++-----+-----------------------------------------------------------------+ +| 524 | X2APIC Options cause Linux to crash on emulation/qemu-i440fx | ++-----+-----------------------------------------------------------------+ +| 517 | lenovo x230 boot stuck with connected external monitor | ++-----+-----------------------------------------------------------------+ +| 509 | SD Card hotplug not working on Apollo Lake | ++-----+-----------------------------------------------------------------+ +| 506 | APL/GML don't boot OS when CPU microcode included "from tree" | ++-----+-----------------------------------------------------------------+ +| 505 | Harcuvar CRB - 15 of 16 cores present in the operating system | ++-----+-----------------------------------------------------------------+ +| 499 | T440p - EDK2 fails with RESOURCE_ALLOCATION_TOP_DOWN enabled | ++-----+-----------------------------------------------------------------+ +| 495 | Stoney Chromebooks not booting PSPSecureOS | ++-----+-----------------------------------------------------------------+ +| 478 | X200 booting Linux takes a long time with TSC | ++-----+-----------------------------------------------------------------+ +| 474 | X200s crashes after graphic init with 8GB RAM | ++-----+-----------------------------------------------------------------+ +| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb | ++-----+-----------------------------------------------------------------+ +| 453 | Intel HDMI / DP Audio not present in Windows after libgfxinit | ++-----+-----------------------------------------------------------------+ +| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking | ++-----+-----------------------------------------------------------------+ +| 448 | Thinkpad T440P ACPI Battery Value Issues | ++-----+-----------------------------------------------------------------+ +| 446 | Optiplex 9010 No Post | ++-----+-----------------------------------------------------------------+ +| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz) | ++-----+-----------------------------------------------------------------+ +| 427 | x200: Two battery charging issues | ++-----+-----------------------------------------------------------------+ +| 412 | x230 reboots on suspend | ++-----+-----------------------------------------------------------------+ +| 393 | T500 restarts rather than waking up from suspend | ++-----+-----------------------------------------------------------------+ +| 350 | I225 PCIe device not detected on Harcuvar | ++-----+-----------------------------------------------------------------+ @@ -94,3 +342,4 @@ * Documentation: <https://doc.coreboot.org> * Issue tracker: <https://ticket.coreboot.org/projects/coreboot> * Donations: <https://coreboot.org/donate.html> + -- To view, visit https://review.coreboot.org/c/coreboot/+/87042?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a3894fd617e95b8014c3cf1afe6472994e3fb16 Gerrit-Change-Number: 87042 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[L] Change in coreboot[main]: Docs: Update 25.03 release notes
by Martin L Roth (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Angel Pons, Jason Glenesk, Martin L Roth. Hello Angel Pons, Felix Singer, Jason Glenesk, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87042?usp=email to look at the new patch set (#2). Change subject: Docs: Update 25.03 release notes ...................................................................... Docs: Update 25.03 release notes These are the release notes for the 25.03 release. We will update again after the release is done with the final statistics and information. Change-Id: I4a3894fd617e95b8014c3cf1afe6472994e3fb16 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- M Documentation/releases/coreboot-25.03-relnotes.md 1 file changed, 285 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/87042/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87042?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a3894fd617e95b8014c3cf1afe6472994e3fb16 Gerrit-Change-Number: 87042 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

1 0

[L] Change in coreboot[main]: Docs: Updated 25.03 release notes
by Felix Singer (Code Review) 28 Mar '25

28 Mar '25

Attention is currently required from: Angel Pons, Jason Glenesk, Martin L Roth. Felix Singer has posted comments on this change by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/87042?usp=email ) Change subject: Docs: Updated 25.03 release notes ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87042?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a3894fd617e95b8014c3cf1afe6472994e3fb16 Gerrit-Change-Number: 87042 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Mar 2025 21:23:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

← Newer
1
...
5
6
7
8
9
10
11
...
282
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2025