coreboot-gerrit March 2025

coreboot-gerrit@coreboot.org

1 participants
2811 discussions

[S] Change in coreboot[main]: mb/google/fatcat/var/francka: Add support for DMIC0
by Mac Chiang (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Kapil Porwal, Subrata Banik. Mac Chiang has posted comments on this change by Mac Chiang. ( https://review.coreboot.org/c/coreboot/+/86699?usp=email ) Change subject: mb/google/fatcat/var/francka: Add support for DMIC0 ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/fatcat/variants/francka/fw_config.c: https://review.coreboot.org/c/coreboot/+/86699/comment/eee03abb_3e9aeed0?us… : PS6, Line 28: /* GPP_D09: PCH_DGPU_HOLD_RST#_R */ : PAD_NC(GPP_D09, NONE), : /* GPP_D16: HDA_RST# */ : PAD_NC(GPP_D16, NONE), : /* GPP_S00: SNDW_3_SCL */ : PAD_NC(GPP_S00, NONE), : /* GPP_S01: SNDW_3_SDA */ : PAD_NC(GPP_S01, NONE), : /* GPP_S04: SNDW2_CLK */ : PAD_NC(GPP_S04, NONE), : /* GPP_S05: SNDW2_DATA0 */ : PAD_NC(GPP_S05, NONE), > These pins are NC in either case. why not move them to gpio. […] For future SoundWire SKUs, I think it will need to be reconfigured if set to default. -- To view, visit https://review.coreboot.org/c/coreboot/+/86699?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idcc18a6a605694bc5c1a2994453717887814e897 Gerrit-Change-Number: 86699 Gerrit-PatchSet: 6 Gerrit-Owner: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 31 Mar 2025 02:42:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[S] Change in coreboot[main]: util/amdfwtool: add PLATFORM_FAEGAN
by Maximilian Brune (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Felix Held, Patrick Rudolph. Maximilian Brune has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/86940?usp=email ) Change subject: util/amdfwtool: add PLATFORM_FAEGAN ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86940?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40a3e9981696fc02a44fbf300d1b47060a4a398b Gerrit-Change-Number: 86940 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 31 Mar 2025 00:23:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: Documentation/mainboard/lenovo: Add ThinkCentre M700/M900 Tiny
by Nicholas Chin (Code Review) 30 Mar '25

30 Mar '25

Attention is currently required from: Krystian Hebel, Maciej Pijanowski, Michał Kopeć, Michał Żygowski. Nicholas Chin has posted comments on this change by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/87044?usp=email ) Change subject: Documentation/mainboard/lenovo: Add ThinkCentre M700/M900 Tiny ...................................................................... Patch Set 3: (3 comments) File Documentation/mainboard/lenovo/thinkcentre_m900_tiny.md: https://review.coreboot.org/c/coreboot/+/87044/comment/7cbfc7a3_10c8e903?us… : PS3, Line 30: 25L12873F MX25L12873F? https://review.coreboot.org/c/coreboot/+/87044/comment/329dc421_3f4731bb?us… : PS3, Line 63: MrChromebox' EDK II fork Would be good to mention the version https://review.coreboot.org/c/coreboot/+/87044/comment/b4047dd2_576f4cfa?us… : PS3, Line 87: https://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-fla… This link doesn't seem to work as intended. Seems like the `&` gets converted to `&`, breaking the link (links to https://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-fla…)8JV). I haven't found a fix though; seems like this is a general issue with markdown. Maybe use a different link such as https://www.mouser.com/datasheet/2/949/w25q128jv_revf_03272018_plus-1489608… ? -- To view, visit https://review.coreboot.org/c/coreboot/+/87044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c3860ba6254919769082c9ed749f8bb287a5f5e Gerrit-Change-Number: 87044 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Sun, 30 Mar 2025 16:54:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/intel/cmn/blk: Remove boot partition check for forced cse sync
by Subrata Banik (Code Review) 30 Mar '25

30 Mar '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Kapil Porwal. Subrata Banik has posted comments on this change by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/86153?usp=email ) Change subject: soc/intel/cmn/blk: Remove boot partition check for forced cse sync ...................................................................... Patch Set 13: (3 comments) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/86153/comment/b5c6485f_f3071db0?us… : PS12, Line 751: if ((vb2api_gbb_get_flags(ctx) & VB2_GBB_FLAG_FORCE_CSE_SYNC) && : cse_get_current_bp() == RO) { > The current flag-based implementation has backward compatibility and will always function regardless of the current boot partition. Therefore, I believe we may not need to check if the platform is newer or older than PTL. WDYT. what is the point returning `return cse_info_in_cmos.cse_sync_status & CSE_ENFORCED_SYNC_REQUEST` as true if the CSE slot is RW? We won't be able to enforce CSE sync when CSE is booting from RW slot ? we might need to push CSE to go into RO slot so we can enforce CSE update https://review.coreboot.org/c/coreboot/+/86153/comment/3922cd55_4723b0de?us… : PS12, Line 765: is_cse_sync_enforced > The ESOL screen function at romstage also calls `is_cse_sync_enforced()`. At that stage, the enforce CSE sync status flags have not been updated. Therefore, an update to these status flags is required. I'm unable to follow. if you take a look into `is_cse_sync_enforced` API used previously then this API just meant to tell if CSE sync being enforced but now you have used this function to also store the status of CSE info crc, CSE specific information etc. What i'm asking is to decouple this API. What you need here is just return `return cse_info_in_cmos.cse_sync_status & CSE_ENFORCED_SYNC_REQUEST` if you need to update the CSE info CMOS status during `is_cse_sync_enforced`, then you can add `update_cse_info()` from all caller of `is_cse_sync_enforced` API. https://review.coreboot.org/c/coreboot/+/86153/comment/70eadfe7_a61bfc66?us… : PS12, Line 792: n cse_info_in_cmos.cse_sync_status & CSE_ENFORCED_SYNC_REQ; > Yes, the sync status update exhibits a distinct behavior and warrants relocation to a dedicated function, `store_cse_sync_status()`. > > However, `is_cse_sync_enforced()` also determines if ESOL should be displayed or not. If we move the sync status update elsewhere, ESOL execution during ROMSTAGE might not receive the correct indication to display the ESOL screen. you just need to decouple `is_cse_sync_enforced` API to ensure storing into CSE info can be handled by the caller of the API. -- To view, visit https://review.coreboot.org/c/coreboot/+/86153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1e4180cb5fec3990fdee2b0e412173b1c8c6ded Gerrit-Change-Number: 86153 Gerrit-PatchSet: 13 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Sun, 30 Mar 2025 13:04:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Dinesh Gehlot <digehlot(a)google.com>

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[M] Change in coreboot[main]: soc/intel/cmn/blk: Remove boot partition check for forced cse sync
by Subrata Banik (Code Review) 30 Mar '25

30 Mar '25

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[M] Change in coreboot[main]: mb/lenovo/m900_tiny: Put options in CFR cbtable
by Michał Kopeć (Code Review) 30 Mar '25

30 Mar '25

Attention is currently required from: Alexander Couzens. Hello Alexander Couzens, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87048?usp=email to look at the new patch set (#2). Change subject: mb/lenovo/m900_tiny: Put options in CFR cbtable ...................................................................... mb/lenovo/m900_tiny: Put options in CFR cbtable Change-Id: I259f88a3ceb9aee54016bb88a7d4de2b58dffa83 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/mainboard/lenovo/m900_tiny/Kconfig M src/mainboard/lenovo/m900_tiny/Makefile.mk A src/mainboard/lenovo/m900_tiny/cfr.c M src/mainboard/lenovo/m900_tiny/ramstage.c 4 files changed, 113 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/87048/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87048?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I259f88a3ceb9aee54016bb88a7d4de2b58dffa83 Gerrit-Change-Number: 87048 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu>

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[M] Change in coreboot[main]: mb/lenovo/m900_tiny: Put options in CFR cbtable
by Michał Kopeć (Code Review) 30 Mar '25

30 Mar '25

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87048?usp=email ) Change subject: mb/lenovo/m900_tiny: Put options in CFR cbtable ...................................................................... mb/lenovo/m900_tiny: Put options in CFR cbtable Change-Id: I259f88a3ceb9aee54016bb88a7d4de2b58dffa83 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/mainboard/lenovo/m900_tiny/Kconfig M src/mainboard/lenovo/m900_tiny/Makefile.mk A src/mainboard/lenovo/m900_tiny/cfr.c M src/mainboard/lenovo/m900_tiny/ramstage.c 4 files changed, 113 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/87048/1 diff --git a/src/mainboard/lenovo/m900_tiny/Kconfig b/src/mainboard/lenovo/m900_tiny/Kconfig index 8ad36e0..a99afa1 100644 --- a/src/mainboard/lenovo/m900_tiny/Kconfig +++ b/src/mainboard/lenovo/m900_tiny/Kconfig @@ -6,6 +6,8 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 + select DRIVERS_EFI_VARIABLE_STORE + select DRIVERS_OPTION_CFR select DRIVERS_UART_8250IO select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/m900_tiny/Makefile.mk b/src/mainboard/lenovo/m900_tiny/Makefile.mk index 44db091..3b5a2a2 100644 --- a/src/mainboard/lenovo/m900_tiny/Makefile.mk +++ b/src/mainboard/lenovo/m900_tiny/Makefile.mk @@ -7,6 +7,7 @@ romstage-y += romstage.c +ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c ramstage-y += gpio.c ramstage-y += hda_verb.c ramstage-y += ramstage.c diff --git a/src/mainboard/lenovo/m900_tiny/cfr.c b/src/mainboard/lenovo/m900_tiny/cfr.c new file mode 100644 index 0000000..2bbb67b --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/cfr.c @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boot/coreboot_tables.h> +#include <drivers/option/cfr_frontend.h> + +struct sm_object wifi_slot_enable = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "wifi_slot_enable", + .ui_name = "Enable Wi-Fi card slot", + .ui_helptext = "Enable or disable detection of devices in the Wi-Fi card slot", + .default_value = true, +}); + +struct sm_object ssd_slot_enable = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "ssd_slot_enable", + .ui_name = "Enable SSD slot", + .ui_helptext = "Enable or disable detection of devices in the SSD slot", + .default_value = true, +}); + +struct sm_object hdd_slot_enable = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "hdd_slot_enable", + .ui_name = "Enable 2.5 inch disk slot", + .ui_helptext = "Enable or disable detection of devices in the 2.5 inch disk slot", + .default_value = true, +}); + +static struct sm_obj_form devices = { + .ui_name = "Devices", + .obj_list = (const struct sm_object *[]) { + &wifi_slot_enable, + &ssd_slot_enable, + &hdd_slot_enable, + NULL + }, +}; + +struct sm_object ps2_enable = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "ps2_enable", + .ui_name = "PS/2 controller", + .ui_helptext = "Enable or disable the PS/2 controller. Enabling PS/2 slightly increases boot time.", + .default_value = true, +}); + +struct sm_object power_on_after_fail = SM_DECLARE_ENUM({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "power_on_after_fail", + .ui_name = "Power state after fail", + .ui_helptext = "State of the platform after external power is restored", + .default_value = CONFIG_MAINBOARD_POWER_FAILURE_STATE, + .values = (const struct sm_enum_value[]) { + { "Off", 0 }, + { "On", 1 }, + { "Previous", 2 }, + SM_ENUM_VALUE_END }, +}); + +static struct sm_obj_form superio = { + .ui_name = "Super I/O", + .obj_list = (const struct sm_object *[]) { + &ps2_enable, + &power_on_after_fail, + NULL + }, +}; + +static struct sm_obj_form *sm_root[] = { + &devices, + &superio, + NULL +}; + +void mb_cfr_setup_menu(struct lb_cfr *cfr_root) +{ + cfr_write_setup_menu(cfr_root, sm_root); +} diff --git a/src/mainboard/lenovo/m900_tiny/ramstage.c b/src/mainboard/lenovo/m900_tiny/ramstage.c index 6e66f3a..7eadabe 100644 --- a/src/mainboard/lenovo/m900_tiny/ramstage.c +++ b/src/mainboard/lenovo/m900_tiny/ramstage.c @@ -2,10 +2,14 @@ #include <console/console.h> #include <device/device.h> +#include <device/pci_def.h> #include <drivers/intel/gma/int15.h> #include <gpio.h> #include <mainboard/gpio.h> +#include <option.h> #include <soc/ramstage.h> +#include <static.h> +#include <superio/nuvoton/nct6687d/nct6687d.h> static void print_board_id(void) { @@ -32,19 +36,42 @@ } printk(BIOS_INFO, "Serial header %spopulated\n", !gpio_get(GPP_A22) ? "" : "un"); - printk(BIOS_INFO, "PS/2 header %spopulated\n", !gpio_get(GPP_D14) ? "" : "un"); - printk(BIOS_INFO, "USB header %spopulated\n", !gpio_get(GPP_C19) ? "" : "un"); - printk(BIOS_INFO, "DisplayPort header %spopulated\n", !gpio_get(GPP_B15) ? "" : "un"); - printk(BIOS_INFO, "PCIe / SATA header %spopulated\n", !gpio_get(GPP_B21) ? "" : "un"); } +static void devtree_update(void) +{ + config_t *cfg = config_of_soc(); + struct device *wifi_dev = DEV_PTR(pcie_rp7); + struct device *ssd_dev = DEV_PTR(pcie_rp17); + struct device *ps2_dev = dev_find_slot_pnp(0x2e, NCT6687D_KBC); + + if (get_uint_option("wifi_slot_enable", 1) == 0) { + cfg->usb2_ports[8].enable = 0; + wifi_dev->enabled = 0; + } + + if (get_uint_option("ssd_slot_enable", 1) == 0) { + cfg->SataPortsEnable[4] = 0; + ssd_dev->enabled = 0; + } + + if (get_uint_option("hdd_slot_enable", 1) == 0) { + cfg->SataPortsEnable[0] = 0; + cfg->SataPortsEnable[1] = 0; + } + + if (get_uint_option("ps2_enable", 1) == 0) + ps2_dev->enabled = 0; +} + static void mainboard_enable(struct device *dev) { mainboard_configure_gpios(); + devtree_update(); print_board_id(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/87048?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I259f88a3ceb9aee54016bb88a7d4de2b58dffa83 Gerrit-Change-Number: 87048 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com>

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[NoOp] Change in coreboot[main]: mb/lenovo/m900_tiny: Update VBT to build 1037 with Kaby Lake gfx support
by Michał Kopeć (Code Review) 30 Mar '25

30 Mar '25

Attention is currently required from: Alexander Couzens, Krystian Hebel, Michał Kopeć, Michał Żygowski, Paul Menzel. Hello Alexander Couzens, Krystian Hebel, Michał Żygowski, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84873?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/lenovo/m900_tiny: Update VBT to build 1037 with Kaby Lake gfx support ...................................................................... mb/lenovo/m900_tiny: Update VBT to build 1037 with Kaby Lake gfx support Update VBT to one extracted from newer Lenovo UEFI, version FWKTBFA. The newer VBT has build number 1037 and supports Kaby Lake graphics, while the old VBT with build number 1000 only supports Skylake. The old VBT starts with $VBT_SKYLAKE while the new one starts with $VBT_KABYLAKE. TEST=Insert CPU with integrated HD 630 graphics (i3-7100) and check if all video outputs work in firmware. Change-Id: I5e108d4ad8bf0663f3e1fa32145e40ea9babeac5 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/mainboard/lenovo/m900_tiny/data.vbt 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/84873/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84873?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e108d4ad8bf0663f3e1fa32145e40ea9babeac5 Gerrit-Change-Number: 84873 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu>

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Keith Hui (Code Review) 30 Mar '25

30 Mar '25

Attention is currently required from: Angel Pons, Bill XIE, Nicholas Chin. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 7: (1 comment) File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c: https://review.coreboot.org/c/coreboot/+/85413/comment/4f30c54b_baa89725?us… : PS7, Line 104: 0x40 > No, those values are from digging through p8z77-v vendor bios, module PcieLaneDxe, with Ghidra. […] Bill, if you have a multimeter on hand, this next test will settle everything once and for all (I hope). I'd like you to probe the three PCIe switcher select signals directly, while running vendor BIOS, for each possible setting - start with the one where PCIEX1_2 actually works. You need not boot any OS at all, though it shouldn't hurt. Hook the meter's negative lead to a ground and use the positive lead to probe these three locations: X_QSW_SEL2: QSWR504 pad 2 (towards the PCI slot) X_QSW_SEL3: QSWR504 pad 1 (towards the PCIEX16_1 slot) X_QSW_SEL4: QSWQ7 pin 3 (on the single leg side) QSWR504 according to boardview should be unpopulated, giving you access to both pads. I uploaded a map of their positions on the board to the issue tracker. High is 3.3v. -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 7 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sun, 30 Mar 2025 02:00:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[M] Change in coreboot[main]: Documentation: Add coreboot release 25.06 template
by 9elements QA (Code Review) 29 Mar '25

29 Mar '25

9elements QA has posted comments on this change by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/87030?usp=email ) Change subject: Documentation: Add coreboot release 25.06 template ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/237313 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/237311 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/237310 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/237309 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/237308 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/237307 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/237306 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/237305 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/237304 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/237303 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/237302 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/237301 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/87030?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8aa266973181be12620343eb58bb9ba8f0ccc79 Gerrit-Change-Number: 87030 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sat, 29 Mar 2025 22:07:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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