coreboot-gerrit March 2025

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[M] Change in coreboot[main]: Documentation/mainboard/lenovo: Add ThinkCentre M700/M900 Tiny
by Michał Kopeć (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Krystian Hebel, Maciej Pijanowski, Michał Żygowski, Nicholas Chin. Michał Kopeć has posted comments on this change by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/87044?usp=email ) Change subject: Documentation/mainboard/lenovo: Add ThinkCentre M700/M900 Tiny ...................................................................... Patch Set 4: (3 comments) File Documentation/mainboard/lenovo/thinkcentre_m900_tiny.md: https://review.coreboot.org/c/coreboot/+/87044/comment/5721b6b9_96eafd88?us… : PS3, Line 30: 25L12873F > MX25L12873F? Right, yes, done https://review.coreboot.org/c/coreboot/+/87044/comment/c48a6818_f62a35c5?us… : PS3, Line 63: MrChromebox' EDK II fork > Would be good to mention the version Added https://review.coreboot.org/c/coreboot/+/87044/comment/9c86a78a_2f60d46a?us… : PS3, Line 87: https://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-fla… > This link doesn't seem to work as intended. […] Thanks, changed to the other link -- To view, visit https://review.coreboot.org/c/coreboot/+/87044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c3860ba6254919769082c9ed749f8bb287a5f5e Gerrit-Change-Number: 87044 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 31 Mar 2025 19:19:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

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[M] Change in coreboot[main]: Documentation/mainboard/lenovo: Add ThinkCentre M700/M900 Tiny
by Michał Kopeć (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Krystian Hebel, Maciej Pijanowski, Michał Kopeć, Michał Żygowski, Nicholas Chin. Hello Krystian Hebel, Maciej Pijanowski, Michał Żygowski, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87044?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Documentation/mainboard/lenovo: Add ThinkCentre M700/M900 Tiny ...................................................................... Documentation/mainboard/lenovo: Add ThinkCentre M700/M900 Tiny Heavily based on M710s documentation. Change-Id: I8c3860ba6254919769082c9ed749f8bb287a5f5e Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/thinkcentre_m900_tiny.md A Documentation/mainboard/lenovo/thinkcentre_m900_tiny_spi_location.jpg 3 files changed, 89 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/87044/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/87044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c3860ba6254919769082c9ed749f8bb287a5f5e Gerrit-Change-Number: 87044 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[M] Change in coreboot[main]: mb/google/fatcat: Rationalize Wi-Fi and Bluetooth combinations
by Jérémy Compostella (Code Review) 31 Mar '25

31 Mar '25

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85662?usp=email ) Change subject: mb/google/fatcat: Rationalize Wi-Fi and Bluetooth combinations ...................................................................... mb/google/fatcat: Rationalize Wi-Fi and Bluetooth combinations We aim to support only two Wi-Fi and Bluetooth combinations: - CNVi Wi-Fi paired with CNVi Bluetooth - Discrete Wi-Fi paired with USB Bluetooth The CNVi core settings are configured at runtime based on the firmware configuration for Fatcat and Felino variants. Since Francka only supports CNVi configuration, settings are enforced in the override device tree. Change-Id: Ida95d1898d24898880de567db7c0ac8ac053eeaa Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85662 Reviewed-by: Ben Kao <ben.kao(a)intel.com> Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb M src/mainboard/google/fatcat/variants/felino/Makefile.mk M src/mainboard/google/fatcat/variants/felino/overridetree.cb A src/mainboard/google/fatcat/variants/felino/variant.c M src/mainboard/google/fatcat/variants/francka/overridetree.cb 5 files changed, 43 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved Jayvik Desai: Looks good to me, but someone else must approve Ben Kao: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index bc0b9e2..741b5a4 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -77,7 +77,7 @@ register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C3 register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0 register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 / WWAN with rework - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #2 / M.2 WWAN with rework @@ -444,7 +444,10 @@ register "desc" = ""USB2 Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)" - device ref usb2_port8 on end + device ref usb2_port8 on + probe WIFI WIFI_PCIE_6 + probe WIFI WIFI_PCIE_7 + end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port 1"" @@ -570,9 +573,16 @@ register "wake" = "GPE0_PME_B0" register "add_acpi_dma_property" = "true" register "enable_cnvi_ddr_rfim" = "true" + use cnvi_bluetooth as bluetooth_companion device generic 0 on end end end # CNVi + + device ref cnvi_bluetooth on + probe WIFI WIFI_CNVI_6 + probe WIFI WIFI_CNVI_7 + end + # NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled. # TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways. device ref i2c0 on end diff --git a/src/mainboard/google/fatcat/variants/felino/Makefile.mk b/src/mainboard/google/fatcat/variants/felino/Makefile.mk index dcd5ec7..80d4f62 100644 --- a/src/mainboard/google/fatcat/variants/felino/Makefile.mk +++ b/src/mainboard/google/fatcat/variants/felino/Makefile.mk @@ -6,3 +6,4 @@ ramstage-y += gpio.c romstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb index aa8c16b..b3b63e7 100644 --- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb @@ -67,7 +67,7 @@ register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 # USB HUB (USB2 Camera) register "usb2_ports[5]" = "USB2_PORT_LONG(OC3)" # Type-A Port A1 / - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 x1 Type-A Con #2 / @@ -187,7 +187,10 @@ register "desc" = ""USB2 Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)" - device ref usb2_port8 on end + device ref usb2_port8 on + probe WIFI WIFI_PCIE_6 + probe WIFI WIFI_PCIE_7 + end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port 1"" @@ -266,10 +269,16 @@ register "wake" = "GPE0_PME_B0" register "add_acpi_dma_property" = "true" register "enable_cnvi_ddr_rfim" = "true" + use cnvi_bluetooth as bluetooth_companion device generic 0 on end end end # CNVi + device ref cnvi_bluetooth on + probe WIFI WIFI_CNVI_6 + probe WIFI WIFI_CNVI_7 + end + device ref i2c0 on end device ref i2c1 on diff --git a/src/mainboard/google/fatcat/variants/felino/variant.c b/src/mainboard/google/fatcat/variants/felino/variant.c new file mode 100644 index 0000000..76089ed --- /dev/null +++ b/src/mainboard/google/fatcat/variants/felino/variant.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <fw_config.h> + +void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config) +{ + if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) || /* CNVi Wi-Fi */ + fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) { + config->cnvi_wifi_core = true; + config->cnvi_bt_core = true; + } +} diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb index f9ae720..f9e172c 100644 --- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb @@ -33,7 +33,6 @@ register "usb2_ports[4]" = "USB2_PORT_SHORT(OC0)" # Type-A Port A1 register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # USB HUB (USB2 Camera) - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #1 @@ -53,8 +52,9 @@ # TCSS USB3 register "tcss_aux_ori" = "1" - # Enable CNVi WiFi + # Enable CNVi Wi-Fi and Bluetooth register "cnvi_wifi_core" = "true" + register "cnvi_bt_core" = "true" register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -162,12 +162,6 @@ device ref usb2_port7 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)" - device ref usb2_port8 on end - end - chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port 0"" register "type" = "UPC_TYPE_USB3_A" register "group" = "ACPI_PLD_GROUP(1, 2)" @@ -188,9 +182,13 @@ register "wake" = "GPE0_PME_B0" register "add_acpi_dma_property" = "true" register "enable_cnvi_ddr_rfim" = "true" + use cnvi_bluetooth as bluetooth_companion device generic 0 on end end end # CNVi + + device ref cnvi_bluetooth on end + # NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled. # TPM device is under i2c1. Therefore, i2c0 needs to be enabled anyways. device ref i2c0 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/85662?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida95d1898d24898880de567db7c0ac8ac053eeaa Gerrit-Change-Number: 85662 Gerrit-PatchSet: 19 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Ben Kao <ben.kao(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/elkahrtalake/pmc,gpio: Fix PMC GPE GPIO routes
by Jérémy Compostella (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Intel coreboot Reviewers, Michał Żygowski, Werner Zeh. Jérémy Compostella has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/87050?usp=email ) Change subject: soc/intel/elkahrtalake/pmc,gpio: Fix PMC GPE GPIO routes ...................................................................... Patch Set 1: Code-Review+1 (3 comments) Patchset: PS1: Note: I did not open the EDS to verify the values changed by this CL. Commit Message: https://review.coreboot.org/c/coreboot/+/87050/comment/ceef9cb0_9ef19959?us… : PS1, Line 7: elkahrtalake elkhartlake https://review.coreboot.org/c/coreboot/+/87050/comment/958608bd_aa48ca09?us… : PS1, Line 10: R&DC R&DC is not necessary. The document title and number is the reference. -- To view, visit https://review.coreboot.org/c/coreboot/+/87050?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I910f3c4c0d31b8d24b83cd2c3a28688b898b5d9f Gerrit-Change-Number: 87050 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 31 Mar 2025 16:53:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/var/uldrenite: Configure descriptor for either MBVR or FIVR
by Jérémy Compostella (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Ben Kao, Dinesh Gehlot, Dtrain Hsu, Eric Lai, Intel coreboot Reviewers, Jamie Chen, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro, Subrata Banik. Jérémy Compostella has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/87033?usp=email ) Change subject: mb/var/uldrenite: Configure descriptor for either MBVR or FIVR ...................................................................... Patch Set 5: (6 comments) Patchset: PS5: I am a bit confused by this CL, and I am not even sure it is in a ready-to-review state. I'll move on until instructed otherwise. Commit Message: https://review.coreboot.org/c/coreboot/+/87033/comment/19b60894_c0725bfc?us… : PS5, Line 9: According to the root cause analysis in b/404126972#comment22, Not everyone on coreboot.org have access to this information. https://review.coreboot.org/c/coreboot/+/87033/comment/293bf3ec_5971872d?us… : PS5, Line 10: , , , https://review.coreboot.org/c/coreboot/+/87033/comment/25ca6689_c57e3ce7?us… : PS5, Line 10: Right right https://review.coreboot.org/c/coreboot/+/87033/comment/d1ff6434_e13cc45f?us… : PS5, Line 10: FIVR FIVR (Fully Integrated Voltage Regulator) https://review.coreboot.org/c/coreboot/+/87033/comment/3142e2f0_7e2187aa?us… : PS5, Line 11: MBVR MBVR (MotherBoard Voltage Regulator) -- To view, visit https://review.coreboot.org/c/coreboot/+/87033?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I337574c8c55889ceb49b9f33625feadb48bd8890 Gerrit-Change-Number: 87033 Gerrit-PatchSet: 5 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ben Kao <ben.kao(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ben Kao <ben.kao(a)intel.com> Gerrit-Comment-Date: Mon, 31 Mar 2025 16:47:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/amd/*/psp_verstage: Remove duplicate verstage-generic-ccopts
by Maximilian Brune (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86864?usp=email ) Change subject: soc/amd/*/psp_verstage: Remove duplicate verstage-generic-ccopts ...................................................................... Patch Set 5: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/86864?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic64f5187e50b903af5461bfa4d57bb4951d3b501 Gerrit-Change-Number: 86864 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 31 Mar 2025 16:28:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/proteclti/vault_ehl/devicetree.cb: Remove TPM I/O resources
by Michał Kopeć (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Michał Żygowski, Piotr Król. Michał Kopeć has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/87052?usp=email ) Change subject: mb/proteclti/vault_ehl/devicetree.cb: Remove TPM I/O resources ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/87052/comment/1f2b7ea8_37ba2532?us… : PS1, Line 7: mb/proteclti/vault_ehl/devicetree.cb: Remove TPM I/O resources typo: protectli -- To view, visit https://review.coreboot.org/c/coreboot/+/87052?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e504af6bc7268bc5ecce2e6642ed172ab682726 Gerrit-Change-Number: 87052 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Mon, 31 Mar 2025 15:20:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/elkahrtalake/pmc,gpio: Fix PMC GPE GPIO routes
by Michał Żygowski (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Intel coreboot Reviewers, Werner Zeh. Michał Żygowski has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/87050?usp=email ) Change subject: soc/intel/elkahrtalake/pmc,gpio: Fix PMC GPE GPIO routes ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/87050/comment/59095f56_cb57bbd9?us… : PS1, Line 13: non-existent GPIO groups I mean, GPP_S exists, but there is no value for it in the PMC and GPIO GPE DW registers. I may bring back the value of 0xE here if necessary... -- To view, visit https://review.coreboot.org/c/coreboot/+/87050?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I910f3c4c0d31b8d24b83cd2c3a28688b898b5d9f Gerrit-Change-Number: 87050 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 31 Mar 2025 14:02:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/proteclti/vault_ehl/devicetree.cb: Remove TPM I/O resources
by Michał Żygowski (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Piotr Król. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87052?usp=email ) Change subject: mb/proteclti/vault_ehl/devicetree.cb: Remove TPM I/O resources ...................................................................... mb/proteclti/vault_ehl/devicetree.cb: Remove TPM I/O resources Modern TPMs do not use legacy I/O access in favor of MMIO access. Discard the I/O resource, so it is not added to the ACPI _CRS. TEST=Boot Ubuntu 24.04 and check dmesg that Linux does not report problems with TPM. Check Windows Device Manager does not report any problem with TPM and its resources. Change-Id: I0e504af6bc7268bc5ecce2e6642ed172ab682726 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/protectli/vault_ehl/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/87052/1 diff --git a/src/mainboard/protectli/vault_ehl/devicetree.cb b/src/mainboard/protectli/vault_ehl/devicetree.cb index 0db005f..3eb8307 100644 --- a/src/mainboard/protectli/vault_ehl/devicetree.cb +++ b/src/mainboard/protectli/vault_ehl/devicetree.cb @@ -195,7 +195,7 @@ device pnp 2e.a off end # CIR end chip drivers/pc80/tpm - device pnp 0c31.0 on end + device pnp 0.0 on end end end device pci 1f.1 on end # P2SB -- To view, visit https://review.coreboot.org/c/coreboot/+/87052?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e504af6bc7268bc5ecce2e6642ed172ab682726 Gerrit-Change-Number: 87052 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com>

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[XS] Change in coreboot[main]: mainboard/protectli/vault_ehl/Kconfig: Configure TPM PIRQ
by Michał Żygowski (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Piotr Król. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87051?usp=email ) Change subject: mainboard/protectli/vault_ehl/Kconfig: Configure TPM PIRQ ...................................................................... mainboard/protectli/vault_ehl/Kconfig: Configure TPM PIRQ The board uses GPP_G19 as GPIO interrupt for SPI dTPM. The pad is already configured as APIC interrupt, so simply define the TPM_PIRQ to GPP_G19_IRQ, which is 0x6B for Elkhart Lake. TEST=Boot Ubuntu 24.04 and check dmesg that Linux does not complain on TPM interrupt not working. Check Windows Device Manager does not report any problem with TPM and its resources. Change-Id: Ia23319680cff927f10b44d7a5d07928cc30dbc9d Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/protectli/vault_ehl/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/87051/1 diff --git a/src/mainboard/protectli/vault_ehl/Kconfig b/src/mainboard/protectli/vault_ehl/Kconfig index 5f283ee..c9d4d18 100644 --- a/src/mainboard/protectli/vault_ehl/Kconfig +++ b/src/mainboard/protectli/vault_ehl/Kconfig @@ -49,4 +49,7 @@ config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A +config TPM_PIRQ + default 0x6B # GPP_G19_IRQ + endif # BOARD_PROTECTLI_VP2420 -- To view, visit https://review.coreboot.org/c/coreboot/+/87051?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia23319680cff927f10b44d7a5d07928cc30dbc9d Gerrit-Change-Number: 87051 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com>

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