coreboot-gerrit March 2025

coreboot-gerrit@coreboot.org

1 participants
2811 discussions

[S] Change in coreboot[main]: soc/intel/elkahrtalake/pmc,gpio: Fix PMC GPE GPIO routes
by Michał Żygowski (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Intel coreboot Reviewers, Werner Zeh. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87050?usp=email ) Change subject: soc/intel/elkahrtalake/pmc,gpio: Fix PMC GPE GPIO routes ...................................................................... soc/intel/elkahrtalake/pmc,gpio: Fix PMC GPE GPIO routes Based on the description of PMC GPIO_CONF register from EHL EDS Vol 2 Book 2 rev 2.3 R&DC #614109. Some of the groups had incorrect values or even defined non-existent GPIO groups. TEST=Boot Protectli VP2420 to Ubuntu 24.04. Change-Id: I910f3c4c0d31b8d24b83cd2c3a28688b898b5d9f Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/elkhartlake/gpio.c M src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h M src/soc/intel/elkhartlake/include/soc/pmc.h 3 files changed, 10 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/87050/1 diff --git a/src/soc/intel/elkhartlake/gpio.c b/src/soc/intel/elkhartlake/gpio.c index 1b07bc5..795763e 100644 --- a/src/soc/intel/elkhartlake/gpio.c +++ b/src/soc/intel/elkhartlake/gpio.c @@ -226,7 +226,6 @@ { PMC_GPP_C, GPP_C }, { PMC_GPP_E, GPP_E }, { PMC_GPP_G, GPP_G }, - { PMC_GPP_S, GPP_S } }; *num = ARRAY_SIZE(routes); diff --git a/src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h b/src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h index 33fcb6b..0aefe96 100644 --- a/src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h @@ -10,19 +10,18 @@ */ #define GPP_B 0x0 #define GPP_T 0x1 -#define GPP_D 0x2 -#define GPP_A 0x3 -#define GPP_R 0x4 +#define GPP_A 0x2 +#define GPP_R 0x3 +#define GPD 0x4 #define GPP_V 0x5 -#define GPD 0x6 -#define GPP_H 0x7 +#define GPP_H 0x6 +#define GPP_D 0x7 #define GPP_U 0x8 #define VGPIO 0x9 #define GPP_F 0xA #define GPP_C 0xB #define GPP_E 0xC #define GPP_G 0xD -#define GPP_S 0xE #define GPIO_NUM_GROUPS 15 #define GPIO_MAX_NUM_PER_GROUP 32 diff --git a/src/soc/intel/elkhartlake/include/soc/pmc.h b/src/soc/intel/elkhartlake/include/soc/pmc.h index 1c8cb1a..a20d6fe 100644 --- a/src/soc/intel/elkhartlake/include/soc/pmc.h +++ b/src/soc/intel/elkhartlake/include/soc/pmc.h @@ -105,19 +105,18 @@ #define PMC_GPP_B 0x0 #define PMC_GPP_T 0x1 -#define PMC_GPP_D 0x2 -#define PMC_GPP_A 0x3 -#define PMC_GPP_R 0x4 +#define PMC_GPP_A 0x2 +#define PMC_GPP_R 0x3 +#define PMC_GPD 0x4 #define PMC_GPP_V 0x5 -#define PMC_GPD 0x6 -#define PMC_GPP_H 0x7 +#define PMC_GPP_H 0x6 +#define PMC_GPP_D 0x7 #define PMC_GPP_U 0x8 #define PMC_VGPIO 0x9 #define PMC_GPP_F 0xA #define PMC_GPP_C 0xB #define PMC_GPP_E 0xC #define PMC_GPP_G 0xD -#define PMC_GPP_S 0xE #define GBLRST_CAUSE0 0x1924 #define GBLRST_CAUSE0_THERMTRIP (1 << 5) -- To view, visit https://review.coreboot.org/c/coreboot/+/87050?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I910f3c4c0d31b8d24b83cd2c3a28688b898b5d9f Gerrit-Change-Number: 87050 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com>

1 0

[XS] Change in coreboot[main]: mb/protectli/vault_ehl/devicetree.cb: Fix assertion in soc/pmutil
by Michał Żygowski (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Piotr Król. Hello Piotr Król, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87049?usp=email to look at the new patch set (#2). Change subject: mb/protectli/vault_ehl/devicetree.cb: Fix assertion in soc/pmutil ...................................................................... mb/protectli/vault_ehl/devicetree.cb: Fix assertion in soc/pmutil The SoC code requires or GPE DW config values to be different. Assign the default values of PMC GPIO_CONF register as GPIO GPEs are not used on this platform. Fixes the assertion in soc/intel/elkhartalke/pmutil. TEST=Boot Protectli VP2420 to Ubuntu 24.04. Change-Id: Ibf4a1f52bf970c27d0ca8dd1b1377d6a5e6477f9 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/protectli/vault_ehl/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/87049/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87049?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibf4a1f52bf970c27d0ca8dd1b1377d6a5e6477f9 Gerrit-Change-Number: 87049 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com>

1 0

[XS] Change in coreboot[main]: mb/protectli/vault_ehl/devicetree.cb: Fix assertion in soc/pmutil
by Michał Żygowski (Code Review) 31 Mar '25

31 Mar '25

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87049?usp=email ) Change subject: mb/protectli/vault_ehl/devicetree.cb: Fix assertion in soc/pmutil ...................................................................... mb/protectli/vault_ehl/devicetree.cb: Fix assertion in soc/pmutil The SoC code requires or GPE DW config values to be different. Assign the default values of PMC GPIO_CONF register as GPIO GPEs are not used on this platform. Fixes the assertion in soc/intel/elkhartalke/pmutil. TEST=Boot Protectli VP2420 to Ubuntu 24.02. Change-Id: Ibf4a1f52bf970c27d0ca8dd1b1377d6a5e6477f9 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/protectli/vault_ehl/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/87049/1 diff --git a/src/mainboard/protectli/vault_ehl/devicetree.cb b/src/mainboard/protectli/vault_ehl/devicetree.cb index 10782b2..0db005f 100644 --- a/src/mainboard/protectli/vault_ehl/devicetree.cb +++ b/src/mainboard/protectli/vault_ehl/devicetree.cb @@ -18,9 +18,9 @@ # route, i.e., if this route changes then the affected GPE # offset bits also need to be changed. This sets the PMC register # GPE_CFG fields. - #register "pmc_gpe0_dw1" = "PMC_GPE_SCC_63_32" - #register "pmc_gpe0_dw2" = "PMC_GPE_N_31_0" - #register "pmc_gpe0_dw3" = "PMC_GPE_SCC_31_0" + register "pmc_gpe0_dw0" = "PMC_GPP_A" + register "pmc_gpe0_dw1" = "PMC_GPP_R" + register "pmc_gpe0_dw2" = "PMC_GPD" register "tcc_offset" = "5" # TCC of 95C -- To view, visit https://review.coreboot.org/c/coreboot/+/87049?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibf4a1f52bf970c27d0ca8dd1b1377d6a5e6477f9 Gerrit-Change-Number: 87049 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>

1 0

[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Keith Hui (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Angel Pons, Bill XIE, Nicholas Chin. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 7: (2 comments) Patchset: PS7: Guys, as I wrote on the mailing list, I am getting real close to actually implement the whole thing. Looks like sb/intel/bd82x6x already included the SPI_FLASH Kconfig and related stuff. But how do I use the functions in drivers/spi/spi_flash.c? Or am I better off reinventing the wheel? File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c: https://review.coreboot.org/c/coreboot/+/85413/comment/1de572e6_5ea66271?us… : PS7, Line 104: 0x40 > Unfortunately, as https://ticket.coreboot.org/attachments/487 shows, my board is rev 1. […] Your photo shows the same six transistors as my boardview, they are: QSWQ7 QSWQ4 QSWQ6 QSWQ8 QSWQ3 QSWQ5 Pin 3 of Q7 is SEL4. You can find SEL2 at pin 3 of Q3, and SEL3 at pin 3 of Q5. https://ticket.coreboot.org/attachments/489 uploaded with marks showing where to probe instead. (As you can see, QSWQ8 is not there, but it doesn't matter.) -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 7 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 31 Mar 2025 11:10:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

1 0

[M] Change in coreboot[main]: soc/amd/common/block/lpc: Use ROM3 window if possible
by Patrick Rudolph (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Maximilian Brune, Paul Menzel, Varshit Pandya. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86584?usp=email ) Change subject: soc/amd/common/block/lpc: Use ROM3 window if possible ...................................................................... Patch Set 11: (1 comment) File src/soc/amd/common/block/spi/mmap_boot_rom3.c: https://review.coreboot.org/c/coreboot/+/86584/comment/d4347ae7_3417cacb?us… : PS11, Line 62: * 0 +------------+ ------------------------------0xFF0000000--+--------------+- rom2_start > hmm, i don't like that smmstorev2 interface design too much and i still don't think that we should o […] Document 56780 describes the remapping for ROM3 as well. Reading through the document it sounds remapping isn't yet supported. You would need another valid EFS in the second 16MByte page as well as all necessary structures to boot (FMAP, CBFS, ...). -- To view, visit https://review.coreboot.org/c/coreboot/+/86584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8976273cfb31765d7f893b3fc137f117c63b6553 Gerrit-Change-Number: 86584 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 31 Mar 2025 10:20:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[M] Change in coreboot[main]: soc/amd/glinda/cpu: Compute total L3 cache size
by Marvin Drees (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Angel Pons, Naresh Solanki. Marvin Drees has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email ) Change subject: soc/amd/glinda/cpu: Compute total L3 cache size ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 9 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Mon, 31 Mar 2025 10:08:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: arch/x86/cpu: Add helper function to compute cache
by Marvin Drees (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Andy Ebrahiem, Angel Pons, Felix Held, Jincheng Li, Jérémy Compostella, Maximilian Brune, Naresh Solanki, Patrick Rudolph, Shuo Liu. Marvin Drees has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85638?usp=email ) Change subject: arch/x86/cpu: Add helper function to compute cache ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449 Gerrit-Change-Number: 85638 Gerrit-PatchSet: 7 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: NyeonWoo Kim Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 31 Mar 2025 10:07:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING
by Subrata Banik (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Gareth Yu, Gareth Yu, Jayvik Desai, Kapil Porwal, Lawrence Chang, Nick Vaccaro, Paul Menzel, SH Kim, Simon Yang. Subrata Banik has posted comments on this change by Lawrence Chang. ( https://review.coreboot.org/c/coreboot/+/86838?usp=email ) Change subject: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING ...................................................................... Patch Set 26: (3 comments) File src/mainboard/google/brya/variants/meliks/ramstage.c: https://review.coreboot.org/c/coreboot/+/86838/comment/f47c7c18_d12e8b03?us… : PS26, Line 24: ``` static void igd_set_mem_base(uint32_t base) { pci_write_config32(SA_DEVFN_IGD, PCI_BASE_ADDRESS_0, base); igd_cmd = pci_read_config16(SA_DEVFN_IGD, PCI_COMMAND); pci_write_config16(SA_DEVFN_IGD, PCI_BASE_ADDRESS_0, igd_cmd | PCI_COMMAND_MEMORY); } ``` https://review.coreboot.org/c/coreboot/+/86838/comment/04c47222_cfe97bd7?us… : PS26, Line 31: if (!igd_base) { : need_temp_bar = true; : igd_base = CONFIG_GFX_GMA_DEFAULT_MMIO; : pci_write_config32(SA_DEVFN_IGD, PCI_BASE_ADDRESS_0, igd_base); : igd_cmd = pci_read_config16(SA_DEVFN_IGD, PCI_COMMAND); : pci_write_config16(SA_DEVFN_IGD, PCI_BASE_ADDRESS_0, igd_cmd | PCI_COMMAND_MEMORY); : } ``` if (!igd_base) { need_temp_bar = true; igd_set_mem_base(CONFIG_GFX_GMA_DEFAULT_MMIO); } ``` https://review.coreboot.org/c/coreboot/+/86838/comment/9599be65_7b956f37?us… : PS26, Line 41: if (need_temp_bar) { : pci_write_config16(SA_DEVFN_IGD, PCI_COMMAND, igd_cmd & ~PCI_COMMAND_MEMORY); : pci_write_config32(SA_DEVFN_IGD, PCI_BASE_ADDRESS_0, 0); : } ``` if (need_temp_bar) igd_set_mem_base(0); ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/86838?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7857c4f71fc7d1d0c5069a462bdd70c8dbb78179 Gerrit-Change-Number: 86838 Gerrit-PatchSet: 26 Gerrit-Owner: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Gareth Yu <gareth.yu(a)intel.com> Gerrit-Reviewer: Gareth Yu <gareth.yu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Gareth Yu <gareth.yu(a)intel.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Gareth Yu <gareth.yu(a)intel.com> Gerrit-Attention: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 31 Mar 2025 09:50:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[M] Change in coreboot[main]: mb/cwwk: Add CWWK CW-ADLNTB-1C2L-V3.0 board as an adl variants
by Julian Intronati (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Angel Pons, Brandon Weeks, Felix Held, Paul Menzel. Julian Intronati has posted comments on this change by Julian Intronati. ( https://review.coreboot.org/c/coreboot/+/87027?usp=email ) Change subject: mb/cwwk: Add CWWK CW-ADLNTB-1C2L-V3.0 board as an adl variants ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/87027?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia0553141b41717b560042de1136d53b9c3cf7a69 Gerrit-Change-Number: 87027 Gerrit-PatchSet: 2 Gerrit-Owner: Julian Intronati <julian.intronati(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Brandon Weeks <bweeks(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julian Intronati <julian.intronati(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Brandon Weeks <bweeks(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 31 Mar 2025 09:45:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: mb/starlabs/starbook/mtl: Add the option to enable the VPU
by Sean Rhodes (Code Review) 31 Mar '25

31 Mar '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87046?usp=email ) Change subject: mb/starlabs/starbook/mtl: Add the option to enable the VPU ...................................................................... mb/starlabs/starbook/mtl: Add the option to enable the VPU Enable the VPU, and add a CFR option to enable or disable it. Change-Id: I747d85c6764e5affcc202e063abe7ec786d04e39 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87046 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/cfr.c M src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb M src/mainboard/starlabs/starbook/variants/mtl/devtree.c 3 files changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c index 1e08ba1..ac34906 100644 --- a/src/mainboard/starlabs/starbook/cfr.c +++ b/src/mainboard/starlabs/starbook/cfr.c @@ -185,6 +185,15 @@ }); #endif +#if CONFIG(SOC_INTEL_METEORLAKE) +static const struct sm_object vpu = SM_DECLARE_BOOL({ + .opt_name = "vpu", + .ui_name = "VPU", + .ui_helptext = "Enable or disable VPU", + .default_value = true, +}); +#endif + static const struct sm_object webcam = SM_DECLARE_BOOL({ .opt_name = "webcam", .ui_name = "Webcam", @@ -266,6 +275,9 @@ #if CONFIG(DRIVERS_INTEL_USB4_RETIMER) &thunderbolt, #endif + #if CONFIG(SOC_INTEL_METEORLAKE) + &vpu, + #endif &webcam, &wireless, NULL diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb index 43bcd0f..9cd7831 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb @@ -171,6 +171,7 @@ device i2c 2c on end end end + device ref vpu on end device ref ioe_shared_sram on end device ref pmc_shared_sram on end device ref pcie_rp9 on # WiFi diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c index c329bac..69406c7 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c @@ -20,6 +20,7 @@ &cfg->power_limits_config[MTL_P_682_482_CORE]; struct device *gna_dev = pcidev_on_root(0x08, 0); + struct device *vpu_dev = pcidev_on_root(0x0b, 0); uint8_t performance_scale = 100; @@ -63,4 +64,8 @@ /* Enable/Disable GNA based on CMOS settings */ if (get_uint_option("gna", 0) == 0) gna_dev->enabled = 0; + + /* Enable/Disable VPU based on CMOS settings */ + if (get_uint_option("vpu", 0) == 0) + vpu_dev->enabled = 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/87046?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I747d85c6764e5affcc202e063abe7ec786d04e39 Gerrit-Change-Number: 87046 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2025