coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/fatcat/var/fatcat: Update GSPIO CS pin
by Jayvik Desai (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Andy Ebrahiem, Henry Barnor, Kapil Porwal, Paul Menzel, Pranava Y N, Subrata Banik. Hello Andy Ebrahiem, Henry Barnor, Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86480?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Andy Ebrahiem, Verified+1 by build bot (Jenkins) Change subject: mb/fatcat/var/fatcat: Update GSPIO CS pin ...................................................................... mb/fatcat/var/fatcat: Update GSPIO CS pin Update GPIO CS0 pin from GPP_F18 to GPP_E17 BUG=b:395147436 TEST=build fatcat Change-Id: I9d80e163fd4e3e21cc153091bb40763e78d6c595 Signed-off-by: Jayvik Desai <jayvik(a)google.com> --- M src/mainboard/google/fatcat/variants/fatcat/fw_config.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/86480/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86480?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9d80e163fd4e3e21cc153091bb40763e78d6c595 Gerrit-Change-Number: 86480 Gerrit-PatchSet: 4 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Henry Barnor <hbarnor(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Henry Barnor <hbarnor(a)chromium.org>

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[XS] Change in coreboot[main]: device/dram/ddr5.c: Add 7500 MT/s support
by Maximilian Brune (Code Review) 20 Feb '25

20 Feb '25

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86543?usp=email ) Change subject: device/dram/ddr5.c: Add 7500 MT/s support ...................................................................... device/dram/ddr5.c: Add 7500 MT/s support Change-Id: I141f63c4fc505a9e16eed132a9a550441f4ad68d Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/device/dram/ddr5.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/86543/1 diff --git a/src/device/dram/ddr5.c b/src/device/dram/ddr5.c index b546abf..90b67f8 100644 --- a/src/device/dram/ddr5.c +++ b/src/device/dram/ddr5.c @@ -21,6 +21,7 @@ DDR5_5500, DDR5_6000, DDR5_6400, + DDR5_7500, }; struct ddr5_speed_attr { @@ -108,6 +109,11 @@ .max_clock_mhz = 3200, .reported_mts = 6400 }, + [DDR5_7500] = { + .min_clock_mhz = 3201, + .max_clock_mhz = 3750, + .reported_mts = 7500 + }, }; /** -- To view, visit https://review.coreboot.org/c/coreboot/+/86543?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I141f63c4fc505a9e16eed132a9a550441f4ad68d Gerrit-Change-Number: 86543 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XS] Change in coreboot[main]: libpayload/tests: Remove reference to non-existent files
by Maximilian Brune (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Elyes Haouas. Maximilian Brune has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/86536?usp=email ) Change subject: libpayload/tests: Remove reference to non-existent files ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86536?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id2cec6a56ba5ce98832aced6fc2cfd8ebda91f02 Gerrit-Change-Number: 86536 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 20 Feb 2025 17:30:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: sb/intel/common: Add GPIO serial blink console support
by Keith Hui (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Nicholas Chin, Paul Menzel. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/86390?usp=email ) Change subject: sb/intel/common: Add GPIO serial blink console support ...................................................................... Patch Set 3: (6 comments) Patchset: PS3: I'm no native English speaker either, so I ran the text through an online grammar checker. File Documentation/technotes/console.md: https://review.coreboot.org/c/coreboot/+/86390/comment/9313f0d0_f342e0c3?us… : PS2, Line 177: a LED > an LED Done https://review.coreboot.org/c/coreboot/+/86390/comment/5f6d360c_00da7cbb?us… : PS2, Line 178: pulls > pull (without s)? Done https://review.coreboot.org/c/coreboot/+/86390/comment/e761be04_6bdaf574?us… : PS2, Line 182: > No space. Done https://review.coreboot.org/c/coreboot/+/86390/comment/4e5f9243_8083b433?us… : PS2, Line 183: to base your circuit off of > Sounds strange, but I am no native speaker. Done File src/console/Kconfig: https://review.coreboot.org/c/coreboot/+/86390/comment/e212ac7a_30232b08?us… : PS2, Line 405: an > a Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86390?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0741142fe21eba4989d28b96e795d3bfa3085466 Gerrit-Change-Number: 86390 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 17:20:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: sb/intel/common: Add GPIO serial blink console support
by Keith Hui (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Keith Hui, Nicholas Chin. Hello Intel coreboot Reviewers, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86390?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: sb/intel/common: Add GPIO serial blink console support ...................................................................... sb/intel/common: Add GPIO serial blink console support Intel ICH/PCHs from ICH8 onwards have the ability to blink arbitrary messages (in this case, our console) onto a GPIO line. Idea is to place an optical sensor over an LED controlled by the GPIO line with serial blink enabled to "watch" the blinking and extract the messages. Add support and documentation for serializing coreboot console over this channel. Change-Id: I0741142fe21eba4989d28b96e795d3bfa3085466 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M Documentation/technotes/console.md M src/console/Kconfig M src/console/console.c M src/include/console/console.h A src/include/console/gpsb.h M src/southbridge/intel/common/Makefile.mk M src/southbridge/intel/common/gpio.c M src/southbridge/intel/common/gpio.h A src/southbridge/intel/common/gpsb.c 9 files changed, 225 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/86390/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86390?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0741142fe21eba4989d28b96e795d3bfa3085466 Gerrit-Change-Number: 86390 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com>

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[M] Change in coreboot[main]: Documentation: Update console technotes
by Keith Hui (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Keith Hui. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86389?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Documentation: Update console technotes ...................................................................... Documentation: Update console technotes coreboot wiki is no more. Using hints from Wayback Machine and various sources within coreboot, replace the dead link with actual content, updated with a modern take. Change-Id: I83202a69a26b27bd92113e86d04f1a7b0adb1e6c Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M Documentation/technotes/console.md 1 file changed, 95 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/86389/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86389?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I83202a69a26b27bd92113e86d04f1a7b0adb1e6c Gerrit-Change-Number: 86389 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training
by Subrata Banik (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Vikrant L Jadeja. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email ) Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training ...................................................................... Patch Set 21: (1 comment) File src/soc/intel/pantherlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/85454/comment/591a0e87_476d721e?us… : PS21, Line 387: m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING); > After a good night's sleep, I realize that I want to align with your opinion of not pursuing such an endeavor. There is just so much duplication between all the `soc/intel/[...]lake/*` and, in particular, the `fsp_params.c` that it is tempting to find ways to suppress some of them. > > As annoying as it is, if we were to look into ways of improving code sharing in this area, I would stay away from the `fsp_params.c` because User Product Data (UPDs) are outside our control. Common code, even if slightly impacted, would quickly become unmanageable. > > If we were to start looking into reducing code duplication, and I am all for it, I would recommend starting with `soc/intel/*/pmc.c`, `soc/intel/*/reset.c`, or `soc/intel/*/retimer.c`. > > I am marking this as resolved and abandoning my refactoring changelist (CL). Thanks for your understanding. I agree that we should focus on optimizing the redundant code pieces you listed in your previous response, rather than optimizing the FSP-UPD-based SoC code. -- To view, visit https://review.coreboot.org/c/coreboot/+/85454?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367 Gerrit-Change-Number: 85454 Gerrit-PatchSet: 21 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 17:06:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE
by Jérémy Compostella (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Felix Singer, Filip Lewiński, Intel coreboot Reviewers, Krystian Hebel, Martin Roth, Michał Kopeć, Michał Żygowski, Paul Menzel. Jérémy Compostella has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/83730?usp=email ) Change subject: soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE ...................................................................... Patch Set 8: Code-Review+1 (1 comment) File src/soc/intel/cannonlake/lockdown.c: https://review.coreboot.org/c/coreboot/+/83730/comment/8bc902b5_0ad4617e?us… : PS8, Line 3: #include <cpu/x86/msr.h> : #include <cpu/intel/msr.h> I know this is not a formal rule, but implicitly we generally try to keep the header file inclusion alphabetically ordered. -- To view, visit https://review.coreboot.org/c/coreboot/+/83730?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ed4382bbe68f03e8eca151245c13928609f434f Gerrit-Change-Number: 83730 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-CC: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 16:37:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: arch/x86/acpi_bert: Add spinlock
by Jérémy Compostella (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Patrick Rudolph. Jérémy Compostella has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86539?usp=email ) Change subject: arch/x86/acpi_bert: Add spinlock ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Did you observe any corruption situation that this patch is addressing that you could document in the commit message? -- To view, visit https://review.coreboot.org/c/coreboot/+/86539?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab484149ef00797e1846441fb93407fe05ac8abb Gerrit-Change-Number: 86539 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 16:30:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings
by Jérémy Compostella (Code Review) 20 Feb '25

20 Feb '25

Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/86532?usp=email ) Change subject: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: After a good night's sleep, I realize that I want to align with your opinion of not pursuing such an endeavor. There is just so much duplication between all the `soc/intel/[...]lake/*` and, in particular, the `fsp_params.c` that it is tempting to find ways to suppress some of them. As annoying as it is, if we were to look into ways of improving code sharing in this area, I would stay away from the `fsp_params.c` because User Product Data (UPDs) are outside our control. Common code, even if slightly impacted, would quickly become unmanageable. If we were to start looking into reducing code duplication, and I am all for it, I would recommend starting with `soc/intel/*/pmc.c`, `soc/intel/*/reset.c`, or `soc/intel/*/retimer.c`. -- To view, visit https://review.coreboot.org/c/coreboot/+/86532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03506fbc49ea5b86ce65fe2afbf692b6708a87c5 Gerrit-Change-Number: 86532 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 20 Feb 2025 16:24:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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coreboot-gerrit February 2025