coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

1 participants
2886 discussions

[S] Change in coreboot[main]: mb/starlabs/starlite_adl: Reconfigure the vGPIO's for CNVi BT
by Matt DeVillier (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86387?usp=email ) Change subject: mb/starlabs/starlite_adl: Reconfigure the vGPIO's for CNVi BT ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86387?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d1c337523450de41f11fc9bfbc9b52825d7311c Gerrit-Change-Number: 86387 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 20 Feb 2025 16:23:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings
by Jérémy Compostella (Code Review) 20 Feb '25

20 Feb '25

Jérémy Compostella has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/86532?usp=email ) Change subject: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/86532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03506fbc49ea5b86ce65fe2afbf692b6708a87c5 Gerrit-Change-Number: 86532 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training
by Jérémy Compostella (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Kapil Porwal, Paul Menzel, Pranava Y N, Vikrant L Jadeja. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email ) Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training ...................................................................... Patch Set 21: (1 comment) File src/soc/intel/pantherlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/85454/comment/bac29505_b06ad67f?us… : PS21, Line 387: m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING); > > I have considered your point, and I agree with you that there is a slight leap of faith in the pro […] After a good night's sleep, I realize that I want to align with your opinion of not pursuing such an endeavor. There is just so much duplication between all the `soc/intel/[...]lake/*` and, in particular, the `fsp_params.c` that it is tempting to find ways to suppress some of them. As annoying as it is, if we were to look into ways of improving code sharing in this area, I would stay away from the `fsp_params.c` because User Product Data (UPDs) are outside our control. Common code, even if slightly impacted, would quickly become unmanageable. If we were to start looking into reducing code duplication, and I am all for it, I would recommend starting with `soc/intel/*/pmc.c`, `soc/intel/*/reset.c`, or `soc/intel/*/retimer.c`. I am marking this as resolved and abandoning my refactoring changelist (CL). -- To view, visit https://review.coreboot.org/c/coreboot/+/85454?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367 Gerrit-Change-Number: 85454 Gerrit-PatchSet: 21 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 16:23:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: security: Allow vboot when INTEL_TXT enabled
by Filip Lewiński (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Christian Walter, Julius Werner, Krystian Hebel, Michał Żygowski. Filip Lewiński has posted comments on this change by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/82695?usp=email ) Change subject: security: Allow vboot when INTEL_TXT enabled ...................................................................... Patch Set 17: (1 comment) File src/lib/bootblock.c: https://review.coreboot.org/c/coreboot/+/82695/comment/fcfeb93e_81a00596?us… : PS5, Line 62: if (CONFIG(TPM_MEASURED_BOOT_INIT_BOOTBLOCK) && !CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) { > @jwerner@chromium.org Thank you for your detailed feedback and patience in this discussion. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82695?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19dc3d910c23fcfd8732465c488f47dd86a96781 Gerrit-Change-Number: 82695 Gerrit-PatchSet: 17 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 16:18:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Filip Lewiński <filip.lewinski(a)3mdeb.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[M] Change in coreboot[main]: security/intel/txt: Verify Intel TXT required TPM2 indices presence
by Filip Lewiński (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Arthur Heymans, Felix Singer, Julius Werner, Krystian Hebel, Martin Roth, Michał Kopeć, Michał Żygowski, Yu-Ping Wu. Filip Lewiński has posted comments on this change by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/82417?usp=email ) Change subject: security/intel/txt: Verify Intel TXT required TPM2 indices presence ...................................................................... Patch Set 12: (3 comments) File src/security/intel/txt/common.c: https://review.coreboot.org/c/coreboot/+/82417/comment/d0c02c1a_558dc560?us… : PS11, Line 14: #include <security/tpm/tss.h> > Keep includes ordered alphabetically. [Moved](https://review.coreboot.org/c/coreboot/+/82417/11..12/src/security/i… https://review.coreboot.org/c/coreboot/+/82417/comment/9af1be47_d7cd392a?us… : PS11, Line 426: /* The index could have been written already, but we don't need to care. */ > Can it _not_ be written? Further code compares it against known value, so it must have a content. [Removed](https://review.coreboot.org/c/coreboot/+/82417/11..12/src/security… https://review.coreboot.org/c/coreboot/+/82417/comment/2d202e4a_2fa06550?us… : PS11, Line 458: /* The index could have been written already, but we don't need to care. */ > Same as above. [Removed](https://review.coreboot.org/c/coreboot/+/82417/11..12/src/security…, as above -- To view, visit https://review.coreboot.org/c/coreboot/+/82417?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5b4267b2d51e21cfa514e96301f30ebf7437c470 Gerrit-Change-Number: 82417 Gerrit-PatchSet: 12 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 16:16:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com>

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[M] Change in coreboot[main]: security/intel/txt: Verify Intel TXT required TPM2 indices presence
by Filip Lewiński (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Arthur Heymans, Felix Singer, Filip Lewiński, Julius Werner, Martin Roth, Michał Kopeć, Michał Żygowski, Yu-Ping Wu. Hello Arthur Heymans, Felix Singer, Julius Werner, Krystian Hebel, Martin Roth, Michał Kopeć, Michał Żygowski, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82417?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: security/intel/txt: Verify Intel TXT required TPM2 indices presence ...................................................................... security/intel/txt: Verify Intel TXT required TPM2 indices presence If required TPM2 indices are not present, the SCHECK will cause a reset, which will result in a reset-loop. Unable to boot any operating-system or shell environment to provision a TPM, one ends up in a soft-brick. Avoid it by checkign the TPM2 indices presence and skip SCHECK if indices not found. Better to leave Intel TXT uninitialized rather than having a reset loop. Change-Id: I5b4267b2d51e21cfa514e96301f30ebf7437c470 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/security/intel/txt/common.c 1 file changed, 90 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/82417/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/82417?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5b4267b2d51e21cfa514e96301f30ebf7437c470 Gerrit-Change-Number: 82417 Gerrit-PatchSet: 12 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE
by Filip Lewiński (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Felix Singer, Intel coreboot Reviewers, Jérémy Compostella, Krystian Hebel, Martin Roth, Michał Kopeć, Michał Żygowski, Paul Menzel. Filip Lewiński has uploaded a new patch set (#8) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/83730?usp=email ) Change subject: soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE ...................................................................... soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE Intel TXT requires the debug interface to be disabled. There is no way to program the MSR_IA32_DEBUG_INTERFACE using FSP as needed, so let coreboot handle it. TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled Change-Id: I7ed4382bbe68f03e8eca151245c13928609f434f Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/include/cpu/intel/msr.h M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/lockdown.c 3 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/83730/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/83730?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ed4382bbe68f03e8eca151245c13928609f434f Gerrit-Change-Number: 83730 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-CC: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com>

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[S] Change in coreboot[main]: soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE
by Filip Lewiński (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Felix Singer, Intel coreboot Reviewers, Jérémy Compostella, Krystian Hebel, Martin Roth, Michał Kopeć, Michał Żygowski, Paul Menzel. Filip Lewiński has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/83730?usp=email ) Change subject: soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE ...................................................................... Patch Set 7: (4 comments) File src/include/cpu/intel/msr.h: https://review.coreboot.org/c/coreboot/+/83730/comment/3318ffab_ff4c9d7d?us… : PS6, Line 19: #define MSR_IA32_DEBUG_INTERFACE 0xc80 > It seems to be an extra tab […] [Done](https://review.coreboot.org/c/coreboot/+/83730/6..7/src/include/cpu/i… File src/soc/intel/cannonlake/lockdown.c: https://review.coreboot.org/c/coreboot/+/83730/comment/10ebfdad_21d25aca?us… : PS6, Line 11: #define MSR_IA32_DEBUG_INTERFACE_EN (1 << 0) : #define MS > Shouldn't it be in src/include/cpu/intel/msr.h ? […] I've [moved](https://review.coreboot.org/c/coreboot/+/83730/6..7/src/include/cpu/… them to `msr.h`. From what I can see, none of the defines there use the BIT() macro. Should we be consistent with the rest of the file, or would you like me to update all of them? https://review.coreboot.org/c/coreboot/+/83730/comment/7f43187a_a0e226fb?us… : PS6, Line 14: static void cpu_lockdown_cfg(void) > Could it be called `lock_debug_interface` instead ? [Done](https://review.coreboot.org/c/coreboot/+/83730/6..7/src/soc/intel/can… https://review.coreboot.org/c/coreboot/+/83730/comment/621e54ce_468563cc?us… : PS6, Line 18: if (!(msr.lo & MSR_IA32_DEBUG_INTERFACE_LOCK)) { > ``` […] [Done](https://review.coreboot.org/c/coreboot/+/83730/6..7/src/soc/intel/can… -- To view, visit https://review.coreboot.org/c/coreboot/+/83730?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ed4382bbe68f03e8eca151245c13928609f434f Gerrit-Change-Number: 83730 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-CC: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 15:58:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: mb/starlabs/starlite_adl: Reconfigure the vGPIO's for CNVi BT
by Sean Rhodes (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Sean Rhodes. Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86387?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/starlabs/starlite_adl: Reconfigure the vGPIO's for CNVi BT ...................................................................... mb/starlabs/starlite_adl: Reconfigure the vGPIO's for CNVi BT It seems FSP will only automatically configure the vGPIO's for CNVi Bluetooth if USB 2 Port 7 is used. On this board, USB 2 Port 9 is used, so manually confgiure the vGPIO's related to CNVi for USB Bluetooth instead of UART. Change-Id: I8d1c337523450de41f11fc9bfbc9b52825d7311c Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c 1 file changed, 21 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/86387/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/86387?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d1c337523450de41f11fc9bfbc9b52825d7311c Gerrit-Change-Number: 86387 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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[S] Change in coreboot[main]: soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE
by Filip Lewiński (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Felix Singer, Filip Lewiński, Intel coreboot Reviewers, Krystian Hebel, Martin Roth, Michał Kopeć, Michał Żygowski, Paul Menzel. Filip Lewiński has uploaded a new patch set (#7) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/83730?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE ...................................................................... soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE Intel TXT requires the debug interface to be disabled. There is no way to program the MSR_IA32_DEBUG_INTERFACE using FSP as needed, so let coreboot handle it. TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled Change-Id: I7ed4382bbe68f03e8eca151245c13928609f434f Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/include/cpu/intel/msr.h M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/lockdown.c 3 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/83730/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/83730?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ed4382bbe68f03e8eca151245c13928609f434f Gerrit-Change-Number: 83730 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-CC: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com>

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coreboot-gerrit February 2025