coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: mb/cwwk/adl: Various device tree fixes
by Brandon Weeks (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Brandon Weeks, Felix Held. Hello Felix Held, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86260?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Felix Held, Verified+1 by build bot (Jenkins) Change subject: mb/cwwk/adl: Various device tree fixes ......................................................................… [View More]

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[S] Change in coreboot[main]: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs
by Vince Liu (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Hung-Te Lin. Vince Liu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/86538?usp=email ) Change subject: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86538/comment/b10f1733_b1db68b9?us… : PS2, Line 12: This modification reduces the … [View More]

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[S] Change in coreboot[main]: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs
by Vince Liu (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Hung-Te Lin, Vince Liu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86538?usp=email to look at the new patch set (#3). Change subject: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs ...................................................................... soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR … [View More]

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[XS] Change in coreboot[main]: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info
by Jérémy Compostella (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Zhixing Ma. Jérémy Compostella has posted comments on this change by Zhixing Ma. ( https://review.coreboot.org/c/coreboot/+/85960?usp=email ) Change subject: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85960?usp=email To unsubscribe, or for help writing mail filters, visit https://… [View More]

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[XS] Change in coreboot[main]: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info
by Zhixing Ma (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Jérémy Compostella. Zhixing Ma has posted comments on this change by Zhixing Ma. ( https://review.coreboot.org/c/coreboot/+/85960?usp=email ) Change subject: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info ...................................................................... Patch Set 8: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85960/comment/183d6c70_51fde446?us… : PS7, Line 9: The current SMBIOS for fatcat is … [View More]missing processor upgrade info, > information […] Done https://review.coreboot.org/c/coreboot/+/85960/comment/f7c405c1_0b231f0e?us… : PS7, Line 10: This patch adds the missing value by enabling a kconfig flag. > which Kconfig flag ? Done https://review.coreboot.org/c/coreboot/+/85960/comment/b566cb35_06460ae4?us… : PS7, Line 12: https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/defau… > can't you give the direct link https://www.dmtf. […] This was requested by coreboot maintainers on similar patch prior. https://review.coreboot.org/c/coreboot/+/85960/comment/7df0c9ed_26983d2b?us… : PS7, Line 15: TEST=Boot and verified that SMBIOS processor upgrade value is correct. > I would keep the BUG and TEST tags at the end of the commit message. Done https://review.coreboot.org/c/coreboot/+/85960/comment/210013db_90cf9460?us… : PS7, Line 18: Processor Information > I would personally prefer a diff representation like […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85960?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ica92d15e4a6123f928fceb77c7638e4c45d6dc7d Gerrit-Change-Number: 85960 Gerrit-PatchSet: 8 Gerrit-Owner: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhixing Ma <zhixing.ma(a)intel.corp-partner.google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 23:10:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> [View Less]

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[XS] Change in coreboot[main]: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info
by Zhixing Ma (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Subrata Banik, Zhixing Ma. Hello Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85960?usp=email to look at the new patch set (#8). Change subject: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info ...................................................................... mainboard/google/… [View More]fatcat: Fix SMBIOS Processor upgrade info The current SMBIOS for fatcat is missing processor upgrade information. This patch adds the missing value by enabling kconfig flag CPU_INTEL_SOCKET_OTHER. Refer to SMBIOS spec sheet for documentation on cpu socket values: https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/defau… Output of dmidecode: Handle 0x0004, DMI type 4, 48 bytes Processor Information Socket Designation: CPU0 Type: Central Processor Family: Pentium Pro Manufacturer: GenuineIntel ID: C0 06 0C 00 FF FB EB BF Signature: Type 0, Family 6, Model 204, Stepping 0 Flags: ... Version: Genuine Intel(R) 0000 Voltage: Unknown External Clock: 100 MHz Max Speed: 3200 MHz Current Speed: 3000 MHz Status: Populated, Enabled - Upgrade: Unknown + Upgrade: Other BUG=NONE TEST=Boot and verified that SMBIOS processor upgrade value is correct. Change-Id: Ica92d15e4a6123f928fceb77c7638e4c45d6dc7d Signed-off-by: Zhixing Ma <zhixing.ma(a)intel.com> --- M src/mainboard/google/fatcat/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/85960/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/85960?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ica92d15e4a6123f928fceb77c7638e4c45d6dc7d Gerrit-Change-Number: 85960 Gerrit-PatchSet: 8 Gerrit-Owner: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhixing Ma <zhixing.ma(a)intel.corp-partner.google.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> [View Less]

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[S] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training
by Julius Werner (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Vikrant L Jadeja. Julius Werner has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training ..................… [View More].................................................... Patch Set 21: (1 comment) File src/soc/intel/pantherlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/85454/comment/b5da4c1f_c9a61bde?us… : PS21, Line 387: m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING); > > After a good night's sleep, I realize that I want to align with your opinion of not pursuing such […] Why not try Jérémy's solution for now and use it for as many generations as it works in? "common" doesn't need to mean "it has to work in every SoC from now till the end of forever". As long as it's common between at least two SoCs and it's a large enough piece of code worth deduplicating, you can factor it out into common code. Just call the file `common/fsp_esol.c` for now, and if they eventually change the UPDs you can rename it to `common/fsp_esol_2025.c` and put a `common/fsp_esol_2028.c` or whatever with the new implementation next to it (or whatever other version distinguisher seems suitable for that). Then each SoC just needs to select the version that's applicable to them, but we still duplicate less code than if we had kept a separate copy for each SoC. (Compare, for example, how there's a `dpm_v1.c` and `dpm_v2.c` in `src/soc/mediatek/common`. `mt8188`, `mt8192` and `mt8195` refer to `dpm_v1.c` in their Makefiles, and `mt8196` and later will use `dpm_v2.c`. On the Arm boards we just tend to pull in common `.c` files from the SoC-specific Makefile so this pick-and-choose approach becomes particularly easy, but you can achieve the same with SoC-selected Kconfigs if you prefer too.) -- To view, visit https://review.coreboot.org/c/coreboot/+/85454?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367 Gerrit-Change-Number: 85454 Gerrit-PatchSet: 21 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 21:55:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> [View Less]

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[XS] Change in coreboot[main]: mb/google/nissa/var/pujjoniru: Modify the gpio of GPIO_PCH_WP
by Dinesh Gehlot (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Qinghong Zeng, Subrata Banik, hualin wei. Dinesh Gehlot has posted comments on this change by hualin wei. ( https://review.coreboot.org/c/coreboot/+/86510?usp=email ) Change subject: mb/google/nissa/var/pujjoniru: Modify the gpio of GPIO_PCH_WP ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/… [View More]86510/comment/744229b0_33f3b6ad?us… : PS3, Line 15: Build coreboot, flash, boot to : and log into kernel, execute "wp enable" in console, : execute "crossystem" at kernel prompt and verify that "wpsw_cur" : shows as being "1", Execute "wp disable" in console, execute : "crossystem" at kernel prompt and verify "wpsw_cur" is 0. wp status update verified by toggling it on and off. File src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h: https://review.coreboot.org/c/coreboot/+/86510/comment/f6f113ab_31c94963?us… : PS3, Line 14: #if CONFIG(BOARD_GOOGLE_PUJJONIRU) : #define GPIO_PCH_WP GPP_E17 : #else : #define GPIO_PCH_WP GPP_E12 : #endif Instead of adding a condition to the baseboard, we can update the WP GPIO at a specific variant level. In this case, we can update `pujjoniru/include/variant/gpio.h` as below ``` #undef GPIO_PCH_WP #define GPIO_PCH_WP GPP_E17 ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/86510?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iee76fa8b357aa472699f17789b2c718028f812a3 Gerrit-Change-Number: 86510 Gerrit-PatchSet: 3 Gerrit-Owner: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cindy Lu <luyi8(a)huaqin.corp-partner.google.com> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 20:47:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No [View Less]

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[XS] Change in coreboot[main]: libpayload/tests: Remove reference to non-existent files
by Julius Werner (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Elyes Haouas. Julius Werner has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/86536?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: libpayload/tests: Remove reference to non-existent files ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Removing that still makes this test not build … [View More]

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[XS] Change in coreboot[main]: google/fatcat/var/fatcat: Update GSPI0 CS pin
by Jayvik Desai (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Andy Ebrahiem, Henry Barnor, Kapil Porwal, Paul Menzel, Pranava Y N, Subrata Banik. Hello Andy Ebrahiem, Henry Barnor, Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86480?usp=email to look at the new patch set (#5). Change subject: google/fatcat/var/fatcat: Update GSPI0 CS pin ..................................................................… [View More]

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coreboot-gerrit February 2025