coreboot-gerrit February 2025

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Adjust and save HW protect temperature to SRAM
by Jarried Lin (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86533?usp=email ) Change subject: soc/mediatek/mt8196: Adjust and save HW protect temperature to SRAM ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Please split the patch into two. […] Hi yidi, Please review: https://review.coreboot.org/c/coreboot/+/86551 https://review.coreboot.org/c/coreboot/+/86552 abandon this patch -- To view, visit https://review.coreboot.org/c/coreboot/+/86533?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied0a7e710e77a4e74372590374f9342c5edc9122 Gerrit-Change-Number: 86533 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 21 Feb 2025 07:08:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Disable HWRot's clocks
by Jarried Lin (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86553?usp=email ) Change subject: soc/mediatek/mt8196: Disable HWRot's clocks ...................................................................... soc/mediatek/mt8196: Disable HWRot's clocks HWRot(Hardware Root of trust) are not used, so we disable its clocks to save power. BRANCH=rauru BUG=b:377628718 TEST=Bootup OK & Suspend/Resume OK Signed-off-by: Guangjie Song <guangjie.song(a)mediatek.com> Change-Id: I25e607e8e8b2d52608d279e1862f423ca50aab6a --- M src/soc/mediatek/mt8196/pll.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/86553/1 diff --git a/src/soc/mediatek/mt8196/pll.c b/src/soc/mediatek/mt8196/pll.c index 2007197..91d2fed 100644 --- a/src/soc/mediatek/mt8196/pll.c +++ b/src/soc/mediatek/mt8196/pll.c @@ -1628,14 +1628,14 @@ write32(&mtk_topckgen->clk_cfg[12].set, 0x80800000); write32(&mtk_topckgen->clk_cfg[15].set, 0x8000); write32(&mtk_topckgen->clk_cfg[16].set, 0x800000); - write32(&mtk_topckgen->clk_cfg[18].set, 0x80000000); + write32(&mtk_topckgen->clk_cfg[18].set, 0x80800000); write32(&mtk_topckgen->clk_cfg[19].set, 0x80808000); write32(&mtk_topckgen->clk_cfg[20].set, 0x80808080); write32(&mtk_topckgen->clk_cfg[21].set, 0x80808080); write32(&mtk_topckgen->clk_cfg[22].set, 0x80); write32(&mtk_vlpsys->vlp_clk_cfg[6].set, 0x80); - write32(&mtk_vlpsys->vlp_clk_cfg[10].set, 0x80800000); + write32(&mtk_vlpsys->vlp_clk_cfg[10].set, 0x80808000); write32(&mtk_vlpsys->vlp_clk_cfg[11].set, 0x80); write32(&mtk_topckgen2->cksys2_clk_cfg[0].set, 0x80808080); -- To view, visit https://review.coreboot.org/c/coreboot/+/86553?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I25e607e8e8b2d52608d279e1862f423ca50aab6a Gerrit-Change-Number: 86553 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Adjust HW protect temperature
by Jarried Lin (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu, Zhaoqing Jiu. Hello Zhaoqing Jiu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/86552?usp=email to review the following change. Change subject: soc/mediatek/mt8196: Adjust HW protect temperature ...................................................................... soc/mediatek/mt8196: Adjust HW protect temperature Adjust HW protect temperature so HW will trigger interrupt at expected trip point. BRANCH=rauru BUG=b:389026545 TEST=Boot up and check temperature in coreboot log: [INFO ] [LVTS_MSR] ts0 msr_all=141d0, msr_temp=16848, temp=41086 [INFO ] lvts_tscpu_thermal_read_tc_temp order 0 ts_name 0 temp 41086 rg_temp 41073(42059) [INFO ] [LVTS_MSR] ts1 msr_all=141e3, msr_temp=16867, temp=41540 [INFO ] lvts_tscpu_thermal_read_tc_temp order 1 ts_name 1 temp 41540 rg_temp 41526(42523) [INFO ] [LVTS_MSR] ts2 msr_all=14199, msr_temp=16793, temp=39772[0m [INFO ] lvts_tscpu_thermal_read_tc_temp order 2 ts_name 2 temp 39772 rg_temp 39760(40715) [INFO ] [LVTS_MSR] ts3 msr_all=141c2, msr_temp=16834, temp=40751 [INFO ] lvts_tscpu_thermal_read_tc_temp order 3 ts_name 3 temp 40751 rg_temp 40739(41717) [INFO ] [LVTS_MSR] ts4 msr_all=141d0, msr_temp=16848, temp=41086 [INFO ] lvts_tscpu_thermal_read_tc_temp order 0 ts_name 4 temp 41086 rg_temp 41073(42059) [INFO ] [LVTS_MSR] ts5 msr_all=141b3, msr_temp=16819, temp=40393 [INFO ] lvts_tscpu_thermal_read_tc_temp order 1 ts_name 5 temp 40393 rg_temp 40380(41350) [INFO ] [LVTS_MSR] ts6 msr_all=14194, msr_temp=16788, temp=39652 [INFO ] lvts_tscpu_thermal_read_tc_temp order 2 ts_name 6 temp 39652 rg_temp 39641(40593) [INFO ] [LVTS_MSR] ts7 msr_all=14186, msr_temp=16774, temp=39318 [INFO ] lvts_tscpu_thermal_read_tc_temp order 3 ts_name 7 temp 39318 rg_temp 39307(40251) Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Change-Id: Ia7361edd7f75b82fff4241ec94488ed1ef07346f --- M src/soc/mediatek/mt8196/include/soc/thermal_internal.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/86552/1 diff --git a/src/soc/mediatek/mt8196/include/soc/thermal_internal.h b/src/soc/mediatek/mt8196/include/soc/thermal_internal.h index b584117..55c300d 100644 --- a/src/soc/mediatek/mt8196/include/soc/thermal_internal.h +++ b/src/soc/mediatek/mt8196/include/soc/thermal_internal.h @@ -171,8 +171,8 @@ #define AP_RST_SET (INFRACFG_AO_SEC_BASE + 0xf30) #define AP_RST_CLR (INFRACFG_AO_SEC_BASE + 0xf34) -#define LVTS_COF_T_SLP_GLD 358830 -#define LVTS_COF_COUNT_R_GLD 34389 +#define LVTS_COF_T_SLP_GLD 391460 +#define LVTS_COF_COUNT_R_GLD 34412 #define LVTS_COF_T_CONST_OFS 0 #define DEFAULT_EFUSE_GOLDEN_TEMP 60 -- To view, visit https://review.coreboot.org/c/coreboot/+/86552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7361edd7f75b82fff4241ec94488ed1ef07346f Gerrit-Change-Number: 86552 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Save HW protect temperature to SRAM
by Jarried Lin (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Zhaoqing Jiu. Hello Zhaoqing Jiu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/86551?usp=email to review the following change. Change subject: soc/mediatek/mt8196: Save HW protect temperature to SRAM ...................................................................... soc/mediatek/mt8196: Save HW protect temperature to SRAM It will restore the HW protection settings based on the data saved in the SRAM, after the system suspends and resumes. BRANCH=rauru BUG=b:389026545 TEST=Boot up and check temperature in coreboot log: [INFO ] [LVTS_MSR] ts0 msr_all=141d0, msr_temp=16848, temp=41086 [INFO ] lvts_tscpu_thermal_read_tc_temp order 0 ts_name 0 temp 41086 rg_temp 41073(42059) [INFO ] [LVTS_MSR] ts1 msr_all=141e3, msr_temp=16867, temp=41540 [INFO ] lvts_tscpu_thermal_read_tc_temp order 1 ts_name 1 temp 41540 rg_temp 41526(42523) [INFO ] [LVTS_MSR] ts2 msr_all=14199, msr_temp=16793, temp=39772[0m [INFO ] lvts_tscpu_thermal_read_tc_temp order 2 ts_name 2 temp 39772 rg_temp 39760(40715) [INFO ] [LVTS_MSR] ts3 msr_all=141c2, msr_temp=16834, temp=40751 [INFO ] lvts_tscpu_thermal_read_tc_temp order 3 ts_name 3 temp 40751 rg_temp 40739(41717) [INFO ] [LVTS_MSR] ts4 msr_all=141d0, msr_temp=16848, temp=41086 [INFO ] lvts_tscpu_thermal_read_tc_temp order 0 ts_name 4 temp 41086 rg_temp 41073(42059) [INFO ] [LVTS_MSR] ts5 msr_all=141b3, msr_temp=16819, temp=40393 [INFO ] lvts_tscpu_thermal_read_tc_temp order 1 ts_name 5 temp 40393 rg_temp 40380(41350) [INFO ] [LVTS_MSR] ts6 msr_all=14194, msr_temp=16788, temp=39652 [INFO ] lvts_tscpu_thermal_read_tc_temp order 2 ts_name 6 temp 39652 rg_temp 39641(40593) [INFO ] [LVTS_MSR] ts7 msr_all=14186, msr_temp=16774, temp=39318 [INFO ] lvts_tscpu_thermal_read_tc_temp order 3 ts_name 7 temp 39318 rg_temp 39307(40251) Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Change-Id: Ib714c297871132907e286536c4b3aea1532f3869 --- M src/soc/mediatek/mt8196/include/soc/thermal.h M src/soc/mediatek/mt8196/thermal.c M src/soc/mediatek/mt8196/thermal_sram.c 3 files changed, 34 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/86551/1 diff --git a/src/soc/mediatek/mt8196/include/soc/thermal.h b/src/soc/mediatek/mt8196/include/soc/thermal.h index 6d2b523..1517b37 100644 --- a/src/soc/mediatek/mt8196/include/soc/thermal.h +++ b/src/soc/mediatek/mt8196/include/soc/thermal.h @@ -5,5 +5,7 @@ void thermal_sram_init(void); void thermal_init(void); +void thermal_write_reboot_temp_sram(int value); +void thermal_write_reboot_msr_sram(int idx, int value); #endif /* SOC_MEDIATEK_MT8196_THERMAL_H */ diff --git a/src/soc/mediatek/mt8196/thermal.c b/src/soc/mediatek/mt8196/thermal.c index 001cd06..be7fece 100644 --- a/src/soc/mediatek/mt8196/thermal.c +++ b/src/soc/mediatek/mt8196/thermal.c @@ -575,12 +575,14 @@ write32p(AP_RST_CLR, BIT(11)); } -static void lvts_set_tc_trigger_hw_protect(const struct lvts_thermal_controller *tc) +static void lvts_set_tc_trigger_hw_protect(unsigned int tc_num) { int d_index, i; uint32_t raw_high; uint16_t raw; enum lvts_sensor ts_name; + int tc_index = 0xFF; + const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[tc_num]; if (tc->dominator_ts_idx < tc->ts_number) { d_index = tc->dominator_ts_idx; @@ -601,6 +603,16 @@ raw = lvts_temp_to_raw(tc->reboot_temperature, ts_name); raw_high = MAX(raw_high, raw); } + if (tc_num == LVTS_AP_CONTROLLER0) + tc_index = 0; + else if (tc_num == LVTS_AP_CONTROLLER1) + tc_index = 1; + + if (tc_index != 0xff) { + thermal_write_reboot_msr_sram(tc_index, raw_high); + if (tc_index == 0) + thermal_write_reboot_temp_sram(tc->reboot_temperature); + } setbits32(&tc->regs->lvtsprotctl_0, 0x3FFF); /* disable trigger SPM interrupt */ @@ -623,11 +635,10 @@ printk(BIOS_INFO, "===== %s begin ======\n", __func__); for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) { - const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i]; - if (tc->ctrl_on_off == CTRL_OFF) + if ((&lvts_tscpu_g_tc[i])->ctrl_on_off == CTRL_OFF) continue; - lvts_set_tc_trigger_hw_protect(tc); + lvts_set_tc_trigger_hw_protect(i); } } diff --git a/src/soc/mediatek/mt8196/thermal_sram.c b/src/soc/mediatek/mt8196/thermal_sram.c index 5509792..23500cb 100644 --- a/src/soc/mediatek/mt8196/thermal_sram.c +++ b/src/soc/mediatek/mt8196/thermal_sram.c @@ -7,6 +7,9 @@ /* SRAM for Thermal */ #define THERMAL_SRAM_BASE (_mcufw_reserved + 0x1000) #define THERMAL_SRAM_LEN 0x400 +#define THERMAL_REBOOT_TEMP_SRAM_OFFSET 0x39c +#define THERMAL_REBOOT_MSR_SRAM_OFFSET 0x340 +#define THERMAL_REBOOT_MSR_SRAM_LEN (6 * 4) static void thermal_cls_sram(void) { @@ -59,3 +62,17 @@ thermal_stat_cls_sram(); thermal_gpu_stat_cls_sram(); } + +void thermal_write_reboot_temp_sram(int value) +{ + write32(THERMAL_SRAM_BASE + THERMAL_REBOOT_TEMP_SRAM_OFFSET, value); +} + +void thermal_write_reboot_msr_sram(int idx, int value) +{ + unsigned int offset = 0; + if ((idx * 4) < THERMAL_REBOOT_MSR_SRAM_LEN) { + offset = THERMAL_REBOOT_MSR_SRAM_OFFSET + idx * 4; + write32(THERMAL_SRAM_BASE + offset, value); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86551?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib714c297871132907e286536c4b3aea1532f3869 Gerrit-Change-Number: 86551 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com>

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[S] Change in coreboot[main]: libpayload/tests: Remove unused test files
by Elyes Haouas (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Elyes Haouas, Jakub "Kuba" Czapiga, Maximilian Brune. Hello Jakub "Kuba" Czapiga, Maximilian Brune, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86536?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Jakub "Kuba" Czapiga, Code-Review+2 by Maximilian Brune, Verified+1 by build bot (Jenkins) Change subject: libpayload/tests: Remove unused test files ...................................................................... libpayload/tests: Remove unused test files Change-Id: Id2cec6a56ba5ce98832aced6fc2cfd8ebda91f02 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- D payloads/libpayload/tests/Makefile D payloads/libpayload/tests/cbfs-x86-test.c 2 files changed, 0 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/86536/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86536?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id2cec6a56ba5ce98832aced6fc2cfd8ebda91f02 Gerrit-Change-Number: 86536 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: mb/google/nissa/var/dirks: Add fw_config probe for WIFI Type
by David Wu (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. David Wu has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/86540?usp=email ) Change subject: mb/google/nissa/var/dirks: Add fw_config probe for WIFI Type ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/dirks/overridetree.cb: https://review.coreboot.org/c/coreboot/+/86540/comment/1208337a_8cad4eb8?us… : PS1, Line 7: WIFI_ALL > oh I mean change to WIFI_DEFAULT is better. It is to align with the project configurations (config.star). Thanks. https://chrome-internal.googlesource.com/chromeos/project/nissa/dirks/+/ref… -- To view, visit https://review.coreboot.org/c/coreboot/+/86540?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaefda61e4929d48f02ce7190e9e45d70b32b75e3 Gerrit-Change-Number: 86540 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 21 Feb 2025 05:43:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com>

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[S] Change in coreboot[main]: mb/google/auron: Clean up Kconfig selections
by 9elements QA (Code Review) 20 Feb '25

20 Feb '25

9elements QA has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/86455?usp=email ) Change subject: mb/google/auron: Clean up Kconfig selections ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/233867 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/233865 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/233864 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/233863 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/233862 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/233861 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/233860 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/233859 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/233858 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/233857 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/233856 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/233855 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/86455?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0d28bc496ff6bcfa9947a4d15ed2d8f75cf74ac3 Gerrit-Change-Number: 86455 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 21 Feb 2025 04:34:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/nissa/var/dirks: Add fw_config probe for WIFI Type
by Eric Lai (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: David Wu, Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/86540?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/nissa/var/dirks: Add fw_config probe for WIFI Type ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/mainboard/google/brya/variants/dirks/overridetree.cb: https://review.coreboot.org/c/coreboot/+/86540/comment/4289a2c0_6dd2795e?us… : PS1, Line 7: WIFI_ALL oh I mean change to WIFI_DEFAULT is better. -- To view, visit https://review.coreboot.org/c/coreboot/+/86540?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaefda61e4929d48f02ce7190e9e45d70b32b75e3 Gerrit-Change-Number: 86540 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 21 Feb 2025 03:19:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: Enable CNVi wifi core
by Subrata Banik (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N, Tongtong Pan, Weimin Wu. Subrata Banik has posted comments on this change by Tongtong Pan. ( https://review.coreboot.org/c/coreboot/+/86549?usp=email ) Change subject: mb/google/fatcat/var/felino: Enable CNVi wifi core ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86549?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib5a98dc481b0c64612ffd50242262714f114b5b7 Gerrit-Change-Number: 86549 Gerrit-PatchSet: 1 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 21 Feb 2025 02:56:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: Enable CNVi wifi core
by Tongtong Pan (Code Review) 20 Feb '25

20 Feb '25

Tongtong Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86549?usp=email ) Change subject: mb/google/fatcat/var/felino: Enable CNVi wifi core ...................................................................... mb/google/fatcat/var/felino: Enable CNVi wifi core Enable CNVi wifi core for felino. BUG=b:388982526 TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino Change-Id: Ib5a98dc481b0c64612ffd50242262714f114b5b7 Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/fatcat/variants/felino/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/86549/1 diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb index 66a8a74..04cfa28 100644 --- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb @@ -28,6 +28,9 @@ .tdp_pl2_override = 25, }" + # Enable CNVi WiFi + register "cnvi_wifi_core" = "true" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 # USB HUB (USB2 Camera) -- To view, visit https://review.coreboot.org/c/coreboot/+/86549?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib5a98dc481b0c64612ffd50242262714f114b5b7 Gerrit-Change-Number: 86549 Gerrit-PatchSet: 1 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com>

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